arch/ppc/kernel/cputable.c

   1 /*
   2  *  arch/ppc/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/threads.h>
  16 #include <linux/init.h>
  17 #include <asm/cputable.h>
  18
  19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
  20
  21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  35
  36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  37                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
  38                      !defined(CONFIG_BOOKE))
  39
  40 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  41  * ones as well...
  42  */
  43 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  44                          PPC_FEATURE_HAS_MMU)
  45
  46 /* We only set the altivec features if the kernel was compiled with altivec
  47  * support
  48  */
  49 #ifdef CONFIG_ALTIVEC
  50 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
  51 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
  52 #else
  53 #define CPU_FTR_ALTIVEC_COMP            0
  54 #define PPC_FEATURE_ALTIVEC_COMP        0
  55 #endif
  56
  57 /* We need to mark all pages as being coherent if we're SMP or we
  58  * have a 754x and an MPC107 host bridge. */
  59 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
  60 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  61 #else
  62 #define CPU_FTR_COMMON                  0
  63 #endif
  64
  65 struct cpu_spec cpu_specs[] = {
  66 #if CLASSIC_PPC
  67     {   /* 601 */
  68         0xffff0000, 0x00010000, "601",
  69         CPU_FTR_COMMON |
  70         CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
  71         COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
  72         32, 32,
  73         __setup_cpu_601
  74     },
  75     {   /* 603 */
  76         0xffff0000, 0x00030000, "603",
  77         CPU_FTR_COMMON |
  78         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  79         CPU_FTR_CAN_NAP,
  80         COMMON_PPC,
  81         32, 32,
  82         __setup_cpu_603
  83     },
  84     {   /* 603e */
  85         0xffff0000, 0x00060000, "603e",
  86         CPU_FTR_COMMON |
  87         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  88         CPU_FTR_CAN_NAP,
  89         COMMON_PPC,
  90         32, 32,
  91         __setup_cpu_603
  92     },
  93     {   /* 603ev */
  94         0xffff0000, 0x00070000, "603ev",
  95         CPU_FTR_COMMON |
  96         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  97         CPU_FTR_CAN_NAP,
  98         COMMON_PPC,
  99         32, 32,
 100         __setup_cpu_603
 101     },
 102     {   /* 604 */
 103         0xffff0000, 0x00040000, "604",
 104         CPU_FTR_COMMON |
 105         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 106         CPU_FTR_HPTE_TABLE,
 107         COMMON_PPC,
 108         32, 32,
 109         __setup_cpu_604
 110     },
 111     {   /* 604e */
 112         0xfffff000, 0x00090000, "604e",
 113         CPU_FTR_COMMON |
 114         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 115         CPU_FTR_HPTE_TABLE,
 116         COMMON_PPC,
 117         32, 32,
 118         __setup_cpu_604
 119     },
 120     {   /* 604r */
 121         0xffff0000, 0x00090000, "604r",
 122         CPU_FTR_COMMON |
 123         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 124         CPU_FTR_HPTE_TABLE,
 125         COMMON_PPC,
 126         32, 32,
 127         __setup_cpu_604
 128     },
 129     {   /* 604ev */
 130         0xffff0000, 0x000a0000, "604ev",
 131         CPU_FTR_COMMON |
 132         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 133         CPU_FTR_HPTE_TABLE,
 134         COMMON_PPC,
 135         32, 32,
 136         __setup_cpu_604
 137     },
 138     {   /* 740/750 (0x4202, don't support TAU ?) */
 139         0xffffffff, 0x00084202, "740/750",
 140         CPU_FTR_COMMON |
 141         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 142         CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 143         COMMON_PPC,
 144         32, 32,
 145         __setup_cpu_750
 146     },
 147     {   /* 745/755 */
 148         0xfffff000, 0x00083000, "745/755",
 149         CPU_FTR_COMMON |
 150         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 151         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 152         COMMON_PPC,
 153         32, 32,
 154         __setup_cpu_750
 155     },
 156     {   /* 750CX (80100 and 8010x?) */
 157         0xfffffff0, 0x00080100, "750CX",
 158         CPU_FTR_COMMON |
 159         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 160         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 161         COMMON_PPC,
 162         32, 32,
 163         __setup_cpu_750cx
 164     },
 165     {   /* 750CX (82201 and 82202) */
 166         0xfffffff0, 0x00082200, "750CX",
 167         CPU_FTR_COMMON |
 168         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 169         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 170         COMMON_PPC,
 171         32, 32,
 172         __setup_cpu_750cx
 173     },
 174     {   /* 750CXe (82214) */
 175         0xfffffff0, 0x00082210, "750CXe",
 176         CPU_FTR_COMMON |
 177         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 178         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 179         COMMON_PPC,
 180         32, 32,
 181         __setup_cpu_750cx
 182     },
 183     {   /* 750FX rev 1.x */
 184         0xffffff00, 0x70000100, "750FX",
 185         CPU_FTR_COMMON |
 186         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 187         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 188         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 189         COMMON_PPC,
 190         32, 32,
 191         __setup_cpu_750
 192     },
 193     {   /* 750FX rev 2.0 must disable HID0[DPM] */
 194         0xffffffff, 0x70000200, "750FX",
 195         CPU_FTR_COMMON |
 196         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 197         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 198         CPU_FTR_NO_DPM,
 199         COMMON_PPC,
 200         32, 32,
 201         __setup_cpu_750
 202     },
 203     {   /* 750FX (All revs except 2.0) */
 204         0xffff0000, 0x70000000, "750FX",
 205         CPU_FTR_COMMON |
 206         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 207         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 208         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 209         COMMON_PPC,
 210         32, 32,
 211         __setup_cpu_750fx
 212     },
 213     {   /* 750GX */
 214         0xffff0000, 0x70020000, "750GX",
 215         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 216         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 217         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 218         COMMON_PPC,
 219         32, 32,
 220         __setup_cpu_750fx
 221     },
 222     {   /* 740/750 (L2CR bit need fixup for 740) */
 223         0xffff0000, 0x00080000, "740/750",
 224         CPU_FTR_COMMON |
 225         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 226         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 227         COMMON_PPC,
 228         32, 32,
 229         __setup_cpu_750
 230     },
 231     {   /* 7400 rev 1.1 ? (no TAU) */
 232         0xffffffff, 0x000c1101, "7400 (1.1)",
 233         CPU_FTR_COMMON |
 234         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 235         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 236         CPU_FTR_CAN_NAP,
 237         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 238         32, 32,
 239         __setup_cpu_7400
 240     },
 241     {   /* 7400 */
 242         0xffff0000, 0x000c0000, "7400",
 243         CPU_FTR_COMMON |
 244         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 245         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 246         CPU_FTR_CAN_NAP,
 247         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 248         32, 32,
 249         __setup_cpu_7400
 250     },
 251     {   /* 7410 */
 252         0xffff0000, 0x800c0000, "7410",
 253         CPU_FTR_COMMON |
 254         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 255         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 256         CPU_FTR_CAN_NAP,
 257         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 258         32, 32,
 259         __setup_cpu_7410
 260     },
 261     {   /* 7450 2.0 - no doze/nap */
 262         0xffffffff, 0x80000200, "7450",
 263         CPU_FTR_COMMON |
 264         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 265         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 266         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
 267         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 268         32, 32,
 269         __setup_cpu_745x
 270     },
 271     {   /* 7450 2.1 */
 272         0xffffffff, 0x80000201, "7450",
 273         CPU_FTR_COMMON |
 274         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 275         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 276         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 277         CPU_FTR_L3_DISABLE_NAP,
 278         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 279         32, 32,
 280         __setup_cpu_745x
 281     },
 282     {   /* 7450 2.3 and newer */
 283         0xffff0000, 0x80000000, "7450",
 284         CPU_FTR_COMMON |
 285         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 286         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 287         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
 288         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 289         32, 32,
 290         __setup_cpu_745x
 291     },
 292     {   /* 7455 rev 1.x */
 293         0xffffff00, 0x80010100, "7455",
 294         CPU_FTR_COMMON |
 295         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 296         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 297         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
 298         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 299         32, 32,
 300         __setup_cpu_745x
 301     },
 302     {   /* 7455 rev 2.0 */
 303         0xffffffff, 0x80010200, "7455",
 304         CPU_FTR_COMMON |
 305         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 306         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 307         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 308         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
 309         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 310         32, 32,
 311         __setup_cpu_745x
 312     },
 313     {   /* 7455 others */
 314         0xffff0000, 0x80010000, "7455",
 315         CPU_FTR_COMMON |
 316         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 317         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 318         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 319         CPU_FTR_HAS_HIGH_BATS,
 320         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 321         32, 32,
 322         __setup_cpu_745x
 323     },
 324     {   /* 7457 */
 325         0xffff0000, 0x80020000, "7457",
 326         CPU_FTR_COMMON |
 327         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 328         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 329         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 330         CPU_FTR_HAS_HIGH_BATS,
 331         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 332         32, 32,
 333         __setup_cpu_745x
 334     },
 335     {   /* 7447A */
 336         0xffff0000, 0x80030000, "7447A",
 337         CPU_FTR_COMMON |
 338         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 339         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 340         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 341         CPU_FTR_HAS_HIGH_BATS,
 342         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 343         32, 32,
 344         __setup_cpu_745x
 345     },
 346     {   /* 82xx (8240, 8245, 8260 are all 603e cores) */
 347         0x7fff0000, 0x00810000, "82xx",
 348         CPU_FTR_COMMON |
 349         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
 350         COMMON_PPC,
 351         32, 32,
 352         __setup_cpu_603
 353     },
 354     {   /* 8280 is a G2_LE (603e core, plus some) */
 355         0x7fff0000, 0x00820000, "8280",
 356         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 357         CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 358         COMMON_PPC,
 359         32, 32,
 360         __setup_cpu_603
 361     },
 362     {   /* default match, we assume split I/D cache & TB (non-601)... */
 363         0x00000000, 0x00000000, "(generic PPC)",
 364         CPU_FTR_COMMON |
 365         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 366         COMMON_PPC,
 367         32, 32,
 368         __setup_cpu_generic
 369     },
 370 #endif /* CLASSIC_PPC */
 371 #ifdef CONFIG_PPC64BRIDGE
 372     {   /* Power3 */
 373         0xffff0000, 0x00400000, "Power3 (630)",
 374         CPU_FTR_COMMON |
 375         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 376         COMMON_PPC | PPC_FEATURE_64,
 377         128, 128,
 378         __setup_cpu_power3
 379     },
 380     {   /* Power3+ */
 381         0xffff0000, 0x00410000, "Power3 (630+)",
 382         CPU_FTR_COMMON |
 383         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 384         COMMON_PPC | PPC_FEATURE_64,
 385         128, 128,
 386         __setup_cpu_power3
 387     },
 388         {       /* I-star */
 389                 0xffff0000, 0x00360000, "I-star",
 390                 CPU_FTR_COMMON |
 391                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 392                 COMMON_PPC | PPC_FEATURE_64,
 393                 128, 128,
 394                 __setup_cpu_power3
 395         },
 396         {       /* S-star */
 397                 0xffff0000, 0x00370000, "S-star",
 398                 CPU_FTR_COMMON |
 399                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 400                 COMMON_PPC | PPC_FEATURE_64,
 401                 128, 128,
 402                 __setup_cpu_power3
 403         },
 404 #endif /* CONFIG_PPC64BRIDGE */
 405 #ifdef CONFIG_POWER4
 406     {   /* Power4 */
 407         0xffff0000, 0x00350000, "Power4",
 408         CPU_FTR_COMMON |
 409         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 410         COMMON_PPC | PPC_FEATURE_64,
 411         128, 128,
 412         __setup_cpu_power4
 413     },
 414     {   /* PPC970 */
 415         0xffff0000, 0x00390000, "PPC970",
 416         CPU_FTR_COMMON |
 417         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 418         CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
 419         COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 420         128, 128,
 421         __setup_cpu_ppc970
 422     },
 423 #endif /* CONFIG_POWER4 */
 424 #ifdef CONFIG_8xx
 425     {   /* 8xx */
 426         0xffff0000, 0x00500000, "8xx",
 427                 /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
 428         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 429         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 430         16, 16,
 431         __setup_cpu_8xx /* Empty */
 432     },
 433 #endif /* CONFIG_8xx */
 434 #ifdef CONFIG_40x
 435     {   /* 403GC */
 436         0xffffff00, 0x00200200, "403GC",
 437         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 438         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 439         16, 16,
 440         0, /*__setup_cpu_403 */
 441     },
 442     {   /* 403GCX */
 443         0xffffff00, 0x00201400, "403GCX",
 444         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 445         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 446         16, 16,
 447         0, /*__setup_cpu_403 */
 448     },
 449     {   /* 403G ?? */
 450         0xffff0000, 0x00200000, "403G ??",
 451         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 452         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 453         16, 16,
 454         0, /*__setup_cpu_403 */
 455     },
 456     {   /* 405GP */
 457         0xffff0000, 0x40110000, "405GP",
 458         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 459         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 460         32, 32,
 461         0, /*__setup_cpu_405 */
 462     },
 463     {   /* STB 03xxx */
 464         0xffff0000, 0x40130000, "STB03xxx",
 465         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 466         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 467         32, 32,
 468         0, /*__setup_cpu_405 */
 469     },
 470     {   /* STB 04xxx */
 471         0xffff0000, 0x41810000, "STB04xxx",
 472         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 473         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 474         32, 32,
 475         0, /*__setup_cpu_405 */
 476     },
 477     {   /* NP405L */
 478         0xffff0000, 0x41610000, "NP405L",
 479         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 480         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 481         32, 32,
 482         0, /*__setup_cpu_405 */
 483     },
 484     {   /* NP4GS3 */
 485         0xffff0000, 0x40B10000, "NP4GS3",
 486         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 487         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 488         32, 32,
 489         0, /*__setup_cpu_405 */
 490     },
 491     {   /* NP405H */
 492         0xffff0000, 0x41410000, "NP405H",
 493         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 494         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 495         32, 32,
 496         0, /*__setup_cpu_405 */
 497      },
 498      {  /* 405GPr */
 499         0xffff0000, 0x50910000, "405GPr",
 500         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 501         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 502         32, 32,
 503         0, /*__setup_cpu_405 */
 504     },
 505     {   /* STBx25xx */
 506         0xffff0000, 0x51510000, "STBx25xx",
 507         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 508         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 509         32, 32,
 510         0, /*__setup_cpu_405 */
 511      },
 512      {  /* 405LP */
 513         0xffff0000, 0x41F10000, "405LP",
 514         CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
 515         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 516         32, 32,
 517         0, /*__setup_cpu_405 */
 518      },
 519      {  /* Xilinx Virtex-II Pro  */
 520         0xffff0000, 0x20010000, "Virtex-II Pro",
 521         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 522         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 523         32, 32,
 524         0, /*__setup_cpu_405 */
 525      },
 526
 527 #endif /* CONFIG_40x */
 528 #ifdef CONFIG_44x
 529     { /* 440GP Rev. B */
 530         0xf0000fff, 0x40000440, "440GP Rev. B",
 531         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 532         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 533         32, 32,
 534         0, /*__setup_cpu_440 */
 535     },
 536     { /* 440GP Rev. C */
 537         0xf0000fff, 0x40000481, "440GP Rev. C",
 538         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 539         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 540         32, 32,
 541         0, /*__setup_cpu_440 */
 542     },
 543     { /* 440GX Rev. A */
 544         0xf0000fff, 0x50000850, "440GX Rev. A",
 545         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 546         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 547         32, 32,
 548         0, /*__setup_cpu_440 */
 549     },
 550     { /* 440GX Rev. B */
 551         0xf0000fff, 0x50000851, "440GX Rev. B",
 552         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 553         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 554         32, 32,
 555         0, /*__setup_cpu_440 */
 556     },
 557     { /* 440GX Rev. C */
 558         0xf0000fff, 0x50000892, "440GX Rev. C",
 559         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 560         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 561         32, 32,
 562         0, /*__setup_cpu_440 */
 563     },
 564 #endif /* CONFIG_44x */
 565 #ifdef CONFIG_E500
 566     { /* e500 */
 567         0xffff0000, 0x80200000, "e500",
 568         /* xxx - galak: add CPU_FTR_CAN_DOZE */
 569         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 570         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 571         32, 32,
 572         0, /*__setup_cpu_e500 */
 573     },
 574 #endif
 575 #if !CLASSIC_PPC
 576     {   /* default match */
 577         0x00000000, 0x00000000, "(generic PPC)",
 578         CPU_FTR_COMMON,
 579         PPC_FEATURE_32,
 580         32, 32,
 581         0,
 582     }
 583 #endif /* !CLASSIC_PPC */
 584 };