arch/ppc/kernel/cputable.c

   1 /*
   2  *  arch/ppc/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/threads.h>
  16 #include <linux/init.h>
  17 #include <asm/cputable.h>
  18
  19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
  20
  21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  35
  36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  37                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
  38                      !defined(CONFIG_BOOKE))
  39
  40 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  41  * ones as well...
  42  */
  43 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  44                          PPC_FEATURE_HAS_MMU)
  45
  46 /* We only set the altivec features if the kernel was compiled with altivec
  47  * support
  48  */
  49 #ifdef CONFIG_ALTIVEC
  50 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
  51 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
  52 #else
  53 #define CPU_FTR_ALTIVEC_COMP            0
  54 #define PPC_FEATURE_ALTIVEC_COMP        0
  55 #endif
  56
  57 /* We need to mark all pages as being coherent if we're SMP or we
  58  * have a 74[45]x and an MPC107 host bridge.
  59  */
  60 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
  61 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  62 #else
  63 #define CPU_FTR_COMMON                  0
  64 #endif
  65
  66 /* The powersave features NAP & DOZE seems to confuse BDI when
  67    debugging. So if a BDI is used, disable theses
  68  */
  69 #ifndef CONFIG_BDI_SWITCH
  70 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
  71 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
  72 #else
  73 #define CPU_FTR_MAYBE_CAN_DOZE  0
  74 #define CPU_FTR_MAYBE_CAN_NAP   0
  75 #endif
  76
  77 struct cpu_spec cpu_specs[] = {
  78 #if CLASSIC_PPC
  79     {   /* 601 */
  80         0xffff0000, 0x00010000, "601",
  81         CPU_FTR_COMMON |
  82         CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
  83         COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
  84         32, 32,
  85         __setup_cpu_601
  86     },
  87     {   /* 603 */
  88         0xffff0000, 0x00030000, "603",
  89         CPU_FTR_COMMON |
  90         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
  91         CPU_FTR_MAYBE_CAN_NAP,
  92         COMMON_PPC,
  93         32, 32,
  94         __setup_cpu_603
  95     },
  96     {   /* 603e */
  97         0xffff0000, 0x00060000, "603e",
  98         CPU_FTR_COMMON |
  99         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 100         CPU_FTR_MAYBE_CAN_NAP,
 101         COMMON_PPC,
 102         32, 32,
 103         __setup_cpu_603
 104     },
 105     {   /* 603ev */
 106         0xffff0000, 0x00070000, "603ev",
 107         CPU_FTR_COMMON |
 108         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 109         CPU_FTR_MAYBE_CAN_NAP,
 110         COMMON_PPC,
 111         32, 32,
 112         __setup_cpu_603
 113     },
 114     {   /* 604 */
 115         0xffff0000, 0x00040000, "604",
 116         CPU_FTR_COMMON |
 117         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 118         CPU_FTR_HPTE_TABLE,
 119         COMMON_PPC,
 120         32, 32,
 121         __setup_cpu_604
 122     },
 123     {   /* 604e */
 124         0xfffff000, 0x00090000, "604e",
 125         CPU_FTR_COMMON |
 126         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 127         CPU_FTR_HPTE_TABLE,
 128         COMMON_PPC,
 129         32, 32,
 130         __setup_cpu_604
 131     },
 132     {   /* 604r */
 133         0xffff0000, 0x00090000, "604r",
 134         CPU_FTR_COMMON |
 135         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 136         CPU_FTR_HPTE_TABLE,
 137         COMMON_PPC,
 138         32, 32,
 139         __setup_cpu_604
 140     },
 141     {   /* 604ev */
 142         0xffff0000, 0x000a0000, "604ev",
 143         CPU_FTR_COMMON |
 144         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 145         CPU_FTR_HPTE_TABLE,
 146         COMMON_PPC,
 147         32, 32,
 148         __setup_cpu_604
 149     },
 150     {   /* 740/750 (0x4202, don't support TAU ?) */
 151         0xffffffff, 0x00084202, "740/750",
 152         CPU_FTR_COMMON |
 153         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 154         CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 155         COMMON_PPC,
 156         32, 32,
 157         __setup_cpu_750
 158     },
 159     {   /* 745/755 */
 160         0xfffff000, 0x00083000, "745/755",
 161         CPU_FTR_COMMON |
 162         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 163         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 164         COMMON_PPC,
 165         32, 32,
 166         __setup_cpu_750
 167     },
 168     {   /* 750CX (80100 and 8010x?) */
 169         0xfffffff0, 0x00080100, "750CX",
 170         CPU_FTR_COMMON |
 171         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 172         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 173         COMMON_PPC,
 174         32, 32,
 175         __setup_cpu_750cx
 176     },
 177     {   /* 750CX (82201 and 82202) */
 178         0xfffffff0, 0x00082200, "750CX",
 179         CPU_FTR_COMMON |
 180         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 181         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 182         COMMON_PPC,
 183         32, 32,
 184         __setup_cpu_750cx
 185     },
 186     {   /* 750CXe (82214) */
 187         0xfffffff0, 0x00082210, "750CXe",
 188         CPU_FTR_COMMON |
 189         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 190         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 191         COMMON_PPC,
 192         32, 32,
 193         __setup_cpu_750cx
 194     },
 195     {   /* 750FX rev 1.x */
 196         0xffffff00, 0x70000100, "750FX",
 197         CPU_FTR_COMMON |
 198         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 199         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 200         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 201         COMMON_PPC,
 202         32, 32,
 203         __setup_cpu_750
 204     },
 205     {   /* 750FX rev 2.0 must disable HID0[DPM] */
 206         0xffffffff, 0x70000200, "750FX",
 207         CPU_FTR_COMMON |
 208         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 209         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 210         CPU_FTR_NO_DPM,
 211         COMMON_PPC,
 212         32, 32,
 213         __setup_cpu_750
 214     },
 215     {   /* 750FX (All revs except 2.0) */
 216         0xffff0000, 0x70000000, "750FX",
 217         CPU_FTR_COMMON |
 218         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 219         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 220         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 221         COMMON_PPC,
 222         32, 32,
 223         __setup_cpu_750fx
 224     },
 225     {   /* 750GX */
 226         0xffff0000, 0x70020000, "750GX",
 227         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 228         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 229         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 230         COMMON_PPC,
 231         32, 32,
 232         __setup_cpu_750fx
 233     },
 234     {   /* 740/750 (L2CR bit need fixup for 740) */
 235         0xffff0000, 0x00080000, "740/750",
 236         CPU_FTR_COMMON |
 237         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 238         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 239         COMMON_PPC,
 240         32, 32,
 241         __setup_cpu_750
 242     },
 243     {   /* 7400 rev 1.1 ? (no TAU) */
 244         0xffffffff, 0x000c1101, "7400 (1.1)",
 245         CPU_FTR_COMMON |
 246         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 247         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 248         CPU_FTR_MAYBE_CAN_NAP,
 249         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 250         32, 32,
 251         __setup_cpu_7400
 252     },
 253     {   /* 7400 */
 254         0xffff0000, 0x000c0000, "7400",
 255         CPU_FTR_COMMON |
 256         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 257         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 258         CPU_FTR_MAYBE_CAN_NAP,
 259         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 260         32, 32,
 261         __setup_cpu_7400
 262     },
 263     {   /* 7410 */
 264         0xffff0000, 0x800c0000, "7410",
 265         CPU_FTR_COMMON |
 266         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 267         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 268         CPU_FTR_MAYBE_CAN_NAP,
 269         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 270         32, 32,
 271         __setup_cpu_7410
 272     },
 273     {   /* 7450 2.0 - no doze/nap */
 274         0xffffffff, 0x80000200, "7450",
 275         CPU_FTR_COMMON |
 276         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 277         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 278         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
 279         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 280         32, 32,
 281         __setup_cpu_745x
 282     },
 283     {   /* 7450 2.1 */
 284         0xffffffff, 0x80000201, "7450",
 285         CPU_FTR_COMMON |
 286         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 287         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 288         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 289         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
 290         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 291         32, 32,
 292         __setup_cpu_745x
 293     },
 294     {   /* 7450 2.3 and newer */
 295         0xffff0000, 0x80000000, "7450",
 296         CPU_FTR_COMMON |
 297         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 298         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 299         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 300         CPU_FTR_NEED_COHERENT,
 301         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 302         32, 32,
 303         __setup_cpu_745x
 304     },
 305     {   /* 7455 rev 1.x */
 306         0xffffff00, 0x80010100, "7455",
 307         CPU_FTR_COMMON |
 308         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 309         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 310         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
 311         CPU_FTR_NEED_COHERENT,
 312         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 313         32, 32,
 314         __setup_cpu_745x
 315     },
 316     {   /* 7455 rev 2.0 */
 317         0xffffffff, 0x80010200, "7455",
 318         CPU_FTR_COMMON |
 319         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 320         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 321         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 322         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 323         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 324         32, 32,
 325         __setup_cpu_745x
 326     },
 327     {   /* 7455 others */
 328         0xffff0000, 0x80010000, "7455",
 329         CPU_FTR_COMMON |
 330         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 331         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 332         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 333         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 334         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 335         32, 32,
 336         __setup_cpu_745x
 337     },
 338     {   /* 7447/7457 Rev 1.0 */
 339         0xffffffff, 0x80020100, "7447/7457",
 340         CPU_FTR_COMMON |
 341         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 342         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 343         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 344         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 345         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 346         32, 32,
 347         __setup_cpu_745x
 348     },
 349     {   /* 7447/7457 Rev 1.1 */
 350         0xffffffff, 0x80020101, "7447/7457",
 351         CPU_FTR_COMMON |
 352         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 353         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 354         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 355         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 356         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 357         32, 32,
 358         __setup_cpu_745x
 359     },
 360     {   /* 7447/7457 Rev 1.2 and later */
 361         0xffff0000, 0x80020000, "7447/7457",
 362         CPU_FTR_COMMON |
 363         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 364         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 365         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 366         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 367         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 368         32, 32,
 369         __setup_cpu_745x
 370     },
 371     {   /* 7447A */
 372         0xffff0000, 0x80030000, "7447A",
 373         CPU_FTR_COMMON |
 374         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 375         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 376         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 377         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 378         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 379         32, 32,
 380         __setup_cpu_745x
 381     },
 382     {   /* 82xx (8240, 8245, 8260 are all 603e cores) */
 383         0x7fff0000, 0x00810000, "82xx",
 384         CPU_FTR_COMMON |
 385         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
 386         COMMON_PPC,
 387         32, 32,
 388         __setup_cpu_603
 389     },
 390     {   /* All G2_LE (603e core, plus some) have the same pvr */
 391         0x7fff0000, 0x00820000, "G2_LE",
 392         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 393         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 394         COMMON_PPC,
 395         32, 32,
 396         __setup_cpu_603
 397     },
 398     {   /* default match, we assume split I/D cache & TB (non-601)... */
 399         0x00000000, 0x00000000, "(generic PPC)",
 400         CPU_FTR_COMMON |
 401         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 402         COMMON_PPC,
 403         32, 32,
 404         __setup_cpu_generic
 405     },
 406 #endif /* CLASSIC_PPC */
 407 #ifdef CONFIG_PPC64BRIDGE
 408     {   /* Power3 */
 409         0xffff0000, 0x00400000, "Power3 (630)",
 410         CPU_FTR_COMMON |
 411         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 412         COMMON_PPC | PPC_FEATURE_64,
 413         128, 128,
 414         __setup_cpu_power3
 415     },
 416     {   /* Power3+ */
 417         0xffff0000, 0x00410000, "Power3 (630+)",
 418         CPU_FTR_COMMON |
 419         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 420         COMMON_PPC | PPC_FEATURE_64,
 421         128, 128,
 422         __setup_cpu_power3
 423     },
 424         {       /* I-star */
 425                 0xffff0000, 0x00360000, "I-star",
 426                 CPU_FTR_COMMON |
 427                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 428                 COMMON_PPC | PPC_FEATURE_64,
 429                 128, 128,
 430                 __setup_cpu_power3
 431         },
 432         {       /* S-star */
 433                 0xffff0000, 0x00370000, "S-star",
 434                 CPU_FTR_COMMON |
 435                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 436                 COMMON_PPC | PPC_FEATURE_64,
 437                 128, 128,
 438                 __setup_cpu_power3
 439         },
 440 #endif /* CONFIG_PPC64BRIDGE */
 441 #ifdef CONFIG_POWER4
 442     {   /* Power4 */
 443         0xffff0000, 0x00350000, "Power4",
 444         CPU_FTR_COMMON |
 445         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 446         COMMON_PPC | PPC_FEATURE_64,
 447         128, 128,
 448         __setup_cpu_power4
 449     },
 450     {   /* PPC970 */
 451         0xffff0000, 0x00390000, "PPC970",
 452         CPU_FTR_COMMON |
 453         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 454         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
 455         COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 456         128, 128,
 457         __setup_cpu_ppc970
 458     },
 459     {   /* PPC970FX */
 460         0xffff0000, 0x003c0000, "PPC970FX",
 461         CPU_FTR_COMMON |
 462         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 463         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
 464         COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 465         128, 128,
 466         __setup_cpu_ppc970
 467     },
 468 #endif /* CONFIG_POWER4 */
 469 #ifdef CONFIG_8xx
 470     {   /* 8xx */
 471         0xffff0000, 0x00500000, "8xx",
 472                 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
 473                  * if the 8xx code is there.... */
 474         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 475         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 476         16, 16,
 477         __setup_cpu_8xx /* Empty */
 478     },
 479 #endif /* CONFIG_8xx */
 480 #ifdef CONFIG_40x
 481     {   /* 403GC */
 482         0xffffff00, 0x00200200, "403GC",
 483         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 484         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 485         16, 16,
 486         0, /*__setup_cpu_403 */
 487     },
 488     {   /* 403GCX */
 489         0xffffff00, 0x00201400, "403GCX",
 490         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 491         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 492         16, 16,
 493         0, /*__setup_cpu_403 */
 494     },
 495     {   /* 403G ?? */
 496         0xffff0000, 0x00200000, "403G ??",
 497         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 498         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 499         16, 16,
 500         0, /*__setup_cpu_403 */
 501     },
 502     {   /* 405GP */
 503         0xffff0000, 0x40110000, "405GP",
 504         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 505         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 506         32, 32,
 507         0, /*__setup_cpu_405 */
 508     },
 509     {   /* STB 03xxx */
 510         0xffff0000, 0x40130000, "STB03xxx",
 511         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 512         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 513         32, 32,
 514         0, /*__setup_cpu_405 */
 515     },
 516     {   /* STB 04xxx */
 517         0xffff0000, 0x41810000, "STB04xxx",
 518         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 519         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 520         32, 32,
 521         0, /*__setup_cpu_405 */
 522     },
 523     {   /* NP405L */
 524         0xffff0000, 0x41610000, "NP405L",
 525         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 526         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 527         32, 32,
 528         0, /*__setup_cpu_405 */
 529     },
 530     {   /* NP4GS3 */
 531         0xffff0000, 0x40B10000, "NP4GS3",
 532         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 533         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 534         32, 32,
 535         0, /*__setup_cpu_405 */
 536     },
 537     {   /* NP405H */
 538         0xffff0000, 0x41410000, "NP405H",
 539         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 540         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 541         32, 32,
 542         0, /*__setup_cpu_405 */
 543      },
 544      {  /* 405GPr */
 545         0xffff0000, 0x50910000, "405GPr",
 546         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 547         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 548         32, 32,
 549         0, /*__setup_cpu_405 */
 550     },
 551     {   /* STBx25xx */
 552         0xffff0000, 0x51510000, "STBx25xx",
 553         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 554         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 555         32, 32,
 556         0, /*__setup_cpu_405 */
 557      },
 558      {  /* 405LP */
 559         0xffff0000, 0x41F10000, "405LP",
 560         CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
 561         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 562         32, 32,
 563         0, /*__setup_cpu_405 */
 564      },
 565      {  /* Xilinx Virtex-II Pro  */
 566         0xffff0000, 0x20010000, "Virtex-II Pro",
 567         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 568         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 569         32, 32,
 570         0, /*__setup_cpu_405 */
 571      },
 572
 573 #endif /* CONFIG_40x */
 574 #ifdef CONFIG_44x
 575     { /* 440GP Rev. B */
 576         0xf0000fff, 0x40000440, "440GP Rev. B",
 577         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 578         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 579         32, 32,
 580         0, /*__setup_cpu_440 */
 581     },
 582     { /* 440GP Rev. C */
 583         0xf0000fff, 0x40000481, "440GP Rev. C",
 584         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 585         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 586         32, 32,
 587         0, /*__setup_cpu_440 */
 588     },
 589     { /* 440GX Rev. A */
 590         0xf0000fff, 0x50000850, "440GX Rev. A",
 591         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 592         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 593         32, 32,
 594         0, /*__setup_cpu_440 */
 595     },
 596     { /* 440GX Rev. B */
 597         0xf0000fff, 0x50000851, "440GX Rev. B",
 598         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 599         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 600         32, 32,
 601         0, /*__setup_cpu_440 */
 602     },
 603     { /* 440GX Rev. C */
 604         0xf0000fff, 0x50000892, "440GX Rev. C",
 605         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 606         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 607         32, 32,
 608         0, /*__setup_cpu_440 */
 609     },
 610 #endif /* CONFIG_44x */
 611 #ifdef CONFIG_E500
 612     { /* e500 */
 613         0xffff0000, 0x80200000, "e500",
 614         /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
 615         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 616         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 617         32, 32,
 618         0, /*__setup_cpu_e500 */
 619     },
 620 #endif
 621 #if !CLASSIC_PPC
 622     {   /* default match */
 623         0x00000000, 0x00000000, "(generic PPC)",
 624         CPU_FTR_COMMON,
 625         PPC_FEATURE_32,
 626         32, 32,
 627         0,
 628     }
 629 #endif /* !CLASSIC_PPC */
 630 };