arch/ppc/kernel/cputable.c

   1 /*
   2  *  arch/ppc/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/threads.h>
  16 #include <linux/init.h>
  17 #include <asm/cputable.h>
  18
  19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
  20
  21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  35
  36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  37                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4))
  38
  39 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  40  * ones as well...
  41  */
  42 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  43                          PPC_FEATURE_HAS_MMU)
  44
  45 /* We only set the altivec features if the kernel was compiled with altivec
  46  * support
  47  */
  48 #ifdef CONFIG_ALTIVEC
  49 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
  50 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
  51 #else
  52 #define CPU_FTR_ALTIVEC_COMP            0
  53 #define PPC_FEATURE_ALTIVEC_COMP        0
  54 #endif
  55
  56 /* We need to mark all pages as being coherent if we're SMP or we
  57  * have a 754x and an MPC107 host bridge. */
  58 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
  59 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  60 #else
  61 #define CPU_FTR_COMMON                  0
  62 #endif
  63
  64 struct cpu_spec cpu_specs[] = {
  65 #if CLASSIC_PPC
  66     {   /* 601 */
  67         0xffff0000, 0x00010000, "601",
  68         CPU_FTR_COMMON |
  69         CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
  70         COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
  71         32, 32,
  72         __setup_cpu_601
  73     },
  74     {   /* 603 */
  75         0xffff0000, 0x00030000, "603",
  76         CPU_FTR_COMMON |
  77         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  78         CPU_FTR_CAN_NAP,
  79         COMMON_PPC,
  80         32, 32,
  81         __setup_cpu_603
  82     },
  83     {   /* 603e */
  84         0xffff0000, 0x00060000, "603e",
  85         CPU_FTR_COMMON |
  86         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  87         CPU_FTR_CAN_NAP,
  88         COMMON_PPC,
  89         32, 32,
  90         __setup_cpu_603
  91     },
  92     {   /* 603ev */
  93         0xffff0000, 0x00070000, "603ev",
  94         CPU_FTR_COMMON |
  95         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  96         CPU_FTR_CAN_NAP,
  97         COMMON_PPC,
  98         32, 32,
  99         __setup_cpu_603
 100     },
 101     {   /* 604 */
 102         0xffff0000, 0x00040000, "604",
 103         CPU_FTR_COMMON |
 104         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 105         CPU_FTR_HPTE_TABLE,
 106         COMMON_PPC,
 107         32, 32,
 108         __setup_cpu_604
 109     },
 110     {   /* 604e */
 111         0xfffff000, 0x00090000, "604e",
 112         CPU_FTR_COMMON |
 113         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 114         CPU_FTR_HPTE_TABLE,
 115         COMMON_PPC,
 116         32, 32,
 117         __setup_cpu_604
 118     },
 119     {   /* 604r */
 120         0xffff0000, 0x00090000, "604r",
 121         CPU_FTR_COMMON |
 122         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 123         CPU_FTR_HPTE_TABLE,
 124         COMMON_PPC,
 125         32, 32,
 126         __setup_cpu_604
 127     },
 128     {   /* 604ev */
 129         0xffff0000, 0x000a0000, "604ev",
 130         CPU_FTR_COMMON |
 131         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 132         CPU_FTR_HPTE_TABLE,
 133         COMMON_PPC,
 134         32, 32,
 135         __setup_cpu_604
 136     },
 137     {   /* 740/750 (0x4202, don't support TAU ?) */
 138         0xffffffff, 0x00084202, "740/750",
 139         CPU_FTR_COMMON |
 140         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 141         CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 142         COMMON_PPC,
 143         32, 32,
 144         __setup_cpu_750
 145     },
 146     {   /* 745/755 */
 147         0xfffff000, 0x00083000, "745/755",
 148         CPU_FTR_COMMON |
 149         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 150         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 151         COMMON_PPC,
 152         32, 32,
 153         __setup_cpu_750
 154     },
 155     {   /* 750CX (80100 and 8010x?) */
 156         0xfffffff0, 0x00080100, "750CX",
 157         CPU_FTR_COMMON |
 158         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 159         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 160         COMMON_PPC,
 161         32, 32,
 162         __setup_cpu_750cx
 163     },
 164     {   /* 750CX (82201 and 82202) */
 165         0xfffffff0, 0x00082200, "750CX",
 166         CPU_FTR_COMMON |
 167         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 168         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 169         COMMON_PPC,
 170         32, 32,
 171         __setup_cpu_750cx
 172     },
 173     {   /* 750CXe (82214) */
 174         0xfffffff0, 0x00082210, "750CXe",
 175         CPU_FTR_COMMON |
 176         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 177         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 178         COMMON_PPC,
 179         32, 32,
 180         __setup_cpu_750cx
 181     },
 182     {   /* 750FX rev 1.x */
 183         0xffffff00, 0x70000100, "750FX",
 184         CPU_FTR_COMMON |
 185         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 186         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 187         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 188         COMMON_PPC,
 189         32, 32,
 190         __setup_cpu_750
 191     },
 192     {   /* 750FX rev 2.0 must disable HID0[DPM] */
 193         0xffffffff, 0x70000200, "750FX",
 194         CPU_FTR_COMMON |
 195         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 196         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 197         CPU_FTR_NO_DPM,
 198         COMMON_PPC,
 199         32, 32,
 200         __setup_cpu_750
 201     },
 202     {   /* 750FX (All revs except 2.0) */
 203         0xffff0000, 0x70000000, "750FX",
 204         CPU_FTR_COMMON |
 205         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 206         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 207         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 208         COMMON_PPC,
 209         32, 32,
 210         __setup_cpu_750fx
 211     },
 212
 213     {   /* 740/750 (L2CR bit need fixup for 740) */
 214         0xffff0000, 0x00080000, "740/750",
 215         CPU_FTR_COMMON |
 216         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 217         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 218         COMMON_PPC,
 219         32, 32,
 220         __setup_cpu_750
 221     },
 222     {   /* 7400 rev 1.1 ? (no TAU) */
 223         0xffffffff, 0x000c1101, "7400 (1.1)",
 224         CPU_FTR_COMMON |
 225         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 226         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 227         CPU_FTR_CAN_NAP,
 228         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 229         32, 32,
 230         __setup_cpu_7400
 231     },
 232     {   /* 7400 */
 233         0xffff0000, 0x000c0000, "7400",
 234         CPU_FTR_COMMON |
 235         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 236         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 237         CPU_FTR_CAN_NAP,
 238         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 239         32, 32,
 240         __setup_cpu_7400
 241     },
 242     {   /* 7410 */
 243         0xffff0000, 0x800c0000, "7410",
 244         CPU_FTR_COMMON |
 245         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 246         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 247         CPU_FTR_CAN_NAP,
 248         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 249         32, 32,
 250         __setup_cpu_7410
 251     },
 252     {   /* 7450 2.0 - no doze/nap */
 253         0xffffffff, 0x80000200, "7450",
 254         CPU_FTR_COMMON |
 255         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 256         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 257         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
 258         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 259         32, 32,
 260         __setup_cpu_745x
 261     },
 262     {   /* 7450 2.1 */
 263         0xffffffff, 0x80000201, "7450",
 264         CPU_FTR_COMMON |
 265         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 266         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 267         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 268         CPU_FTR_L3_DISABLE_NAP,
 269         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 270         32, 32,
 271         __setup_cpu_745x
 272     },
 273     {   /* 7450 2.3 and newer */
 274         0xffff0000, 0x80000000, "7450",
 275         CPU_FTR_COMMON |
 276         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 277         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 278         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
 279         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 280         32, 32,
 281         __setup_cpu_745x
 282     },
 283     {   /* 7455 rev 1.x */
 284         0xffffff00, 0x80010100, "7455",
 285         CPU_FTR_COMMON |
 286         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 287         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 288         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
 289         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 290         32, 32,
 291         __setup_cpu_745x
 292     },
 293     {   /* 7455 rev 2.0 */
 294         0xffffffff, 0x80010200, "7455",
 295         CPU_FTR_COMMON |
 296         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 297         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 298         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 299         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
 300         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 301         32, 32,
 302         __setup_cpu_745x
 303     },
 304     {   /* 7455 others */
 305         0xffff0000, 0x80010000, "7455",
 306         CPU_FTR_COMMON |
 307         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 308         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 309         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 310         CPU_FTR_HAS_HIGH_BATS,
 311         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 312         32, 32,
 313         __setup_cpu_745x
 314     },
 315     {   /* 7457 */
 316         0xffff0000, 0x80020000, "7457",
 317         CPU_FTR_COMMON |
 318         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 319         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 320         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 321         CPU_FTR_HAS_HIGH_BATS,
 322         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 323         32, 32,
 324         __setup_cpu_745x
 325     },
 326     {   /* 7447A */
 327         0xffff0000, 0x80030000, "7447A",
 328         CPU_FTR_COMMON |
 329         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 330         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 331         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 332         CPU_FTR_HAS_HIGH_BATS,
 333         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 334         32, 32,
 335         __setup_cpu_745x
 336     },
 337     {   /* 82xx (8240, 8245, 8260 are all 603e cores) */
 338         0x7fff0000, 0x00810000, "82xx",
 339         CPU_FTR_COMMON |
 340         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
 341         COMMON_PPC,
 342         32, 32,
 343         __setup_cpu_603
 344     },
 345     {   /* default match, we assume split I/D cache & TB (non-601)... */
 346         0x00000000, 0x00000000, "(generic PPC)",
 347         CPU_FTR_COMMON |
 348         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 349         COMMON_PPC,
 350         32, 32,
 351         __setup_cpu_generic
 352     },
 353 #endif /* CLASSIC_PPC */
 354 #ifdef CONFIG_PPC64BRIDGE
 355     {   /* Power3 */
 356         0xffff0000, 0x00400000, "Power3 (630)",
 357         CPU_FTR_COMMON |
 358         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 359         COMMON_PPC | PPC_FEATURE_64,
 360         128, 128,
 361         __setup_cpu_power3
 362     },
 363     {   /* Power3+ */
 364         0xffff0000, 0x00410000, "Power3 (630+)",
 365         CPU_FTR_COMMON |
 366         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 367         COMMON_PPC | PPC_FEATURE_64,
 368         128, 128,
 369         __setup_cpu_power3
 370     },
 371         {       /* I-star */
 372                 0xffff0000, 0x00360000, "I-star",
 373                 CPU_FTR_COMMON |
 374                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 375                 COMMON_PPC | PPC_FEATURE_64,
 376                 128, 128,
 377                 __setup_cpu_power3
 378         },
 379         {       /* S-star */
 380                 0xffff0000, 0x00370000, "S-star",
 381                 CPU_FTR_COMMON |
 382                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 383                 COMMON_PPC | PPC_FEATURE_64,
 384                 128, 128,
 385                 __setup_cpu_power3
 386         },
 387 #endif /* CONFIG_PPC64BRIDGE */
 388 #ifdef CONFIG_POWER4
 389     {   /* Power4 */
 390         0xffff0000, 0x00350000, "Power4",
 391         CPU_FTR_COMMON |
 392         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 393         COMMON_PPC | PPC_FEATURE_64,
 394         128, 128,
 395         __setup_cpu_power4
 396     },
 397     {   /* PPC970 */
 398         0xffff0000, 0x00390000, "PPC970",
 399         CPU_FTR_COMMON |
 400         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 401         CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
 402         COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 403         128, 128,
 404         __setup_cpu_ppc970
 405     },
 406 #endif /* CONFIG_POWER4 */
 407 #ifdef CONFIG_8xx
 408     {   /* 8xx */
 409         0xffff0000, 0x00500000, "8xx",
 410                 /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
 411         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 412         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 413         16, 16,
 414         __setup_cpu_8xx /* Empty */
 415     },
 416 #endif /* CONFIG_8xx */
 417 #ifdef CONFIG_40x
 418     {   /* 403GC */
 419         0xffffff00, 0x00200200, "403GC",
 420         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 421         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 422         16, 16,
 423         0, /*__setup_cpu_403 */
 424     },
 425     {   /* 403GCX */
 426         0xffffff00, 0x00201400, "403GCX",
 427         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 428         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 429         16, 16,
 430         0, /*__setup_cpu_403 */
 431     },
 432     {   /* 403G ?? */
 433         0xffff0000, 0x00200000, "403G ??",
 434         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 435         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 436         16, 16,
 437         0, /*__setup_cpu_403 */
 438     },
 439     {   /* 405GP */
 440         0xffff0000, 0x40110000, "405GP",
 441         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 442         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 443         32, 32,
 444         0, /*__setup_cpu_405 */
 445     },
 446     {   /* STB 03xxx */
 447         0xffff0000, 0x40130000, "STB03xxx",
 448         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 449         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 450         32, 32,
 451         0, /*__setup_cpu_405 */
 452     },
 453     {   /* STB 04xxx */
 454         0xffff0000, 0x41810000, "STB04xxx",
 455         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 456         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 457         32, 32,
 458         0, /*__setup_cpu_405 */
 459     },
 460     {   /* NP405L */
 461         0xffff0000, 0x41610000, "NP405L",
 462         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 463         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 464         32, 32,
 465         0, /*__setup_cpu_405 */
 466     },
 467     {   /* NP4GS3 */
 468         0xffff0000, 0x40B10000, "NP4GS3",
 469         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 470         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 471         32, 32,
 472         0, /*__setup_cpu_405 */
 473     },
 474     {   /* NP405H */
 475         0xffff0000, 0x41410000, "NP405H",
 476         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 477         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 478         32, 32,
 479         0, /*__setup_cpu_405 */
 480      },
 481      {  /* 405GPr */
 482         0xffff0000, 0x50910000, "405GPr",
 483         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 484         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 485         32, 32,
 486         0, /*__setup_cpu_405 */
 487     },
 488     {   /* STBx25xx */
 489         0xffff0000, 0x51510000, "STBx25xx",
 490         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 491         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 492         32, 32,
 493         0, /*__setup_cpu_405 */
 494      },
 495      {  /* 405LP */
 496         0xffff0000, 0x41F10000, "405LP",
 497         CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
 498         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 499         32, 32,
 500         0, /*__setup_cpu_405 */
 501      },
 502      {  /* Xilinx Virtex-II Pro  */
 503         0xffff0000, 0x20010000, "Virtex-II Pro",
 504         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 505         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 506         32, 32,
 507         0, /*__setup_cpu_405 */
 508      },
 509
 510 #endif /* CONFIG_40x */
 511 #ifdef CONFIG_44x
 512     { /* 440GP Rev. B */
 513         0xf0000fff, 0x40000440, "440GP Rev. B",
 514         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 515         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 516         32, 32,
 517         0, /*__setup_cpu_440 */
 518     },
 519     { /* 440GP Rev. C */
 520         0xf0000fff, 0x40000481, "440GP Rev. C",
 521         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 522         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 523         32, 32,
 524         0, /*__setup_cpu_440 */
 525     },
 526     { /* 440GX Rev. A */
 527         0xf0000fff, 0x50000850, "440GX Rev. A",
 528         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 529         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 530         32, 32,
 531         0, /*__setup_cpu_440 */
 532     },
 533     { /* 440GX Rev. B */
 534         0xf0000fff, 0x50000851, "440GX Rev. B",
 535         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 536         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 537         32, 32,
 538         0, /*__setup_cpu_440 */
 539     },
 540     { /* 440GX Rev. B1 (2.1) */
 541         0xf0000fff, 0x50000852, "440GX Rev. B1 (2.1)",
 542         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 543         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 544         32, 32,
 545         0, /*__setup_cpu_440 */
 546     },
 547 #endif /* CONFIG_44x */
 548 #if !CLASSIC_PPC
 549     {   /* default match */
 550         0x00000000, 0x00000000, "(generic PPC)",
 551         CPU_FTR_COMMON,
 552         PPC_FEATURE_32,
 553         32, 32,
 554         0,
 555     }
 556 #endif /* !CLASSIC_PPC */
 557 };