arch/ppc/kernel/cputable.c

   1 /*
   2  *  arch/ppc/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/threads.h>
  16 #include <linux/init.h>
  17 #include <asm/cputable.h>
  18
  19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
  20
  21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  35
  36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  37                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
  38                      !defined(CONFIG_BOOKE))
  39
  40 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  41  * ones as well...
  42  */
  43 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  44                          PPC_FEATURE_HAS_MMU)
  45
  46 /* We only set the altivec features if the kernel was compiled with altivec
  47  * support
  48  */
  49 #ifdef CONFIG_ALTIVEC
  50 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
  51 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
  52 #else
  53 #define CPU_FTR_ALTIVEC_COMP            0
  54 #define PPC_FEATURE_ALTIVEC_COMP        0
  55 #endif
  56
  57 /* We need to mark all pages as being coherent if we're SMP or we
  58  * have a 754x and an MPC107 host bridge.
  59  */
  60 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
  61 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  62 #else
  63 #define CPU_FTR_COMMON                  0
  64 #endif
  65
  66 struct cpu_spec cpu_specs[] = {
  67 #if CLASSIC_PPC
  68     {   /* 601 */
  69         0xffff0000, 0x00010000, "601",
  70         CPU_FTR_COMMON |
  71         CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
  72         COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
  73         32, 32,
  74         __setup_cpu_601
  75     },
  76     {   /* 603 */
  77         0xffff0000, 0x00030000, "603",
  78         CPU_FTR_COMMON |
  79         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  80         CPU_FTR_CAN_NAP,
  81         COMMON_PPC,
  82         32, 32,
  83         __setup_cpu_603
  84     },
  85     {   /* 603e */
  86         0xffff0000, 0x00060000, "603e",
  87         CPU_FTR_COMMON |
  88         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  89         CPU_FTR_CAN_NAP,
  90         COMMON_PPC,
  91         32, 32,
  92         __setup_cpu_603
  93     },
  94     {   /* 603ev */
  95         0xffff0000, 0x00070000, "603ev",
  96         CPU_FTR_COMMON |
  97         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  98         CPU_FTR_CAN_NAP,
  99         COMMON_PPC,
 100         32, 32,
 101         __setup_cpu_603
 102     },
 103     {   /* 604 */
 104         0xffff0000, 0x00040000, "604",
 105         CPU_FTR_COMMON |
 106         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 107         CPU_FTR_HPTE_TABLE,
 108         COMMON_PPC,
 109         32, 32,
 110         __setup_cpu_604
 111     },
 112     {   /* 604e */
 113         0xfffff000, 0x00090000, "604e",
 114         CPU_FTR_COMMON |
 115         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 116         CPU_FTR_HPTE_TABLE,
 117         COMMON_PPC,
 118         32, 32,
 119         __setup_cpu_604
 120     },
 121     {   /* 604r */
 122         0xffff0000, 0x00090000, "604r",
 123         CPU_FTR_COMMON |
 124         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 125         CPU_FTR_HPTE_TABLE,
 126         COMMON_PPC,
 127         32, 32,
 128         __setup_cpu_604
 129     },
 130     {   /* 604ev */
 131         0xffff0000, 0x000a0000, "604ev",
 132         CPU_FTR_COMMON |
 133         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 134         CPU_FTR_HPTE_TABLE,
 135         COMMON_PPC,
 136         32, 32,
 137         __setup_cpu_604
 138     },
 139     {   /* 740/750 (0x4202, don't support TAU ?) */
 140         0xffffffff, 0x00084202, "740/750",
 141         CPU_FTR_COMMON |
 142         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 143         CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 144         COMMON_PPC,
 145         32, 32,
 146         __setup_cpu_750
 147     },
 148     {   /* 745/755 */
 149         0xfffff000, 0x00083000, "745/755",
 150         CPU_FTR_COMMON |
 151         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 152         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 153         COMMON_PPC,
 154         32, 32,
 155         __setup_cpu_750
 156     },
 157     {   /* 750CX (80100 and 8010x?) */
 158         0xfffffff0, 0x00080100, "750CX",
 159         CPU_FTR_COMMON |
 160         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 161         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 162         COMMON_PPC,
 163         32, 32,
 164         __setup_cpu_750cx
 165     },
 166     {   /* 750CX (82201 and 82202) */
 167         0xfffffff0, 0x00082200, "750CX",
 168         CPU_FTR_COMMON |
 169         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 170         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 171         COMMON_PPC,
 172         32, 32,
 173         __setup_cpu_750cx
 174     },
 175     {   /* 750CXe (82214) */
 176         0xfffffff0, 0x00082210, "750CXe",
 177         CPU_FTR_COMMON |
 178         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 179         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 180         COMMON_PPC,
 181         32, 32,
 182         __setup_cpu_750cx
 183     },
 184     {   /* 750FX rev 1.x */
 185         0xffffff00, 0x70000100, "750FX",
 186         CPU_FTR_COMMON |
 187         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 188         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 189         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 190         COMMON_PPC,
 191         32, 32,
 192         __setup_cpu_750
 193     },
 194     {   /* 750FX rev 2.0 must disable HID0[DPM] */
 195         0xffffffff, 0x70000200, "750FX",
 196         CPU_FTR_COMMON |
 197         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 198         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 199         CPU_FTR_NO_DPM,
 200         COMMON_PPC,
 201         32, 32,
 202         __setup_cpu_750
 203     },
 204     {   /* 750FX (All revs except 2.0) */
 205         0xffff0000, 0x70000000, "750FX",
 206         CPU_FTR_COMMON |
 207         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 208         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 209         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 210         COMMON_PPC,
 211         32, 32,
 212         __setup_cpu_750fx
 213     },
 214     {   /* 750GX */
 215         0xffff0000, 0x70020000, "750GX",
 216         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 217         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 218         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 219         COMMON_PPC,
 220         32, 32,
 221         __setup_cpu_750fx
 222     },
 223     {   /* 740/750 (L2CR bit need fixup for 740) */
 224         0xffff0000, 0x00080000, "740/750",
 225         CPU_FTR_COMMON |
 226         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 227         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 228         COMMON_PPC,
 229         32, 32,
 230         __setup_cpu_750
 231     },
 232     {   /* 7400 rev 1.1 ? (no TAU) */
 233         0xffffffff, 0x000c1101, "7400 (1.1)",
 234         CPU_FTR_COMMON |
 235         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 236         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 237         CPU_FTR_CAN_NAP,
 238         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 239         32, 32,
 240         __setup_cpu_7400
 241     },
 242     {   /* 7400 */
 243         0xffff0000, 0x000c0000, "7400",
 244         CPU_FTR_COMMON |
 245         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 246         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 247         CPU_FTR_CAN_NAP,
 248         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 249         32, 32,
 250         __setup_cpu_7400
 251     },
 252     {   /* 7410 */
 253         0xffff0000, 0x800c0000, "7410",
 254         CPU_FTR_COMMON |
 255         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 256         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 257         CPU_FTR_CAN_NAP,
 258         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 259         32, 32,
 260         __setup_cpu_7410
 261     },
 262     {   /* 7450 2.0 - no doze/nap */
 263         0xffffffff, 0x80000200, "7450",
 264         CPU_FTR_COMMON |
 265         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 266         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 267         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
 268         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 269         32, 32,
 270         __setup_cpu_745x
 271     },
 272     {   /* 7450 2.1 */
 273         0xffffffff, 0x80000201, "7450",
 274         CPU_FTR_COMMON |
 275         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 276         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 277         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 278         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
 279         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 280         32, 32,
 281         __setup_cpu_745x
 282     },
 283     {   /* 7450 2.3 and newer */
 284         0xffff0000, 0x80000000, "7450",
 285         CPU_FTR_COMMON |
 286         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 287         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 288         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 289         CPU_FTR_NEED_COHERENT,
 290         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 291         32, 32,
 292         __setup_cpu_745x
 293     },
 294     {   /* 7455 rev 1.x */
 295         0xffffff00, 0x80010100, "7455",
 296         CPU_FTR_COMMON |
 297         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 298         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 299         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
 300         CPU_FTR_NEED_COHERENT,
 301         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 302         32, 32,
 303         __setup_cpu_745x
 304     },
 305     {   /* 7455 rev 2.0 */
 306         0xffffffff, 0x80010200, "7455",
 307         CPU_FTR_COMMON |
 308         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 309         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 310         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 311         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 312         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 313         32, 32,
 314         __setup_cpu_745x
 315     },
 316     {   /* 7455 others */
 317         0xffff0000, 0x80010000, "7455",
 318         CPU_FTR_COMMON |
 319         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 320         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 321         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 322         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 323         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 324         32, 32,
 325         __setup_cpu_745x
 326     },
 327     {   /* 7447/7457 Rev 1.0 */
 328         0xffffffff, 0x80020100, "7447/7457",
 329         CPU_FTR_COMMON |
 330         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 331         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 332         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 333         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 334         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 335         32, 32,
 336         __setup_cpu_745x
 337     },
 338     {   /* 7447/7457 Rev 1.1 */
 339         0xffffffff, 0x80020101, "7447/7457",
 340         CPU_FTR_COMMON |
 341         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 342         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 343         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 344         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 345         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 346         32, 32,
 347         __setup_cpu_745x
 348     },
 349     {   /* 7447/7457 Rev 1.2 and later */
 350         0xffff0000, 0x80020000, "7447/7457",
 351         CPU_FTR_COMMON |
 352         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 353         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 354         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 355         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 356         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 357         32, 32,
 358         __setup_cpu_745x
 359     },
 360     {   /* 7447A */
 361         0xffff0000, 0x80030000, "7447A",
 362         CPU_FTR_COMMON |
 363         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 364         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 365         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 366         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 367         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 368         32, 32,
 369         __setup_cpu_745x
 370     },
 371     {   /* 82xx (8240, 8245, 8260 are all 603e cores) */
 372         0x7fff0000, 0x00810000, "82xx",
 373         CPU_FTR_COMMON |
 374         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
 375         COMMON_PPC,
 376         32, 32,
 377         __setup_cpu_603
 378     },
 379     {   /* All G2_LE (603e core, plus some) have the same pvr */
 380         0x7fff0000, 0x00820000, "G2_LE",
 381         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 382         CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 383         COMMON_PPC,
 384         32, 32,
 385         __setup_cpu_603
 386     },
 387     {   /* default match, we assume split I/D cache & TB (non-601)... */
 388         0x00000000, 0x00000000, "(generic PPC)",
 389         CPU_FTR_COMMON |
 390         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 391         COMMON_PPC,
 392         32, 32,
 393         __setup_cpu_generic
 394     },
 395 #endif /* CLASSIC_PPC */
 396 #ifdef CONFIG_PPC64BRIDGE
 397     {   /* Power3 */
 398         0xffff0000, 0x00400000, "Power3 (630)",
 399         CPU_FTR_COMMON |
 400         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 401         COMMON_PPC | PPC_FEATURE_64,
 402         128, 128,
 403         __setup_cpu_power3
 404     },
 405     {   /* Power3+ */
 406         0xffff0000, 0x00410000, "Power3 (630+)",
 407         CPU_FTR_COMMON |
 408         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 409         COMMON_PPC | PPC_FEATURE_64,
 410         128, 128,
 411         __setup_cpu_power3
 412     },
 413         {       /* I-star */
 414                 0xffff0000, 0x00360000, "I-star",
 415                 CPU_FTR_COMMON |
 416                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 417                 COMMON_PPC | PPC_FEATURE_64,
 418                 128, 128,
 419                 __setup_cpu_power3
 420         },
 421         {       /* S-star */
 422                 0xffff0000, 0x00370000, "S-star",
 423                 CPU_FTR_COMMON |
 424                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 425                 COMMON_PPC | PPC_FEATURE_64,
 426                 128, 128,
 427                 __setup_cpu_power3
 428         },
 429 #endif /* CONFIG_PPC64BRIDGE */
 430 #ifdef CONFIG_POWER4
 431     {   /* Power4 */
 432         0xffff0000, 0x00350000, "Power4",
 433         CPU_FTR_COMMON |
 434         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 435         COMMON_PPC | PPC_FEATURE_64,
 436         128, 128,
 437         __setup_cpu_power4
 438     },
 439     {   /* PPC970 */
 440         0xffff0000, 0x00390000, "PPC970",
 441         CPU_FTR_COMMON |
 442         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 443         CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
 444         COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 445         128, 128,
 446         __setup_cpu_ppc970
 447     },
 448 #endif /* CONFIG_POWER4 */
 449 #ifdef CONFIG_8xx
 450     {   /* 8xx */
 451         0xffff0000, 0x00500000, "8xx",
 452                 /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
 453         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 454         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 455         16, 16,
 456         __setup_cpu_8xx /* Empty */
 457     },
 458 #endif /* CONFIG_8xx */
 459 #ifdef CONFIG_40x
 460     {   /* 403GC */
 461         0xffffff00, 0x00200200, "403GC",
 462         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 463         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 464         16, 16,
 465         0, /*__setup_cpu_403 */
 466     },
 467     {   /* 403GCX */
 468         0xffffff00, 0x00201400, "403GCX",
 469         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 470         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 471         16, 16,
 472         0, /*__setup_cpu_403 */
 473     },
 474     {   /* 403G ?? */
 475         0xffff0000, 0x00200000, "403G ??",
 476         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 477         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 478         16, 16,
 479         0, /*__setup_cpu_403 */
 480     },
 481     {   /* 405GP */
 482         0xffff0000, 0x40110000, "405GP",
 483         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 484         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 485         32, 32,
 486         0, /*__setup_cpu_405 */
 487     },
 488     {   /* STB 03xxx */
 489         0xffff0000, 0x40130000, "STB03xxx",
 490         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 491         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 492         32, 32,
 493         0, /*__setup_cpu_405 */
 494     },
 495     {   /* STB 04xxx */
 496         0xffff0000, 0x41810000, "STB04xxx",
 497         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 498         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 499         32, 32,
 500         0, /*__setup_cpu_405 */
 501     },
 502     {   /* NP405L */
 503         0xffff0000, 0x41610000, "NP405L",
 504         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 505         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 506         32, 32,
 507         0, /*__setup_cpu_405 */
 508     },
 509     {   /* NP4GS3 */
 510         0xffff0000, 0x40B10000, "NP4GS3",
 511         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 512         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 513         32, 32,
 514         0, /*__setup_cpu_405 */
 515     },
 516     {   /* NP405H */
 517         0xffff0000, 0x41410000, "NP405H",
 518         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 519         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 520         32, 32,
 521         0, /*__setup_cpu_405 */
 522      },
 523      {  /* 405GPr */
 524         0xffff0000, 0x50910000, "405GPr",
 525         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 526         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 527         32, 32,
 528         0, /*__setup_cpu_405 */
 529     },
 530     {   /* STBx25xx */
 531         0xffff0000, 0x51510000, "STBx25xx",
 532         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 533         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 534         32, 32,
 535         0, /*__setup_cpu_405 */
 536      },
 537      {  /* 405LP */
 538         0xffff0000, 0x41F10000, "405LP",
 539         CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
 540         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 541         32, 32,
 542         0, /*__setup_cpu_405 */
 543      },
 544      {  /* Xilinx Virtex-II Pro  */
 545         0xffff0000, 0x20010000, "Virtex-II Pro",
 546         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 547         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 548         32, 32,
 549         0, /*__setup_cpu_405 */
 550      },
 551
 552 #endif /* CONFIG_40x */
 553 #ifdef CONFIG_44x
 554     { /* 440GP Rev. B */
 555         0xf0000fff, 0x40000440, "440GP Rev. B",
 556         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 557         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 558         32, 32,
 559         0, /*__setup_cpu_440 */
 560     },
 561     { /* 440GP Rev. C */
 562         0xf0000fff, 0x40000481, "440GP Rev. C",
 563         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 564         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 565         32, 32,
 566         0, /*__setup_cpu_440 */
 567     },
 568     { /* 440GX Rev. A */
 569         0xf0000fff, 0x50000850, "440GX Rev. A",
 570         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 571         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 572         32, 32,
 573         0, /*__setup_cpu_440 */
 574     },
 575     { /* 440GX Rev. B */
 576         0xf0000fff, 0x50000851, "440GX Rev. B",
 577         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 578         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 579         32, 32,
 580         0, /*__setup_cpu_440 */
 581     },
 582     { /* 440GX Rev. C */
 583         0xf0000fff, 0x50000892, "440GX Rev. C",
 584         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 585         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 586         32, 32,
 587         0, /*__setup_cpu_440 */
 588     },
 589 #endif /* CONFIG_44x */
 590 #ifdef CONFIG_E500
 591     { /* e500 */
 592         0xffff0000, 0x80200000, "e500",
 593         /* xxx - galak: add CPU_FTR_CAN_DOZE */
 594         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 595         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 596         32, 32,
 597         0, /*__setup_cpu_e500 */
 598     },
 599 #endif
 600 #if !CLASSIC_PPC
 601     {   /* default match */
 602         0x00000000, 0x00000000, "(generic PPC)",
 603         CPU_FTR_COMMON,
 604         PPC_FEATURE_32,
 605         32, 32,
 606         0,
 607     }
 608 #endif /* !CLASSIC_PPC */
 609 };