arch/ppc/kernel/head_booke.h

   1 #ifndef __HEAD_BOOKE_H__
   2 #define __HEAD_BOOKE_H__
   3
   4 /*
   5  * Macros used for common Book-e exception handling
   6  */
   7
   8 #define SET_IVOR(vector_number, vector_label)           \
   9                 li      r26,vector_label@l;             \
  10                 mtspr   SPRN_IVOR##vector_number,r26;   \
  11                 sync
  12
  13 #define NORMAL_EXCEPTION_PROLOG                                              \
  14         mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
  15         mtspr   SPRN_SPRG1,r11;                                              \
  16         mtspr   SPRN_SPRG4W,r1;                                              \
  17         mfcr    r10;                    /* save CR in r10 for now          */\
  18         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
  19         andi.   r11,r11,MSR_PR;                                              \
  20         beq     1f;                                                          \
  21         mfspr   r1,SPRG3;               /* if from user, start at top of   */\
  22         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
  23         addi    r1,r1,THREAD_SIZE;                                           \
  24 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
  25         tophys(r11,r1);                                                      \
  26         stw     r10,_CCR(r11);          /* save various registers          */\
  27         stw     r12,GPR12(r11);                                              \
  28         stw     r9,GPR9(r11);                                                \
  29         mfspr   r10,SPRG0;                                                   \
  30         stw     r10,GPR10(r11);                                              \
  31         mfspr   r12,SPRG1;                                                   \
  32         stw     r12,GPR11(r11);                                              \
  33         mflr    r10;                                                         \
  34         stw     r10,_LINK(r11);                                              \
  35         mfspr   r10,SPRG4R;                                                  \
  36         mfspr   r12,SRR0;                                                    \
  37         stw     r10,GPR1(r11);                                               \
  38         mfspr   r9,SRR1;                                                     \
  39         stw     r10,0(r11);                                                  \
  40         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
  41         stw     r0,GPR0(r11);                                                \
  42         SAVE_4GPRS(3, r11);                                                  \
  43         SAVE_2GPRS(7, r11)
  44
  45 /*
  46  * Exception prolog for critical exceptions.  This is a little different
  47  * from the normal exception prolog above since a critical exception
  48  * can potentially occur at any point during normal exception processing.
  49  * Thus we cannot use the same SPRG registers as the normal prolog above.
  50  * Instead we use a couple of words of memory at low physical addresses.
  51  * This is OK since we don't support SMP on these processors. For Book E
  52  * processors, we also have a reserved register (SPRG2) that is only used
  53  * in critical exceptions so we can free up a GPR to use as the base for
  54  * indirect access to the critical exception save area.  This is necessary
  55  * since the MMU is always on and the save area is offset from KERNELBASE.
  56  */
  57 #define CRITICAL_EXCEPTION_PROLOG                                            \
  58         mtspr   SPRG2,r8;               /* SPRG2 only used in criticals */   \
  59         lis     r8,crit_save@ha;                                             \
  60         stw     r10,crit_r10@l(r8);                                          \
  61         stw     r11,crit_r11@l(r8);                                          \
  62         mfspr   r10,SPRG0;                                                   \
  63         stw     r10,crit_sprg0@l(r8);                                        \
  64         mfspr   r10,SPRG1;                                                   \
  65         stw     r10,crit_sprg1@l(r8);                                        \
  66         mfspr   r10,SPRG4R;                                                  \
  67         stw     r10,crit_sprg4@l(r8);                                        \
  68         mfspr   r10,SPRG5R;                                                  \
  69         stw     r10,crit_sprg5@l(r8);                                        \
  70         mfspr   r10,SPRG7R;                                                  \
  71         stw     r10,crit_sprg7@l(r8);                                        \
  72         mfspr   r10,SPRN_PID;                                                \
  73         stw     r10,crit_pid@l(r8);                                          \
  74         mfspr   r10,SRR0;                                                    \
  75         stw     r10,crit_srr0@l(r8);                                         \
  76         mfspr   r10,SRR1;                                                    \
  77         stw     r10,crit_srr1@l(r8);                                         \
  78         mfspr   r8,SPRG2;               /* SPRG2 only used in criticals */   \
  79         mfcr    r10;                    /* save CR in r10 for now          */\
  80         mfspr   r11,SPRN_CSRR1;         /* check whether user or kernel    */\
  81         andi.   r11,r11,MSR_PR;                                              \
  82         lis     r11,critical_stack_top@h;                                    \
  83         ori     r11,r11,critical_stack_top@l;                                \
  84         beq     1f;                                                          \
  85         /* COMING FROM USER MODE */                                          \
  86         mfspr   r11,SPRG3;              /* if from user, start at top of   */\
  87         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
  88         addi    r11,r11,THREAD_SIZE;                                         \
  89 1:      subi    r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame     */\
  90         stw     r10,_CCR(r11);          /* save various registers          */\
  91         stw     r12,GPR12(r11);                                              \
  92         stw     r9,GPR9(r11);                                                \
  93         mflr    r10;                                                         \
  94         stw     r10,_LINK(r11);                                              \
  95         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
  96         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
  97         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
  98         stw     r9,_ESR(r11);           /* exception was taken             */\
  99         mfspr   r12,CSRR0;                                                   \
 100         stw     r1,GPR1(r11);                                                \
 101         mfspr   r9,CSRR1;                                                    \
 102         stw     r1,0(r11);                                                   \
 103         tovirt(r1,r11);                                                      \
 104         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 105         stw     r0,GPR0(r11);                                                \
 106         SAVE_4GPRS(3, r11);                                                  \
 107         SAVE_2GPRS(7, r11)
 108
 109 /*
 110  * Exception prolog for machine check exceptions.  This is similar to
 111  * the critical exception prolog, except that machine check exceptions
 112  * have their own save area.  For Book E processors, we also have a
 113  * reserved register (SPRG6) that is only used in machine check exceptions
 114  * so we can free up a GPR to use as the base for indirect access to the
 115  * machine check exception save area.  This is necessary since the MMU
 116  * is always on and the save area is offset from KERNELBASE.
 117  */
 118 #define MCHECK_EXCEPTION_PROLOG                                      \
 119         mtspr   SPRG6W,r8;              /* SPRG6 used in machine checks */   \
 120         lis     r8,mcheck_save@ha;                                           \
 121         stw     r10,mcheck_r10@l(r8);                                        \
 122         stw     r11,mcheck_r11@l(r8);                                        \
 123         mfspr   r10,SPRG0;                                                   \
 124         stw     r10,mcheck_sprg0@l(r8);                                      \
 125         mfspr   r10,SPRG1;                                                   \
 126         stw     r10,mcheck_sprg1@l(r8);                                      \
 127         mfspr   r10,SPRG4R;                                                  \
 128         stw     r10,mcheck_sprg4@l(r8);                                      \
 129         mfspr   r10,SPRG5R;                                                  \
 130         stw     r10,mcheck_sprg5@l(r8);                                      \
 131         mfspr   r10,SPRG7R;                                                  \
 132         stw     r10,mcheck_sprg7@l(r8);                                      \
 133         mfspr   r10,SPRN_PID;                                                \
 134         stw     r10,mcheck_pid@l(r8);                                        \
 135         mfspr   r10,SRR0;                                                    \
 136         stw     r10,mcheck_srr0@l(r8);                                       \
 137         mfspr   r10,SRR1;                                                    \
 138         stw     r10,mcheck_srr1@l(r8);                                       \
 139         mfspr   r10,CSRR0;                                                   \
 140         stw     r10,mcheck_csrr0@l(r8);                                      \
 141         mfspr   r10,CSRR1;                                                   \
 142         stw     r10,mcheck_csrr1@l(r8);                                      \
 143         mfspr   r8,SPRG6R;              /* SPRG6 used in machine checks */   \
 144         mfcr    r10;                    /* save CR in r10 for now          */\
 145         mfspr   r11,SPRN_MCSRR1;        /* check whether user or kernel    */\
 146         andi.   r11,r11,MSR_PR;                                              \
 147         lis     r11,mcheck_stack_top@h;                                      \
 148         ori     r11,r11,mcheck_stack_top@l;                                  \
 149         beq     1f;                                                          \
 150         /* COMING FROM USER MODE */                                          \
 151         mfspr   r11,SPRG3;              /* if from user, start at top of   */\
 152         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 153         addi    r11,r11,THREAD_SIZE;                                         \
 154 1:      subi    r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame     */\
 155         stw     r10,_CCR(r11);          /* save various registers          */\
 156         stw     r12,GPR12(r11);                                              \
 157         stw     r9,GPR9(r11);                                                \
 158         mflr    r10;                                                         \
 159         stw     r10,_LINK(r11);                                              \
 160         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 161         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 162         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 163         stw     r9,_ESR(r11);           /* exception was taken             */\
 164         mfspr   r12,MCSRR0;                                                  \
 165         stw     r1,GPR1(r11);                                                \
 166         mfspr   r9,MCSRR1;                                                   \
 167         stw     r1,0(r11);                                                   \
 168         tovirt(r1,r11);                                                      \
 169         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 170         stw     r0,GPR0(r11);                                                \
 171         SAVE_4GPRS(3, r11);                                                  \
 172         SAVE_2GPRS(7, r11)
 173
 174 /*
 175  * Exception vectors.
 176  */
 177 #define START_EXCEPTION(label)                                               \
 178         .align 5;                                                            \
 179 label:
 180
 181 #define FINISH_EXCEPTION(func)                                  \
 182         bl      transfer_to_handler_full;                       \
 183         .long   func;                                           \
 184         .long   ret_from_except_full
 185
 186 #define EXCEPTION(n, label, hdlr, xfer)                         \
 187         START_EXCEPTION(label);                                 \
 188         NORMAL_EXCEPTION_PROLOG;                                \
 189         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 190         xfer(n, hdlr)
 191
 192 #define CRITICAL_EXCEPTION(n, label, hdlr)                      \
 193         START_EXCEPTION(label);                                 \
 194         CRITICAL_EXCEPTION_PROLOG;                              \
 195         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 196         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 197                           NOCOPY, transfer_to_handler_full, \
 198                           ret_from_except_full)
 199
 200 #define MCHECK_EXCEPTION(n, label, hdlr)                        \
 201         START_EXCEPTION(label);                                 \
 202         MCHECK_EXCEPTION_PROLOG;                                \
 203         mfspr   r5,SPRN_ESR;                                    \
 204         stw     r5,_ESR(r11);                                   \
 205         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 206         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 207                           NOCOPY, mcheck_transfer_to_handler,   \
 208                           ret_from_mcheck_exc)
 209
 210 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 211         li      r10,trap;                                       \
 212         stw     r10,TRAP(r11);                                  \
 213         lis     r10,msr@h;                                      \
 214         ori     r10,r10,msr@l;                                  \
 215         copyee(r10, r9);                                        \
 216         bl      tfer;                                           \
 217         .long   hdlr;                                           \
 218         .long   ret
 219
 220 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 221 #define NOCOPY(d, s)
 222
 223 #define EXC_XFER_STD(n, hdlr)           \
 224         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 225                           ret_from_except_full)
 226
 227 #define EXC_XFER_LITE(n, hdlr)          \
 228         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 229                           ret_from_except)
 230
 231 #define EXC_XFER_EE(n, hdlr)            \
 232         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 233                           ret_from_except_full)
 234
 235 #define EXC_XFER_EE_LITE(n, hdlr)       \
 236         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 237                           ret_from_except)
 238
 239
 240 /* Check for a single step debug exception while in an exception
 241  * handler before state has been saved.  This is to catch the case
 242  * where an instruction that we are trying to single step causes
 243  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 244  * the exception handler generates a single step debug exception.
 245  *
 246  * If we get a debug trap on the first instruction of an exception handler,
 247  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 248  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 249  * The exception handler was handling a non-critical interrupt, so it will
 250  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 251  * the MSR_DE bit set.
 252  */
 253 #define DEBUG_EXCEPTION                                                       \
 254         START_EXCEPTION(Debug);                                               \
 255         CRITICAL_EXCEPTION_PROLOG;                                            \
 256                                                                               \
 257         /*                                                                    \
 258          * If there is a single step or branch-taken exception in an          \
 259          * exception entry sequence, it was probably meant to apply to        \
 260          * the code where the exception occurred (since exception entry       \
 261          * doesn't turn off DE automatically).  We simulate the effect        \
 262          * of turning off DE on entry to an exception handler by turning      \
 263          * off DE in the CSRR1 value and clearing the debug status.           \
 264          */                                                                   \
 265         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 266         andis.  r10,r10,DBSR_IC@h;                                            \
 267         beq+    2f;                                                           \
 268                                                                               \
 269         lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
 270         ori     r10,r10,KERNELBASE@l;                                         \
 271         cmplw   r12,r10;                                                      \
 272         blt+    2f;                     /* addr below exception vectors */    \
 273                                                                               \
 274         lis     r10,Debug@h;                                                  \
 275         ori     r10,r10,Debug@l;                                              \
 276         cmplw   r12,r10;                                                      \
 277         bgt+    2f;                     /* addr above exception vectors */    \
 278                                                                               \
 279         /* here it looks like we got an inappropriate debug exception. */     \
 280 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
 281         lis     r10,DBSR_IC@h;          /* clear the IC event */              \
 282         mtspr   SPRN_DBSR,r10;                                                \
 283         /* restore state and get out */                                       \
 284         lwz     r10,_CCR(r11);                                                \
 285         lwz     r0,GPR0(r11);                                                 \
 286         lwz     r1,GPR1(r11);                                                 \
 287         mtcrf   0x80,r10;                                                     \
 288         mtspr   CSRR0,r12;                                                    \
 289         mtspr   CSRR1,r9;                                                     \
 290         lwz     r9,GPR9(r11);                                                 \
 291         lwz     r12,GPR12(r11);                                               \
 292         mtspr   SPRG2,r8;               /* SPRG2 only used in criticals */    \
 293         lis     r8,crit_save@ha;                                              \
 294         lwz     r10,crit_r10@l(r8);                                           \
 295         lwz     r11,crit_r11@l(r8);                                           \
 296         mfspr   r8,SPRG2;                                                     \
 297                                                                               \
 298         rfci;                                                                 \
 299         b       .;                                                            \
 300                                                                               \
 301         /* continue normal handling for a critical exception... */            \
 302 2:      mfspr   r4,SPRN_DBSR;                                                 \
 303         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 304         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 305
 306 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
 307         START_EXCEPTION(InstructionStorage)                                   \
 308         NORMAL_EXCEPTION_PROLOG;                                              \
 309         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 310         stw     r5,_ESR(r11);                                                 \
 311         mr      r4,r12;                 /* Pass SRR0 as arg2 */               \
 312         li      r5,0;                   /* Pass zero as arg3 */               \
 313         EXC_XFER_EE_LITE(0x0400, handle_page_fault)
 314
 315 #define ALIGNMENT_EXCEPTION                                                   \
 316         START_EXCEPTION(Alignment)                                            \
 317         NORMAL_EXCEPTION_PROLOG;                                              \
 318         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */       \
 319         stw     r4,_DEAR(r11);                                                \
 320         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 321         EXC_XFER_EE(0x0600, AlignmentException)
 322
 323 #define PROGRAM_EXCEPTION                                                     \
 324         START_EXCEPTION(Program)                                              \
 325         NORMAL_EXCEPTION_PROLOG;                                              \
 326         mfspr   r4,SPRN_ESR;            /* Grab the ESR and save it */        \
 327         stw     r4,_ESR(r11);                                                 \
 328         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 329         EXC_XFER_STD(0x0700, ProgramCheckException)
 330
 331 #define DECREMENTER_EXCEPTION                                                 \
 332         START_EXCEPTION(Decrementer)                                          \
 333         NORMAL_EXCEPTION_PROLOG;                                              \
 334         lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
 335         mtspr   SPRN_TSR,r0;            /* Clear the DEC interrupt */         \
 336         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 337         EXC_XFER_LITE(0x0900, timer_interrupt)
 338
 339 #endif /* __HEAD_BOOKE_H__ */