2 * arch/ppc/platforms/4xx/ebony.c
4 * Ebony board specific routines
6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc.
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/types.h>
27 #include <linux/major.h>
28 #include <linux/blkdev.h>
29 #include <linux/console.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/initrd.h>
33 #include <linux/irq.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/serial_core.h>
40 #include <asm/system.h>
41 #include <asm/pgtable.h>
45 #include <asm/machdep.h>
47 #include <asm/pci-bridge.h>
50 #include <asm/bootinfo.h>
51 #include <asm/ppc4xx_pic.h>
53 #include <syslib/gen550.h>
55 static struct ibm44x_clocks clocks __initdata;
58 * Ebony external IRQ triggering/polarity settings
60 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
66 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
77 ebony_calibrate_decr(void)
82 * Determine system clock speed
84 * If we are on Rev. B silicon, then use
85 * default external system clock. If we are
86 * on Rev. C silicon then errata forces us to
87 * use the internal clock.
89 switch (PVR_REV(mfspr(PVR))) {
90 case PVR_REV(PVR_440GP_RB):
91 freq = EBONY_440GP_RB_SYSCLK;
93 case PVR_REV(PVR_440GP_RC1):
95 freq = EBONY_440GP_RC_SYSCLK;
99 ibm44x_calibrate_decr(freq);
103 ebony_show_cpuinfo(struct seq_file *m)
105 seq_printf(m, "vendor\t\t: IBM\n");
106 seq_printf(m, "machine\t\t: Ebony\n");
112 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
114 static char pci_irq_table[][4] =
116 * PCI IDSEL/INTPIN->INTLINE
120 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
121 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
122 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
123 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
126 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
127 return PCI_IRQ_TABLE_LOOKUP;
130 #define PCIX_WRITEL(value, offset) \
131 (writel(value, pcix_reg_base + offset))
134 * FIXME: This is only here to "make it work". This will move
135 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
136 * configuration library. -Matt
139 ebony_setup_pcix(void)
143 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
145 /* Disable all windows */
146 PCIX_WRITEL(0, PCIX0_POM0SA);
147 PCIX_WRITEL(0, PCIX0_POM1SA);
148 PCIX_WRITEL(0, PCIX0_POM2SA);
149 PCIX_WRITEL(0, PCIX0_PIM0SA);
150 PCIX_WRITEL(0, PCIX0_PIM1SA);
151 PCIX_WRITEL(0, PCIX0_PIM2SA);
153 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
154 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
155 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
156 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
157 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
158 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
160 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
161 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
162 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
163 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
169 ebony_setup_hose(void)
171 struct pci_controller *hose;
173 /* Configure windows on the PCI-X host bridge */
176 hose = pcibios_alloc_controller();
181 hose->first_busno = 0;
182 hose->last_busno = 0xff;
184 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
186 pci_init_resource(&hose->io_resource,
192 pci_init_resource(&hose->mem_resources[0],
198 hose->io_space.start = EBONY_PCI_LOWER_IO;
199 hose->io_space.end = EBONY_PCI_UPPER_IO;
200 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
201 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
203 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
204 hose->io_base_virt = (void *)isa_io_base;
206 setup_indirect_pci(hose,
207 EBONY_PCI_CFGA_PLB32,
208 EBONY_PCI_CFGD_PLB32);
209 hose->set_cfg_type = 1;
211 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
213 ppc_md.pci_swizzle = common_swizzle;
214 ppc_md.pci_map_irq = ebony_map_irq;
220 ebony_early_serial_map(void)
222 struct uart_port port;
224 /* Setup ioremapped serial port access */
225 memset(&port, 0, sizeof(port));
226 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
228 port.uartclk = clocks.uart0;
230 port.iotype = SERIAL_IO_MEM;
231 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
234 if (early_serial_setup(&port) != 0) {
235 printk("Early serial init of port 0 failed\n");
238 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
239 /* Configure debug serial access */
240 gen550_init(0, &port);
243 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
245 port.uartclk = clocks.uart1;
248 if (early_serial_setup(&port) != 0) {
249 printk("Early serial init of port 1 failed\n");
252 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
253 /* Configure debug serial access */
254 gen550_init(1, &port);
259 ebony_setup_arch(void)
261 unsigned char * vpd_base;
263 struct ocp_func_emac_data *emacdata;
265 /* Set mac_addr for each EMAC */
266 vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE);
267 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
268 emacdata = def->additions;
269 memcpy(emacdata->mac_addr, EBONY_NA0_ADDR(vpd_base), 6);
270 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
271 emacdata = def->additions;
272 memcpy(emacdata->mac_addr, EBONY_NA1_ADDR(vpd_base), 6);
276 * Determine various clocks.
277 * To be completely correct we should get SysClk
278 * from FPGA, because it can be changed by on-board switches
281 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
282 ocp_sys_info.opb_bus_freq = clocks.opb;
284 /* Setup TODC access */
285 TODC_INIT(TODC_TYPE_DS1743,
288 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
291 /* init to some ~sane value until calibrate_delay() runs */
292 loops_per_jiffy = 50000000/HZ;
294 /* Setup PCI host bridge */
297 #ifdef CONFIG_BLK_DEV_INITRD
299 ROOT_DEV = Root_RAM0;
302 #ifdef CONFIG_ROOT_NFS
305 ROOT_DEV = Root_HDA1;
308 ebony_early_serial_map();
310 /* Identify the system */
311 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
314 void __init platform_init(unsigned long r3, unsigned long r4,
315 unsigned long r5, unsigned long r6, unsigned long r7)
317 parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
319 ibm44x_platform_init();
321 ppc_md.setup_arch = ebony_setup_arch;
322 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
323 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
325 ppc_md.calibrate_decr = ebony_calibrate_decr;
326 ppc_md.time_init = todc_time_init;
327 ppc_md.set_rtc_time = todc_set_rtc_time;
328 ppc_md.get_rtc_time = todc_get_rtc_time;
330 ppc_md.nvram_read_val = todc_direct_read_val;
331 ppc_md.nvram_write_val = todc_direct_write_val;
333 ppc_md.early_serial_map = ebony_early_serial_map;