2 * arch/ppc/platforms/4xx/ibmnp405h.h
4 * Author: Armin Kuster <akuster@mvista.com>
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
13 #ifndef __ASM_IBMNP405H_H__
14 #define __ASM_IBMNP405H_H__
16 #include <linux/config.h>
17 #include <asm/ibm_ocp.h>
19 /* ibm405.h at bottom of this file */
21 #define PPC405_PCI_CONFIG_ADDR 0xeec00000
22 #define PPC405_PCI_CONFIG_DATA 0xeec00004
23 #define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
25 #define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
26 #define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
27 #define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
29 #define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
30 #define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
31 #define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
32 #define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
34 #define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
36 #define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
37 #define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
38 #define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
39 #define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
40 #define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
41 #define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
42 #define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
43 #define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
45 #define OPB_BASE_START 0x40000000
46 #define EBIU_BASE_START 0xF0100000
48 /* serial port defines */
49 #define RS_TABLE_SIZE 4
53 #define PCIL0_BASE 0xEF400000
54 #define UART0_IO_BASE 0xEF600300
55 #define UART1_IO_BASE 0xEF600400
56 #define IIC0_BASE 0xEF600500
57 #define OPB0_BASE 0xEF600600
58 #define GPIO0_BASE 0xEF600700
59 #define EMAC0_BASE 0xEF600800
60 #define EMAC1_BASE 0xEF600900
61 #define EMAC2_BASE 0xEF600a00
62 #define EMAC3_BASE 0xEF600b00
63 #define ZMII0_BASE 0xEF600C10
64 #define BL_MAC_WOL 41 /* WOL */
65 #define BL_MAL_SERR 45 /* MAL SERR */
66 #define BL_MAL_TXDE 46 /* MAL TXDE */
67 #define BL_MAL_RXDE 47 /* MAL RXDE */
68 #define BL_MAL_TXEOB 17 /* MAL TX EOB */
69 #define BL_MAL_RXEOB 18 /* MAL RX EOB */
70 #define BL_MAC_ETH0 37 /* MAC */
71 #define BL_MAC_ETH1 38 /* MAC */
72 #define BL_MAC_ETH2 39 /* MAC */
73 #define BL_MAC_ETH3 40 /* MAC */
78 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
80 #define STD_UART_OP(num) \
81 { 0, BASE_BAUD, 0, UART##num##_INT, \
82 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
83 iomem_base:(u8 *) UART##num##_IO_BASE, \
84 io_type: SERIAL_IO_MEM},
86 #if defined(CONFIG_UART0_TTYS0)
87 #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
88 #define SERIAL_PORT_DFNS \
93 #if defined(CONFIG_UART0_TTYS1)
94 #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
95 #define SERIAL_PORT_DFNS \
101 /* ------------------------------------------------------------------------- */
103 #define DCRN_CHCR_BASE 0x0F1
104 #define DCRN_CHPSR_BASE 0x0B4
105 #define DCRN_CPMSR_BASE 0x0BA
106 #define DCRN_CPMFR_BASE 0x0B9
107 #define DCRN_CPMER_BASE 0x0B8
109 /* CPM Clocking & Power Mangement defines */
110 #define IBM_CPM_PCI 0x40000000 /* PCI */
111 #define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
112 #define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
113 #define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
114 #define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
115 #define IBM_CPM_EMMII 0 /* Shift value for MII */
116 #define IBM_CPM_EMRX 1 /* Shift value for recv */
117 #define IBM_CPM_EMTX 2 /* Shift value for MAC */
118 #define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
119 #define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
120 #define IBM_CPM_CPU 0x00008000 /* processor core */
121 #define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
122 #define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
123 #define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
124 #define IBM_CPM_HDLC 0x00000800 /* HDCL */
125 #define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
126 #define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
127 #define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
128 #define IBM_CPM_DMA 0x00000040 /* DMA controller */
129 #define IBM_CPM_IIC0 0x00000010 /* IIC interface */
130 #define IBM_CPM_UART0 0x00000002 /* serial port 0 */
131 #define IBM_CPM_UART1 0x00000001 /* serial port 1 */
132 /* this is the default setting for devices put to sleep when booting */
134 #define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
135 | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
136 | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
137 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
138 | IBM_CPM_EMAC3 | IBM_CPM_PCI)
140 #define DCRN_DMA0_BASE 0x100
141 #define DCRN_DMA1_BASE 0x108
142 #define DCRN_DMA2_BASE 0x110
143 #define DCRN_DMA3_BASE 0x118
144 #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
145 #define DCRN_DMASR_BASE 0x120
146 #define DCRN_EBC_BASE 0x012
147 #define DCRN_DCP0_BASE 0x014
148 #define DCRN_MAL_BASE 0x180
149 #define DCRN_OCM0_BASE 0x018
150 #define DCRN_PLB0_BASE 0x084
151 #define DCRN_PLLMR_BASE 0x0B0
152 #define DCRN_POB0_BASE 0x0A0
153 #define DCRN_SDRAM0_BASE 0x010
154 #define DCRN_UIC0_BASE 0x0C0
155 #define DCRN_UIC1_BASE 0x0D0
156 #define DCRN_CPC0_EPRCSR 0x0F3
158 #define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
159 #define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
161 #define CHR1_CETE 0x00000004 /* CPU external timer enable */
162 #define UIC0 DCRN_UIC0_BASE
163 #define UIC1 DCRN_UIC1_BASE
167 #define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
169 /* EMAC DCRN's FIXME: armin */
170 #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
171 #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
172 #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
173 #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
174 #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
175 #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
176 #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
177 #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
179 #include <asm/ibm405.h>
181 #endif /* __ASM_IBMNP405H_H__ */
182 #endif /* __KERNEL__ */