2 * arch/ppc/platforms/ocotea.c
4 * Ocotea board specific routines
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/blkdev.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/initrd.h>
31 #include <linux/irq.h>
32 #include <linux/seq_file.h>
33 #include <linux/root_dev.h>
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
38 #include <asm/system.h>
39 #include <asm/pgtable.h>
43 #include <asm/machdep.h>
45 #include <asm/pci-bridge.h>
48 #include <asm/bootinfo.h>
49 #include <asm/ppc4xx_pic.h>
50 #include <asm/ppcboot.h>
52 #include <syslib/ibm440gx_common.h>
55 * This is a horrible kludge, we eventually need to abstract this
56 * generic PHY stuff, so the standard phy mode defines can be
57 * easily used from arch code.
59 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
63 static struct ibm44x_clocks clocks __initdata;
66 ocotea_calibrate_decr(void)
70 if (mfspr(SPRN_CCR1) & CCR1_TCS)
71 freq = OCOTEA_TMR_CLK;
75 ibm44x_calibrate_decr(freq);
79 ocotea_show_cpuinfo(struct seq_file *m)
81 seq_printf(m, "vendor\t\t: IBM\n");
82 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
88 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
90 static char pci_irq_table[][4] =
92 * PCI IDSEL/INTPIN->INTLINE
96 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
97 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
98 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
99 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
102 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
106 static void __init ocotea_set_emacdata(void)
109 struct ocp_func_emac_data *emacdata;
113 * Note: Current rev. board only operates in Group 4a
114 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
115 * for RGMII (though these could run in RTBI just the same).
117 * The FPGA reg 3 information isn't even suitable for
118 * determining the phy_mode, so if the board becomes
119 * usable in !4a, it will be necessary to parse an environment
120 * variable from the firmware or similar to properly configure
121 * the phy_map/phy_mode.
123 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
124 for (i=0; i<4; i++) {
125 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
126 emacdata = def->additions;
128 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
129 emacdata->phy_mode = PHY_MODE_SMII;
132 emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
133 emacdata->phy_mode = PHY_MODE_RGMII;
136 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
138 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
140 memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
142 memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
146 #define PCIX_READW(offset) \
147 (readw((u32)pcix_reg_base+offset))
149 #define PCIX_WRITEW(value, offset) \
150 (writew(value, (u32)pcix_reg_base+offset))
152 #define PCIX_WRITEL(value, offset) \
153 (writel(value, (u32)pcix_reg_base+offset))
156 * FIXME: This is only here to "make it work". This will move
157 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
158 * configuration library. -Matt
161 ocotea_setup_pcix(void)
165 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
167 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
168 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
170 /* Disable all windows */
171 PCIX_WRITEL(0, PCIX0_POM0SA);
172 PCIX_WRITEL(0, PCIX0_POM1SA);
173 PCIX_WRITEL(0, PCIX0_POM2SA);
174 PCIX_WRITEL(0, PCIX0_PIM0SA);
175 PCIX_WRITEL(0, PCIX0_PIM0SAH);
176 PCIX_WRITEL(0, PCIX0_PIM1SA);
177 PCIX_WRITEL(0, PCIX0_PIM2SA);
178 PCIX_WRITEL(0, PCIX0_PIM2SAH);
180 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
181 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
182 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
183 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
184 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
185 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
187 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
188 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
189 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
190 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
196 ocotea_setup_hose(void)
198 struct pci_controller *hose;
200 /* Configure windows on the PCI-X host bridge */
203 hose = pcibios_alloc_controller();
208 hose->first_busno = 0;
209 hose->last_busno = 0xff;
211 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
213 pci_init_resource(&hose->io_resource,
219 pci_init_resource(&hose->mem_resources[0],
220 OCOTEA_PCI_LOWER_MEM,
221 OCOTEA_PCI_UPPER_MEM,
225 hose->io_space.start = OCOTEA_PCI_LOWER_IO;
226 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
227 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
228 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
230 (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
231 hose->io_base_virt = (void *)isa_io_base;
233 setup_indirect_pci(hose,
234 OCOTEA_PCI_CFGA_PLB32,
235 OCOTEA_PCI_CFGD_PLB32);
236 hose->set_cfg_type = 1;
238 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
240 ppc_md.pci_swizzle = common_swizzle;
241 ppc_md.pci_map_irq = ocotea_map_irq;
248 ocotea_early_serial_map(void)
250 struct uart_port port;
252 /* Setup ioremapped serial port access */
253 memset(&port, 0, sizeof(port));
254 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
255 port.irq = UART0_INT;
256 port.uartclk = clocks.uart0;
258 port.iotype = SERIAL_IO_MEM;
259 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
262 if (early_serial_setup(&port) != 0) {
263 printk("Early serial init of port 0 failed\n");
266 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
267 port.irq = UART1_INT;
268 port.uartclk = clocks.uart1;
271 if (early_serial_setup(&port) != 0) {
272 printk("Early serial init of port 1 failed\n");
277 ocotea_setup_arch(void)
279 ocotea_set_emacdata();
281 ibm440gx_tah_enable();
283 #if !defined(CONFIG_BDI_SWITCH)
285 * The Abatron BDI JTAG debugger does not tolerate others
286 * mucking with the debug registers.
288 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
292 * Determine various clocks.
293 * To be completely correct we should get SysClk
294 * from FPGA, because it can be changed by on-board switches
297 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
298 ocp_sys_info.opb_bus_freq = clocks.opb;
300 /* Setup TODC access */
301 TODC_INIT(TODC_TYPE_DS1743,
304 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
307 /* init to some ~sane value until calibrate_delay() runs */
308 loops_per_jiffy = 50000000/HZ;
310 /* Setup PCI host bridge */
313 #ifdef CONFIG_BLK_DEV_INITRD
315 ROOT_DEV = Root_RAM0;
318 #ifdef CONFIG_ROOT_NFS
321 ROOT_DEV = Root_HDA1;
324 ocotea_early_serial_map();
326 /* Identify the system */
327 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
330 void __init platform_init(unsigned long r3, unsigned long r4,
331 unsigned long r5, unsigned long r6, unsigned long r7)
333 parse_bootinfo(find_bootinfo());
336 * If we were passed in a board information, copy it into the
337 * residual data area.
340 __res = *(bd_t *)(r3 + KERNELBASE);
342 /* Disable L2-Cache due to hardware issues */
343 ibm440gx_l2c_disable();
345 ibm44x_platform_init();
347 ppc_md.setup_arch = ocotea_setup_arch;
348 ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
349 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
351 ppc_md.calibrate_decr = ocotea_calibrate_decr;
352 ppc_md.time_init = todc_time_init;
353 ppc_md.set_rtc_time = todc_set_rtc_time;
354 ppc_md.get_rtc_time = todc_get_rtc_time;
356 ppc_md.nvram_read_val = todc_direct_read_val;
357 ppc_md.nvram_write_val = todc_direct_write_val;
360 ppc_md.early_serial_map = ocotea_early_serial_map;