arch/ppc/platforms/4xx/sycamore.c

   1 /*
   2  * arch/ppc/platforms/4xx/sycamore.c
   3  *
   4  * Architecture- / platform-specific boot-time initialization code for
   5  * IBM PowerPC 4xx based boards.
   6  *
   7  * Author: Armin Kuster <akuster@mvista.com>
   8  *
   9  * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/smp.h>
  17 #include <linux/threads.h>
  18 #include <linux/param.h>
  19 #include <linux/string.h>
  20 #include <linux/pci.h>
  21 #include <linux/rtc.h>
  22
  23 #include <asm/ocp.h>
  24 #include <asm/ppc4xx_pic.h>
  25 #include <asm/system.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/machdep.h>
  28 #include <asm/page.h>
  29 #include <asm/time.h>
  30 #include <asm/io.h>
  31 #include <asm/todc.h>
  32
  33 #undef DEBUG
  34
  35 #ifdef DEBUG
  36 #define DBG(x...) printk(x)
  37 #else
  38 #define DBG(x...)
  39 #endif
  40
  41 void *kb_cs;
  42 void *kb_data;
  43 void *sycamore_rtc_base;
  44
  45 /*
  46  * Define all of the IRQ senses and polarities.
  47  */
  48
  49 static u_char Sycamore_IRQ_initsenses[] __initdata = {
  50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 0: Uart 0*/
  51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 1: Uart 1*/
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 2: IIC */
  53         (IRQ_SENSE_EDGE  | IRQ_POLARITY_POSITIVE),      /* 3: External Master */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 4: PCI ext cmd write*/
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 5: DMA Chan 0 */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 6: DMA Chan 1 */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 7: DMA Chan 2 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 8: DMA Chan 3 */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 9: Ethernet wakeup (WOL)*/
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 10: Mal (SEER) */
  61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 11: Mal TXEOB */
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 12: Mal RXEOB */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 13: Mal TXDE*/
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 14: Mal RXDE*/
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 15: Ethernet */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 16: Ext PCI SERR */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 17: ECC */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 18: PCI PM*/
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 19: Ext Int 7 */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 20: Ext Int 8 */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 21: Ext Int 9 */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 22: Ext Int 10 */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 23: Ext Int 11 */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 24: Ext Int 12 */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 25: Ext Int 0 */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 26: Ext Int 1 */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 27: Ext Int 2 */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 28: Ext Int 3 */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 29: Ext Int 4 */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 30: Ext Int 5 */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 31: Ext Int 6 */
  82 };
  83
  84
  85 /* Some IRQs unique to Sycamore.
  86  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  87  */
  88 int __init
  89 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  90 {
  91         static char pci_irq_table[][4] =
  92             /*
  93              *      PCI IDSEL/INTPIN->INTLINE
  94              *      A       B       C       D
  95              */
  96         {
  97                 {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
  98                 {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
  99                 {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
 100                 {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
 101         };
 102
 103         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 104         return PCI_IRQ_TABLE_LOOKUP;
 105 };
 106
 107 void __init
 108 sycamore_setup_arch(void)
 109 {
 110 #define SYCAMORE_PS2_BASE       0xF0100000
 111 #define SYCAMORE_FPGA_BASE      0xF0300000
 112
 113         void *fpga_brdc;
 114         unsigned char fpga_brdc_data;
 115         void *fpga_enable;
 116         void *fpga_polarity;
 117         void *fpga_status;
 118         void *fpga_trigger;
 119
 120         ppc4xx_setup_arch();
 121
 122         kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
 123         if (!kb_data) {
 124                 printk(KERN_CRIT
 125                        "sycamore_setup_arch() kb_data ioremap failed\n");
 126                 return;
 127         }
 128
 129         kb_cs = kb_data + 1;
 130
 131         fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
 132         if (!fpga_status) {
 133                 printk(KERN_CRIT
 134                        "sycamore_setup_arch() fpga_status ioremap failed\n");
 135                 return;
 136         }
 137
 138         fpga_enable = fpga_status + 1;
 139         fpga_polarity = fpga_status + 2;
 140         fpga_trigger = fpga_status + 3;
 141         fpga_brdc = fpga_status + 4;
 142
 143         /* split the keyboard and mouse interrupts */
 144         fpga_brdc_data = readb(fpga_brdc);
 145         fpga_brdc_data |= 0x80;
 146         writeb(fpga_brdc_data, fpga_brdc);
 147
 148         writeb(0x3, fpga_enable);
 149
 150         writeb(0x3, fpga_polarity);
 151
 152         writeb(0x3, fpga_trigger);
 153
 154         /* RTC step for the sycamore */
 155         sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
 156         TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
 157                   sycamore_rtc_base, 8);
 158         ibm4xxPIC_InitSenses = Sycamore_IRQ_initsenses;
 159         ibm4xxPIC_NumInitSenses = sizeof(Sycamore_IRQ_initsenses);
 160
 161         /* Identify the system */
 162         printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
 163         printk(KERN_INFO
 164                "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 165 }
 166
 167 void __init
 168 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 169 {
 170 #ifdef CONFIG_PCI
 171         unsigned int bar_response, bar;
 172         /*
 173          * Expected PCI mapping:
 174          *
 175          *  PLB addr             PCI memory addr
 176          *  ---------------------       ---------------------
 177          *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 178          *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 179          *
 180          *  PLB addr             PCI io addr
 181          *  ---------------------       ---------------------
 182          *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 183          *
 184          * The following code is simplified by assuming that the bootrom
 185          * has been well behaved in following this mapping.
 186          */
 187
 188 #ifdef DEBUG
 189         int i;
 190
 191         printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 192         printk("PCI bridge regs before fixup \n");
 193         for (i = 0; i <= 3; i++) {
 194                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 195                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 196                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 197                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 198         }
 199         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 200         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 201         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 202         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 203
 204 #endif
 205
 206         /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 207
 208         /* Disable region first */
 209         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 210         /* PLB starting addr, PCI: 0x80000000 */
 211         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 212         /* PCI start addr, 0x80000000 */
 213         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 214         /* 512MB range of PLB to PCI */
 215         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 216         /* Enable no pre-fetch, enable region */
 217         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 218                                                 (PPC405_PCI_UPPER_MEM -
 219                                                  PPC405_PCI_MEM_BASE)) | 0x01));
 220
 221         /* Disable region one */
 222         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 223         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 224         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 225         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 226         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 227         out_le32((void *) &(pcip->ptm1ms), 0x00000000);
 228
 229         /* Disable region two */
 230         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 231         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 232         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 233         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 234         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 235         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 236
 237         /* Zero config bars */
 238         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 239                 early_write_config_dword(hose, hose->first_busno,
 240                                          PCI_FUNC(hose->first_busno), bar,
 241                                          0x00000000);
 242                 early_read_config_dword(hose, hose->first_busno,
 243                                         PCI_FUNC(hose->first_busno), bar,
 244                                         &bar_response);
 245                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 246                     hose->first_busno, PCI_SLOT(hose->first_busno),
 247                     PCI_FUNC(hose->first_busno), bar, bar_response);
 248         }
 249         /* end work arround */
 250
 251 #ifdef DEBUG
 252         printk("PCI bridge regs after fixup \n");
 253         for (i = 0; i <= 3; i++) {
 254                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 255                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 256                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 257                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 258         }
 259         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 260         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 261         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 262         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 263
 264 #endif
 265 #endif
 266
 267 }
 268
 269 void __init
 270 sycamore_map_io(void)
 271 {
 272         ppc4xx_map_io();
 273         io_block_mapping(SYCAMORE_RTC_VADDR,
 274                          SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
 275 }
 276
 277 void __init
 278 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 279               unsigned long r6, unsigned long r7)
 280 {
 281         ppc4xx_init(r3, r4, r5, r6, r7);
 282
 283         ppc_md.setup_arch = sycamore_setup_arch;
 284         ppc_md.setup_io_mappings = sycamore_map_io;
 285
 286         ppc_md.time_init = todc_time_init;
 287         ppc_md.set_rtc_time = todc_set_rtc_time;
 288         ppc_md.get_rtc_time = todc_get_rtc_time;
 289         ppc_md.nvram_read_val = todc_direct_read_val;
 290         ppc_md.nvram_write_val = todc_direct_write_val;
 291 }