2 * arch/ppc/platform/85xx/sbc85xx.c
4 * WindRiver PowerQUICC III SBC85xx board common routines
6 * Copyright 2002, 2003 Motorola Inc.
7 * Copyright 2004 Red Hat, Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/config.h>
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/irq.h>
27 #include <linux/seq_file.h>
28 #include <linux/serial.h>
29 #include <linux/module.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
34 #include <asm/atomic.h>
37 #include <asm/machdep.h>
39 #include <asm/open_pic.h>
40 #include <asm/bootinfo.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/mpc85xx.h>
44 #include <asm/immap_85xx.h>
46 #include <mm/mmu_decl.h>
48 #include <platforms/85xx/sbc85xx.h>
50 unsigned char __res[sizeof (bd_t)];
53 unsigned long isa_io_base = 0;
54 unsigned long isa_mem_base = 0;
55 unsigned long pci_dram_offset = 0;
58 extern unsigned long total_memory; /* in mm/init */
60 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
62 static u_char sbc8560_openpic_initsenses[] __initdata = {
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
95 0x0, /* External 0: */
96 0x0, /* External 1: */
97 #if defined(CONFIG_PCI)
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 0 */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 1 */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 2 */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PCI slot 3 */
103 0x0, /* External 2: */
104 0x0, /* External 3: */
105 0x0, /* External 4: */
106 0x0, /* External 5: */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 6: PHY */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
110 0x0, /* External 8: */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: PHY */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 10: PHY */
113 0x0, /* External 11: */
116 /* ************************************************************************ */
118 sbc8560_show_cpuinfo(struct seq_file *m)
120 uint pvid, svid, phid1;
121 uint memsize = total_memory;
122 bd_t *binfo = (bd_t *) __res;
125 /* get the core frequency */
126 freq = binfo->bi_intfreq;
131 seq_printf(m, "Vendor\t\t: Wind River\n");
133 switch (svid & 0xffff0000) {
135 seq_printf(m, "Machine\t\t: hhmmm, this board isn't made yet!\n");
138 seq_printf(m, "Machine\t\t: SBC8560\n");
141 seq_printf(m, "Machine\t\t: unknown\n");
144 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
145 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
146 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
148 /* Display cpu Pll setting */
150 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
152 /* Display the amount of memory */
153 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
159 sbc8560_init_IRQ(void)
161 bd_t *binfo = (bd_t *) __res;
162 /* Determine the Physical Address of the OpenPIC regs */
163 phys_addr_t OpenPIC_PAddr =
164 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
165 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
166 OpenPIC_InitSenses = sbc8560_openpic_initsenses;
167 OpenPIC_NumInitSenses = sizeof (sbc8560_openpic_initsenses);
169 /* Skip reserved space and internal sources */
170 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
171 /* Map PIC IRQs 0-11 */
172 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
174 /* we let openpic interrupts starting from an offset, to
175 * leave space for cascading interrupts underneath.
177 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
187 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
190 static char pci_irq_table[][4] =
192 * PCI IDSEL/INTPIN->INTLINE
196 {PIRQA, PIRQB, PIRQC, PIRQD},
197 {PIRQD, PIRQA, PIRQB, PIRQC},
198 {PIRQC, PIRQD, PIRQA, PIRQB},
199 {PIRQB, PIRQC, PIRQD, PIRQA},
202 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
203 return PCI_IRQ_TABLE_LOOKUP;
206 int mpc85xx_exclude_device(u_char bus, u_char devfn)
208 if (bus == 0 && PCI_SLOT(devfn) == 0)
209 return PCIBIOS_DEVICE_NOT_FOUND;
211 return PCIBIOS_SUCCESSFUL;
213 #endif /* CONFIG_PCI */