arch/ppc/platforms/katana.h

   1 /*
   2  * arch/ppc/platforms/katana.h
   3  *
   4  * Definitions for Artesyn Katana750i/3750 board.
   5  *
   6  * Tim Montgomery <timm@artesyncp.com>
   7  *
   8  * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
   9  * Based on code done by Mark A. Greer <mgreer@mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  */
  16
  17 /*
  18  * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
  19  * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
  20  * We'll only use one PCI MEM window on each PCI bus.
  21  *
  22  * This is the CPU physical memory map (windows must be at least 1MB and start
  23  * on a boundary that is a multiple of the window size):
  24  *
  25  *    0xff800000-0xffffffff      - Boot window
  26  *    0xf8400000-0xf85fffff      - Internal SRAM
  27  *    0xf8200000-0xf823ffff      - CPLD
  28  *    0xf8100000-0xf810ffff      - MV64360 Registers
  29  *    0xf8000000-0xf80fffff      - PLCC socket
  30  *    0xf0000000-0xf01fffff      - Consistent memory pool
  31  *    0xe8000000-0xefffffff      - soldered flash
  32  *    0xc0000000-0xc0ffffff      - PCI I/O
  33  *    0x80000000-0xbfffffff      - PCI MEM
  34  */
  35
  36 #ifndef __PPC_PLATFORMS_KATANA_H
  37 #define __PPC_PLATFORMS_KATANA_H
  38
  39 /* CPU Physical Memory Map setup. */
  40 #define KATANA_BOOT_WINDOW_BASE                 0xff800000
  41 #define KATANA_INTERNAL_SRAM_BASE               0xf8400000
  42 #define KATANA_CPLD_BASE                        0xf8200000
  43 #define KATANA_BRIDGE_REG_BASE                  0xf8100000
  44 #define KATANA_SOCKET_BASE                      0xf8000000
  45 #define KATANA_SOLDERED_FLASH_BASE              0xe8000000
  46
  47 #define KATANA_BOOT_WINDOW_SIZE_ACTUAL          0x00800000 /* 8MB */
  48 #define KATANA_CPLD_SIZE_ACTUAL                 0x00020000 /* 128KB */
  49 #define KATANA_SOCKETED_FLASH_SIZE_ACTUAL       0x00080000 /* 512KB */
  50 #define KATANA_SOLDERED_FLASH_SIZE_ACTUAL       0x02000000 /* 32MB */
  51
  52 #define KATANA_BOOT_WINDOW_SIZE         max(MV64360_WINDOW_SIZE_MIN,    \
  53                 KATANA_BOOT_WINDOW_SIZE_ACTUAL)
  54 #define KATANA_CPLD_SIZE                max(MV64360_WINDOW_SIZE_MIN,    \
  55                 KATANA_CPLD_SIZE_ACTUAL)
  56 #define KATANA_SOCKETED_FLASH_SIZE      max(MV64360_WINDOW_SIZE_MIN,    \
  57                 KATANA_SOCKETED_FLASH_SIZE_ACTUAL)
  58 #define KATANA_SOLDERED_FLASH_SIZE      max(MV64360_WINDOW_SIZE_MIN,    \
  59                 KATANA_SOLDERED_FLASH_SIZE_ACTUAL)
  60
  61 #define KATANA_PCI1_MEM_START_PROC_ADDR         0x80000000
  62 #define KATANA_PCI1_MEM_START_PCI_HI_ADDR       0x00000000
  63 #define KATANA_PCI1_MEM_START_PCI_LO_ADDR       0x80000000
  64 #define KATANA_PCI1_MEM_SIZE                    0x40000000
  65 #define KATANA_PCI1_IO_START_PROC_ADDR          0xc0000000
  66 #define KATANA_PCI1_IO_START_PCI_ADDR           0x00000000
  67 #define KATANA_PCI1_IO_SIZE                     0x01000000
  68
  69 /* Board-specific IRQ info */
  70 #define  KATANA_PCI_INTA_IRQ_3750               64+8
  71 #define  KATANA_PCI_INTB_IRQ_3750               64+9
  72 #define  KATANA_PCI_INTC_IRQ_3750               64+10
  73
  74 #define  KATANA_PCI_INTA_IRQ_750i               64+8
  75 #define  KATANA_PCI_INTB_IRQ_750i               64+9
  76 #define  KATANA_PCI_INTC_IRQ_750i               64+10
  77 #define  KATANA_PCI_INTD_IRQ_750i               64+14
  78
  79 #define KATANA_CPLD_RST_EVENT                   0x00000000
  80 #define KATANA_CPLD_RST_CMD                     0x00001000
  81 #define KATANA_CPLD_PCI_ERR_INT_EN              0x00002000
  82 #define KATANA_CPLD_PCI_ERR_INT_PEND            0x00003000
  83 #define KATANA_CPLD_PRODUCT_ID                  0x00004000
  84 #define KATANA_CPLD_EREADY                      0x00005000
  85
  86 #define KATANA_CPLD_HARDWARE_VER                0x00007000
  87 #define KATANA_CPLD_PLD_VER                     0x00008000
  88 #define KATANA_CPLD_BD_CFG_0                    0x00009000
  89 #define KATANA_CPLD_BD_CFG_1                    0x0000a000
  90 #define KATANA_CPLD_BD_CFG_3                    0x0000c000
  91 #define KATANA_CPLD_LED                         0x0000d000
  92 #define KATANA_CPLD_RESET_OUT                   0x0000e000
  93
  94 #define KATANA_CPLD_RST_EVENT_INITACT           0x80
  95 #define KATANA_CPLD_RST_EVENT_SW                0x40
  96 #define KATANA_CPLD_RST_EVENT_WD                0x20
  97 #define KATANA_CPLD_RST_EVENT_COPS              0x10
  98 #define KATANA_CPLD_RST_EVENT_COPH              0x08
  99 #define KATANA_CPLD_RST_EVENT_CPCI              0x02
 100 #define KATANA_CPLD_RST_EVENT_FP                0x01
 101
 102 #define KATANA_CPLD_RST_CMD_SCL                 0x80
 103 #define KATANA_CPLD_RST_CMD_SDA                 0x40
 104 #define KATANA_CPLD_RST_CMD_I2C                 0x10
 105 #define KATANA_CPLD_RST_CMD_FR                  0x08
 106 #define KATANA_CPLD_RST_CMD_SR                  0x04
 107 #define KATANA_CPLD_RST_CMD_HR                  0x01
 108
 109 #define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK        0xc0
 110 #define KATANA_CPLD_BD_CFG_0_SYSCLK_200         0x00
 111 #define KATANA_CPLD_BD_CFG_0_SYSCLK_166         0x80
 112 #define KATANA_CPLD_BD_CFG_0_SYSCLK_133         0xc0
 113 #define KATANA_CPLD_BD_CFG_0_SYSCLK_100         0x40
 114
 115 #define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK       0x03
 116 #define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB       0x00
 117 #define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB       0x01
 118 #define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB       0x02
 119 #define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB      0x03
 120
 121 #define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK  0x04
 122 #define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE   0x00
 123 #define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO   0x04
 124
 125 #define KATANA_CPLD_BD_CFG_3_MONARCH            0x04
 126
 127 #define KATANA_CPLD_RESET_OUT_PORTSEL           0x80
 128 #define KATANA_CPLD_RESET_OUT_WD                0x20
 129 #define KATANA_CPLD_RESET_OUT_COPH              0x08
 130 #define KATANA_CPLD_RESET_OUT_PCI_RST_PCI       0x02
 131 #define KATANA_CPLD_RESET_OUT_PCI_RST_FP        0x01
 132
 133 #define KATANA_MBOX_RESET_REQUEST               0xC83A
 134 #define KATANA_MBOX_RESET_ACK                   0xE430
 135 #define KATANA_MBOX_RESET_DONE                  0x32E5
 136
 137 #define HSL_PLD_BASE                            0x00010000
 138 #define HSL_PLD_J4SGA_REG_OFF                   0
 139 #define HSL_PLD_J4GA_REG_OFF                    1
 140 #define HSL_PLD_J2GA_REG_OFF                    2
 141 #define GA_MASK                                 0x1f
 142 #define HSL_PLD_SIZE                            0x1000
 143 #define K3750_GPP_GEO_ADDR_PINS                 0xf8000000
 144 #define K3750_GPP_GEO_ADDR_SHIFT                27
 145
 146 #define K3750_GPP_EVENT_PROC_0                  (1 << 21)
 147 #define K3750_GPP_EVENT_PROC_1_2                (1 << 2)
 148
 149 #define PCI_VENDOR_ID_ARTESYN                   0x1223
 150 #define PCI_DEVICE_ID_KATANA_3750_PROC0         0x0041
 151 #define PCI_DEVICE_ID_KATANA_3750_PROC1         0x0042
 152 #define PCI_DEVICE_ID_KATANA_3750_PROC2         0x0043
 153
 154 #define COPROC_MEM_FUNCTION                     0
 155 #define COPROC_MEM_BAR                          0
 156 #define COPROC_REGS_FUNCTION                    0
 157 #define COPROC_REGS_BAR                         4
 158 #define COPROC_FLASH_FUNCTION                   2
 159 #define COPROC_FLASH_BAR                        4
 160
 161 #define KATANA_IPMB_LOCAL_I2C_ADDR              0x08
 162
 163 #define KATANA_DEFAULT_BAUD                     9600
 164 #define KATANA_MPSC_CLK_SRC                     8         /* TCLK */
 165 #define KATANA_MPSC_CLK_FREQ                    133333333 /* 133.3333... MHz */
 166
 167 #define KATANA_ETH0_PHY_ADDR                    12
 168 #define KATANA_ETH1_PHY_ADDR                    11
 169 #define KATANA_ETH2_PHY_ADDR                    4
 170
 171 #define KATANA_PRODUCT_ID_3750                  0x01
 172 #define KATANA_PRODUCT_ID_750i                  0x02
 173 #define KATANA_PRODUCT_ID_752i                  0x04
 174
 175 #define KATANA_ETH_TX_QUEUE_SIZE                800
 176 #define KATANA_ETH_RX_QUEUE_SIZE                400
 177
 178 #define KATANA_ETH_PORT_CONFIG_VALUE                    \
 179         ETH_UNICAST_NORMAL_MODE                 |       \
 180         ETH_DEFAULT_RX_QUEUE_0                  |       \
 181         ETH_DEFAULT_RX_ARP_QUEUE_0              |       \
 182         ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP         |       \
 183         ETH_RECEIVE_BC_IF_IP                    |       \
 184         ETH_RECEIVE_BC_IF_ARP                   |       \
 185         ETH_CAPTURE_TCP_FRAMES_DIS              |       \
 186         ETH_CAPTURE_UDP_FRAMES_DIS              |       \
 187         ETH_DEFAULT_RX_TCP_QUEUE_0              |       \
 188         ETH_DEFAULT_RX_UDP_QUEUE_0              |       \
 189         ETH_DEFAULT_RX_BPDU_QUEUE_0
 190
 191 #define KATANA_ETH_PORT_CONFIG_EXTEND_VALUE             \
 192         ETH_SPAN_BPDU_PACKETS_AS_NORMAL         |       \
 193         ETH_PARTITION_DISABLE
 194
 195 #define GT_ETH_IPG_INT_RX(value)                        \
 196         ((value & 0x3fff) << 8)
 197
 198 #define KATANA_ETH_PORT_SDMA_CONFIG_VALUE               \
 199         ETH_RX_BURST_SIZE_4_64BIT               |       \
 200         GT_ETH_IPG_INT_RX(0)                    |       \
 201         ETH_TX_BURST_SIZE_4_64BIT
 202
 203 #define KATANA_ETH_PORT_SERIAL_CONTROL_VALUE            \
 204         ETH_FORCE_LINK_PASS                     |       \
 205         ETH_ENABLE_AUTO_NEG_FOR_DUPLX           |       \
 206         ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL      |       \
 207         ETH_ADV_SYMMETRIC_FLOW_CTRL             |       \
 208         ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX       |       \
 209         ETH_FORCE_BP_MODE_NO_JAM                |       \
 210         BIT9                                    |       \
 211         ETH_DO_NOT_FORCE_LINK_FAIL              |       \
 212         ETH_RETRANSMIT_16_ATTEMPTS              |       \
 213         ETH_ENABLE_AUTO_NEG_SPEED_GMII          |       \
 214         ETH_DTE_ADV_0                           |       \
 215         ETH_DISABLE_AUTO_NEG_BYPASS             |       \
 216         ETH_AUTO_NEG_NO_CHANGE                  |       \
 217         ETH_MAX_RX_PACKET_9700BYTE              |       \
 218         ETH_CLR_EXT_LOOPBACK                    |       \
 219         ETH_SET_FULL_DUPLEX_MODE                |       \
 220         ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
 221
 222 #ifndef __ASSEMBLY__
 223
 224 typedef enum {
 225         KATANA_ID_3750,
 226         KATANA_ID_750I,
 227         KATANA_ID_752I,
 228         KATANA_ID_MAX
 229 } katana_id_t;
 230
 231 #endif
 232
 233 #endif                          /* __PPC_PLATFORMS_KATANA_H */