VServer 1.9.2 (patch-2.6.8.1-vs1.9.2.diff)
[linux-2.6.git] / arch / ppc / platforms / lopec_setup.c
1 /*
2  * arch/ppc/platforms/lopec_setup.c
3  *
4  * Setup routines for the Motorola LoPEC.
5  *
6  * Author: Dan Cox
7  *         danc@mvista.com
8  *
9  * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
10  * the terms of the GNU General Public License version 2.  This program
11  * is licensed "as is" without any warranty of any kind, whether express
12  * or implied.
13  */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/delay.h>
18 #include <linux/pci_ids.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/ide.h>
22 #include <linux/seq_file.h>
23 #include <linux/initrd.h>
24 #include <linux/console.h>
25 #include <linux/root_dev.h>
26
27 #include <asm/io.h>
28 #include <asm/open_pic.h>
29 #include <asm/i8259.h>
30 #include <asm/todc.h>
31 #include <asm/bootinfo.h>
32 #include <asm/mpc10x.h>
33 #include <asm/hw_irq.h>
34 #include <asm/prep_nvram.h>
35
36 extern void lopec_find_bridges(void);
37
38 /*
39  * Define all of the IRQ senses and polarities.  Taken from the
40  * LoPEC Programmer's Reference Guide.
41  */
42 static u_char lopec_openpic_initsenses[16] __initdata = {
43         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 0 */
44         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 1 */
45         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 2 */
46         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 3 */
47         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 4 */
48         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 5 */
49         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 6 */
50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 7 */
51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 8 */
52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 9 */
53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 10 */
54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 11 */
55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 12 */
56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 13 */
57         (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),       /* IRQ 14 */
58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* IRQ 15 */
59 };
60
61 static int
62 lopec_show_cpuinfo(struct seq_file *m)
63 {
64         seq_printf(m, "machine\t\t: Motorola LoPEC\n");
65         return 0;
66 }
67
68 static u32
69 lopec_irq_canonicalize(u32 irq)
70 {
71         if (irq == 2)
72                 return 9;
73         else
74                 return irq;
75 }
76
77 static void
78 lopec_restart(char *cmd)
79 {
80 #define LOPEC_SYSSTAT1 0xffe00000
81         /* force a hard reset, if possible */
82         unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
83         reg |= 0x80;
84         *((unsigned char *) LOPEC_SYSSTAT1) = reg;
85
86         local_irq_disable();
87         while(1);
88 #undef LOPEC_SYSSTAT1
89 }
90
91 static void
92 lopec_halt(void)
93 {
94         local_irq_disable();
95         while(1);
96 }
97
98 static void
99 lopec_power_off(void)
100 {
101         lopec_halt();
102 }
103
104 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
105 int lopec_ide_ports_known = 0;
106 static unsigned long lopec_ide_regbase[MAX_HWIFS];
107 static unsigned long lopec_ide_ctl_regbase[MAX_HWIFS];
108 static unsigned long lopec_idedma_regbase;
109
110 static void
111 lopec_ide_probe(void)
112 {
113         struct pci_dev *dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
114                                               PCI_DEVICE_ID_WINBOND_82C105,
115                                               NULL);
116         lopec_ide_ports_known = 1;
117
118         if (dev) {
119                 lopec_ide_regbase[0] = dev->resource[0].start;
120                 lopec_ide_regbase[1] = dev->resource[2].start;
121                 lopec_ide_ctl_regbase[0] = dev->resource[1].start;
122                 lopec_ide_ctl_regbase[1] = dev->resource[3].start;
123                 lopec_idedma_regbase = dev->resource[4].start;
124         }
125 }
126
127 static int
128 lopec_ide_default_irq(unsigned long base)
129 {
130         if (lopec_ide_ports_known == 0)
131                 lopec_ide_probe();
132
133         if (base == lopec_ide_regbase[0])
134                 return 14;
135         else if (base == lopec_ide_regbase[1])
136                 return 15;
137         else
138                 return 0;
139 }
140
141 static unsigned long
142 lopec_ide_default_io_base(int index)
143 {
144         if (lopec_ide_ports_known == 0)
145                 lopec_ide_probe();
146         return lopec_ide_regbase[index];
147 }
148
149 static void __init
150 lopec_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data,
151                           unsigned long ctl, int *irq)
152 {
153         unsigned long reg = data;
154         uint alt_status_base;
155         int i;
156
157         for(i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
158                 hw->io_ports[i] = reg++;
159
160         if (data == lopec_ide_regbase[0]) {
161                 alt_status_base = lopec_ide_ctl_regbase[0] + 2;
162                 hw->irq = 14;
163         }
164         else if (data == lopec_ide_regbase[1]) {
165                 alt_status_base = lopec_ide_ctl_regbase[1] + 2;
166                 hw->irq = 15;
167         }
168         else {
169                 alt_status_base = 0;
170                 hw->irq = 0;
171         }
172
173         if (ctl)
174                 hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
175         else
176                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
177
178         if (irq != NULL)
179                 *irq = hw->irq;
180
181 }
182 #endif /* BLK_DEV_IDE */
183
184 static void __init
185 lopec_init_IRQ(void)
186 {
187         int i;
188
189         /*
190          * Provide the open_pic code with the correct table of interrupts.
191          */
192         OpenPIC_InitSenses = lopec_openpic_initsenses;
193         OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
194
195         mpc10x_set_openpic();
196
197         /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
198         openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
199                         &i8259_irq);
200
201         /* Map i8259 interrupts */
202         for(i = 0; i < NUM_8259_INTERRUPTS; i++)
203                 irq_desc[i].handler = &i8259_pic;
204
205         /*
206          * The EPIC allows for a read in the range of 0xFEF00000 ->
207          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
208          */
209         i8259_init(0xfef00000);
210 }
211
212 static int __init
213 lopec_request_io(void)
214 {
215         outb(0x00, 0x4d0);
216         outb(0xc0, 0x4d1);
217
218         request_region(0x00, 0x20, "dma1");
219         request_region(0x20, 0x20, "pic1");
220         request_region(0x40, 0x20, "timer");
221         request_region(0x80, 0x10, "dma page reg");
222         request_region(0xa0, 0x20, "pic2");
223         request_region(0xc0, 0x20, "dma2");
224
225         return 0;
226 }
227
228 device_initcall(lopec_request_io);
229
230 static void __init
231 lopec_map_io(void)
232 {
233         io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
234         io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
235 }
236
237 static void __init
238 lopec_set_bat(void)
239 {
240         unsigned long batu, batl;
241
242         __asm__ __volatile__(
243                 "lis %0,0xf800\n \
244                  ori %1,%0,0x002a\n \
245                  ori %0,%0,0x0ffe\n \
246                  mtspr 0x21e,%0\n \
247                  mtspr 0x21f,%1\n \
248                  isync\n \
249                  sync "
250                 : "=r" (batu), "=r" (batl));
251 }
252
253 #ifdef  CONFIG_SERIAL_TEXT_DEBUG
254 #include <linux/serial.h>
255 #include <linux/serialP.h>
256 #include <linux/serial_reg.h>
257 #include <asm/serial.h>
258
259 static struct serial_state rs_table[RS_TABLE_SIZE] = {
260         SERIAL_PORT_DFNS        /* Defined in <asm/serial.h> */
261 };
262
263 volatile unsigned char *com_port;
264 volatile unsigned char *com_port_lsr;
265
266 static void
267 serial_writechar(char c)
268 {
269         while ((*com_port_lsr & UART_LSR_THRE) == 0)
270                 ;
271         *com_port = c;
272 }
273
274 void
275 lopec_progress(char *s, unsigned short hex)
276 {
277         volatile char c;
278
279         com_port = (volatile unsigned char *) rs_table[0].port;
280         com_port_lsr = com_port + UART_LSR;
281
282         while ((c = *s++) != 0)
283                 serial_writechar(c);
284
285         /* Most messages don't have a newline in them */
286         serial_writechar('\n');
287         serial_writechar('\r');
288 }
289 #endif  /* CONFIG_SERIAL_TEXT_DEBUG */
290
291 TODC_ALLOC();
292
293 static void __init
294 lopec_setup_arch(void)
295 {
296
297         TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
298                   ioremap(0xffe80000, 0x8000), 8);
299
300         loops_per_jiffy = 100000000/HZ;
301
302         lopec_find_bridges();
303
304 #ifdef CONFIG_BLK_DEV_INITRD
305         if (initrd_start)
306                 ROOT_DEV = Root_RAM0;
307         else
308 #elif defined(CONFIG_ROOT_NFS)
309                 ROOT_DEV = Root_NFS;
310 #elif defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
311                 ROOT_DEV = Root_HDA1;
312 #else
313                 ROOT_DEV = Root_SDA1;
314 #endif
315
316 #ifdef CONFIG_VT
317         conswitchp = &dummy_con;
318 #endif
319 #ifdef CONFIG_PPCBUG_NVRAM
320         /* Read in NVRAM data */
321         init_prep_nvram();
322
323         /* if no bootargs, look in NVRAM */
324         if ( cmd_line[0] == '\0' ) {
325                 char *bootargs;
326                  bootargs = prep_nvram_get_var("bootargs");
327                  if (bootargs != NULL) {
328                          strcpy(cmd_line, bootargs);
329                          /* again.. */
330                          strcpy(saved_command_line, cmd_line);
331                 }
332         }
333 #endif
334 }
335
336 void __init
337 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
338               unsigned long r6, unsigned long r7)
339 {
340         parse_bootinfo(find_bootinfo());
341         lopec_set_bat();
342
343         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
344         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
345         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
346         ISA_DMA_THRESHOLD = 0x00ffffff;
347         DMA_MODE_READ = 0x44;
348         DMA_MODE_WRITE = 0x48;
349
350         ppc_md.setup_arch = lopec_setup_arch;
351         ppc_md.show_cpuinfo = lopec_show_cpuinfo;
352         ppc_md.irq_canonicalize = lopec_irq_canonicalize;
353         ppc_md.init_IRQ = lopec_init_IRQ;
354         ppc_md.get_irq = openpic_get_irq;
355
356         ppc_md.restart = lopec_restart;
357         ppc_md.power_off = lopec_power_off;
358         ppc_md.halt = lopec_halt;
359
360         ppc_md.setup_io_mappings = lopec_map_io;
361
362         ppc_md.time_init = todc_time_init;
363         ppc_md.set_rtc_time = todc_set_rtc_time;
364         ppc_md.get_rtc_time = todc_get_rtc_time;
365         ppc_md.calibrate_decr = todc_calibrate_decr;
366
367         ppc_md.nvram_read_val = todc_direct_read_val;
368         ppc_md.nvram_write_val = todc_direct_write_val;
369
370 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
371         ppc_ide_md.default_irq = lopec_ide_default_irq;
372         ppc_ide_md.default_io_base = lopec_ide_default_io_base;
373         ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
374 #endif
375 #ifdef CONFIG_SERIAL_TEXT_DEBUG
376         ppc_md.progress = lopec_progress;
377 #endif
378 }