arch/ppc/platforms/pmac_pic.c

   1 /*
   2  *  Support for the interrupt controllers found on Power Macintosh,
   3  *  currently Apple's "Grand Central" interrupt controller in all
   4  *  it's incarnations. OpenPIC support used on newer machines is
   5  *  in a separate file
   6  *
   7  *  Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
   8  *
   9  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  *
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/stddef.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/signal.h>
  23 #include <linux/pci.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/adb.h>
  27 #include <linux/pmu.h>
  28
  29 #include <asm/sections.h>
  30 #include <asm/io.h>
  31 #include <asm/smp.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/time.h>
  35 #include <asm/open_pic.h>
  36 #include <asm/xmon.h>
  37 #include <asm/pmac_feature.h>
  38
  39 #include "pmac_pic.h"
  40
  41 /*
  42  * XXX this should be in xmon.h, but putting it there means xmon.h
  43  * has to include <linux/interrupt.h> (to get irqreturn_t), which
  44  * causes all sorts of problems.  -- paulus
  45  */
  46 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
  47
  48 struct pmac_irq_hw {
  49         unsigned int    event;
  50         unsigned int    enable;
  51         unsigned int    ack;
  52         unsigned int    level;
  53 };
  54
  55 /* Default addresses */
  56 static volatile struct pmac_irq_hw *pmac_irq_hw[4] __pmacdata = {
  57         (struct pmac_irq_hw *) 0xf3000020,
  58         (struct pmac_irq_hw *) 0xf3000010,
  59         (struct pmac_irq_hw *) 0xf4000020,
  60         (struct pmac_irq_hw *) 0xf4000010,
  61 };
  62
  63 #define GC_LEVEL_MASK           0x3ff00000
  64 #define OHARE_LEVEL_MASK        0x1ff00000
  65 #define HEATHROW_LEVEL_MASK     0x1ff00000
  66
  67 static int max_irqs __pmacdata;
  68 static int max_real_irqs __pmacdata;
  69 static u32 level_mask[4] __pmacdata;
  70
  71 static spinlock_t pmac_pic_lock __pmacdata = SPIN_LOCK_UNLOCKED;
  72
  73
  74 #define GATWICK_IRQ_POOL_SIZE        10
  75 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE] __pmacdata;
  76
  77 /*
  78  * Mark an irq as "lost".  This is only used on the pmac
  79  * since it can lose interrupts (see pmac_set_irq_mask).
  80  * -- Cort
  81  */
  82 void __pmac
  83 __set_lost(unsigned long irq_nr, int nokick)
  84 {
  85         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  86                 atomic_inc(&ppc_n_lost_interrupts);
  87                 if (!nokick)
  88                         set_dec(1);
  89         }
  90 }
  91
  92 static void __pmac
  93 pmac_mask_and_ack_irq(unsigned int irq_nr)
  94 {
  95         unsigned long bit = 1UL << (irq_nr & 0x1f);
  96         int i = irq_nr >> 5;
  97         unsigned long flags;
  98
  99         if ((unsigned)irq_nr >= max_irqs)
 100                 return;
 101
 102         clear_bit(irq_nr, ppc_cached_irq_mask);
 103         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
 104                 atomic_dec(&ppc_n_lost_interrupts);
 105         spin_lock_irqsave(&pmac_pic_lock, flags);
 106         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 107         out_le32(&pmac_irq_hw[i]->ack, bit);
 108         do {
 109                 /* make sure ack gets to controller before we enable
 110                    interrupts */
 111                 mb();
 112         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 113                 != (ppc_cached_irq_mask[i] & bit));
 114         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 115 }
 116
 117 static void __pmac pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
 118 {
 119         unsigned long bit = 1UL << (irq_nr & 0x1f);
 120         int i = irq_nr >> 5;
 121         unsigned long flags;
 122
 123         if ((unsigned)irq_nr >= max_irqs)
 124                 return;
 125
 126         spin_lock_irqsave(&pmac_pic_lock, flags);
 127         /* enable unmasked interrupts */
 128         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 129
 130         do {
 131                 /* make sure mask gets to controller before we
 132                    return to user */
 133                 mb();
 134         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 135                 != (ppc_cached_irq_mask[i] & bit));
 136
 137         /*
 138          * Unfortunately, setting the bit in the enable register
 139          * when the device interrupt is already on *doesn't* set
 140          * the bit in the flag register or request another interrupt.
 141          */
 142         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 143                 __set_lost((ulong)irq_nr, nokicklost);
 144         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 145 }
 146
 147 static void __pmac pmac_mask_irq(unsigned int irq_nr)
 148 {
 149         clear_bit(irq_nr, ppc_cached_irq_mask);
 150         pmac_set_irq_mask(irq_nr, 0);
 151         mb();
 152 }
 153
 154 static void __pmac pmac_unmask_irq(unsigned int irq_nr)
 155 {
 156         set_bit(irq_nr, ppc_cached_irq_mask);
 157         pmac_set_irq_mask(irq_nr, 0);
 158 }
 159
 160 static void __pmac pmac_end_irq(unsigned int irq_nr)
 161 {
 162         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 163             && irq_desc[irq_nr].action) {
 164                 set_bit(irq_nr, ppc_cached_irq_mask);
 165                 pmac_set_irq_mask(irq_nr, 1);
 166         }
 167 }
 168
 169
 170 struct hw_interrupt_type pmac_pic = {
 171         " PMAC-PIC ",
 172         NULL,
 173         NULL,
 174         pmac_unmask_irq,
 175         pmac_mask_irq,
 176         pmac_mask_and_ack_irq,
 177         pmac_end_irq,
 178         NULL
 179 };
 180
 181 struct hw_interrupt_type gatwick_pic = {
 182         " GATWICK  ",
 183         NULL,
 184         NULL,
 185         pmac_unmask_irq,
 186         pmac_mask_irq,
 187         pmac_mask_and_ack_irq,
 188         pmac_end_irq,
 189         NULL
 190 };
 191
 192 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
 193 {
 194         int irq, bits;
 195
 196         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 197                 int i = irq >> 5;
 198                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 199                 /* We must read level interrupts from the level register */
 200                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 201                 bits &= ppc_cached_irq_mask[i];
 202                 if (bits == 0)
 203                         continue;
 204                 irq += __ilog2(bits);
 205                 ppc_irq_dispatch_handler(regs, irq);
 206                 return IRQ_HANDLED;
 207         }
 208         printk("gatwick irq not from gatwick pic\n");
 209         return IRQ_NONE;
 210 }
 211
 212 int
 213 pmac_get_irq(struct pt_regs *regs)
 214 {
 215         int irq;
 216         unsigned long bits = 0;
 217
 218 #ifdef CONFIG_SMP
 219         void psurge_smp_message_recv(struct pt_regs *);
 220
 221         /* IPI's are a hack on the powersurge -- Cort */
 222         if ( smp_processor_id() != 0 ) {
 223                 psurge_smp_message_recv(regs);
 224                 return -2;      /* ignore, already handled */
 225         }
 226 #endif /* CONFIG_SMP */
 227         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 228                 int i = irq >> 5;
 229                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 230                 /* We must read level interrupts from the level register */
 231                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 232                 bits &= ppc_cached_irq_mask[i];
 233                 if (bits == 0)
 234                         continue;
 235                 irq += __ilog2(bits);
 236                 break;
 237         }
 238
 239         return irq;
 240 }
 241
 242 /* This routine will fix some missing interrupt values in the device tree
 243  * on the gatwick mac-io controller used by some PowerBooks
 244  */
 245 static void __init
 246 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
 247 {
 248         struct device_node *node;
 249         int count;
 250
 251         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
 252         node = gw->child;
 253         count = 0;
 254         while(node)
 255         {
 256                 /* Fix SCC */
 257                 if (strcasecmp(node->name, "escc") == 0)
 258                         if (node->child) {
 259                                 if (node->child->n_intrs < 3) {
 260                                         node->child->intrs = &gatwick_int_pool[count];
 261                                         count += 3;
 262                                 }
 263                                 node->child->n_intrs = 3;
 264                                 node->child->intrs[0].line = 15+irq_base;
 265                                 node->child->intrs[1].line =  4+irq_base;
 266                                 node->child->intrs[2].line =  5+irq_base;
 267                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
 268                                         node->child->intrs[0].line,
 269                                         node->child->intrs[1].line,
 270                                         node->child->intrs[2].line);
 271                         }
 272                 /* Fix media-bay & left SWIM */
 273                 if (strcasecmp(node->name, "media-bay") == 0) {
 274                         struct device_node* ya_node;
 275
 276                         if (node->n_intrs == 0)
 277                                 node->intrs = &gatwick_int_pool[count++];
 278                         node->n_intrs = 1;
 279                         node->intrs[0].line = 29+irq_base;
 280                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
 281                                         node->intrs[0].line);
 282
 283                         ya_node = node->child;
 284                         while(ya_node)
 285                         {
 286                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
 287                                         if (ya_node->n_intrs < 2) {
 288                                                 ya_node->intrs = &gatwick_int_pool[count];
 289                                                 count += 2;
 290                                         }
 291                                         ya_node->n_intrs = 2;
 292                                         ya_node->intrs[0].line = 19+irq_base;
 293                                         ya_node->intrs[1].line =  1+irq_base;
 294                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
 295                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 296                                 }
 297                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
 298                                         if (ya_node->n_intrs < 2) {
 299                                                 ya_node->intrs = &gatwick_int_pool[count];
 300                                                 count += 2;
 301                                         }
 302                                         ya_node->n_intrs = 2;
 303                                         ya_node->intrs[0].line = 14+irq_base;
 304                                         ya_node->intrs[1].line =  3+irq_base;
 305                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
 306                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 307                                 }
 308                                 ya_node = ya_node->sibling;
 309                         }
 310                 }
 311                 node = node->sibling;
 312         }
 313         if (count > 10) {
 314                 printk("WARNING !! Gatwick interrupt pool overflow\n");
 315                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
 316                 printk("              requested = %d\n", count);
 317         }
 318 }
 319
 320 /*
 321  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
 322  * card which includes an ohare chip that acts as a second interrupt
 323  * controller.  If we find this second ohare, set it up and fix the
 324  * interrupt value in the device tree for the ethernet chip.
 325  */
 326 static int __init enable_second_ohare(void)
 327 {
 328         unsigned char bus, devfn;
 329         unsigned short cmd;
 330         unsigned long addr;
 331         struct device_node *irqctrler = find_devices("pci106b,7");
 332         struct device_node *ether;
 333
 334         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
 335                 return -1;
 336         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
 337         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
 338         max_irqs = 64;
 339         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
 340                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
 341                 if (!hose)
 342                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
 343                 else {
 344                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
 345                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 346                     cmd &= ~PCI_COMMAND_IO;
 347                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
 348                 }
 349         }
 350
 351         /* Fix interrupt for the modem/ethernet combo controller. The number
 352            in the device tree (27) is bogus (correct for the ethernet-only
 353            board but not the combo ethernet/modem board).
 354            The real interrupt is 28 on the second controller -> 28+32 = 60.
 355         */
 356         ether = find_devices("pci1011,14");
 357         if (ether && ether->n_intrs > 0) {
 358                 ether->intrs[0].line = 60;
 359                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
 360                        ether->intrs[0].line);
 361         }
 362
 363         /* Return the interrupt number of the cascade */
 364         return irqctrler->intrs[0].line;
 365 }
 366
 367 #ifdef CONFIG_POWER4
 368 static irqreturn_t k2u3_action(int cpl, void *dev_id, struct pt_regs *regs)
 369 {
 370         int irq;
 371
 372         irq = openpic2_get_irq(regs);
 373         if (irq != -1)
 374                 ppc_irq_dispatch_handler(regs, irq);
 375         return IRQ_HANDLED;
 376 }
 377 #endif /* CONFIG_POWER4 */
 378
 379 void __init pmac_pic_init(void)
 380 {
 381         int i;
 382         struct device_node *irqctrler  = NULL;
 383         struct device_node *irqctrler2 = NULL;
 384         struct device_node *np;
 385         unsigned long addr;
 386         int irq_cascade = -1;
 387
 388         /* We first try to detect Apple's new Core99 chipset, since mac-io
 389          * is quite different on those machines and contains an IBM MPIC2.
 390          */
 391         np = find_type_devices("open-pic");
 392         while(np) {
 393                 if (np->parent && !strcmp(np->parent->name, "u3"))
 394                         irqctrler2 = np;
 395                 else
 396                         irqctrler = np;
 397                 np = np->next;
 398         }
 399         if (irqctrler != NULL)
 400         {
 401                 if (irqctrler->n_addrs > 0)
 402                 {
 403                         unsigned char senses[128];
 404
 405                         printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
 406                                irqctrler->addrs[0].address);
 407
 408                         prom_get_irq_senses(senses, 0, 128);
 409                         OpenPIC_InitSenses = senses;
 410                         OpenPIC_NumInitSenses = 128;
 411                         ppc_md.get_irq = openpic_get_irq;
 412                         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
 413                         OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
 414                                                irqctrler->addrs[0].size);
 415                         openpic_init(0);
 416
 417 #ifdef CONFIG_POWER4
 418                         if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
 419                             irqctrler2->n_addrs > 0) {
 420                                 printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
 421                                        irqctrler2->addrs[0].address,
 422                                        irqctrler2->intrs[0].line);
 423                                 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
 424                                 OpenPIC2_Addr = ioremap(irqctrler2->addrs[0].address,
 425                                                         irqctrler2->addrs[0].size);
 426                                 prom_get_irq_senses(senses, PMAC_OPENPIC2_OFFSET,
 427                                                     PMAC_OPENPIC2_OFFSET+128);
 428                                 OpenPIC_InitSenses = senses;
 429                                 OpenPIC_NumInitSenses = 128;
 430                                 openpic2_init(PMAC_OPENPIC2_OFFSET);
 431                                 if (request_irq(irqctrler2->intrs[0].line, k2u3_action, 0,
 432                                                 "U3->K2 Cascade", NULL))
 433                                         printk("Unable to get OpenPIC IRQ for cascade\n");
 434                         }
 435 #endif /* CONFIG_POWER4 */
 436
 437 #ifdef CONFIG_XMON
 438                         {
 439                                 struct device_node* pswitch;
 440                                 int nmi_irq;
 441
 442                                 pswitch = find_devices("programmer-switch");
 443                                 if (pswitch && pswitch->n_intrs) {
 444                                         nmi_irq = pswitch->intrs[0].line;
 445                                         openpic_init_nmi_irq(nmi_irq);
 446                                         request_irq(nmi_irq, xmon_irq, 0,
 447                                                     "NMI - XMON", 0);
 448                                 }
 449                         }
 450 #endif  /* CONFIG_XMON */
 451                         return;
 452                 }
 453                 irqctrler = NULL;
 454         }
 455
 456         /* Get the level/edge settings, assume if it's not
 457          * a Grand Central nor an OHare, then it's an Heathrow
 458          * (or Paddington).
 459          */
 460         if (find_devices("gc"))
 461                 level_mask[0] = GC_LEVEL_MASK;
 462         else if (find_devices("ohare")) {
 463                 level_mask[0] = OHARE_LEVEL_MASK;
 464                 /* We might have a second cascaded ohare */
 465                 level_mask[1] = OHARE_LEVEL_MASK;
 466         } else {
 467                 level_mask[0] = HEATHROW_LEVEL_MASK;
 468                 level_mask[1] = 0;
 469                 /* We might have a second cascaded heathrow */
 470                 level_mask[2] = HEATHROW_LEVEL_MASK;
 471                 level_mask[3] = 0;
 472         }
 473
 474         /*
 475          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
 476          * 1998 G3 Series PowerBooks have 128,
 477          * other powermacs have 32.
 478          * The combo ethernet/modem card for the Powerstar powerbooks
 479          * (2400/3400/3500, ohare based) has a second ohare chip
 480          * effectively making a total of 64.
 481          */
 482         max_irqs = max_real_irqs = 32;
 483         irqctrler = find_devices("mac-io");
 484         if (irqctrler)
 485         {
 486                 max_real_irqs = 64;
 487                 if (irqctrler->next)
 488                         max_irqs = 128;
 489                 else
 490                         max_irqs = 64;
 491         }
 492         for ( i = 0; i < max_real_irqs ; i++ )
 493                 irq_desc[i].handler = &pmac_pic;
 494
 495         /* get addresses of first controller */
 496         if (irqctrler) {
 497                 if  (irqctrler->n_addrs > 0) {
 498                         addr = (unsigned long)
 499                                 ioremap(irqctrler->addrs[0].address, 0x40);
 500                         for (i = 0; i < 2; ++i)
 501                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 502                                         (addr + (2 - i) * 0x10);
 503                 }
 504
 505                 /* get addresses of second controller */
 506                 irqctrler = irqctrler->next;
 507                 if (irqctrler && irqctrler->n_addrs > 0) {
 508                         addr = (unsigned long)
 509                                 ioremap(irqctrler->addrs[0].address, 0x40);
 510                         for (i = 2; i < 4; ++i)
 511                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 512                                         (addr + (4 - i) * 0x10);
 513                         irq_cascade = irqctrler->intrs[0].line;
 514                         if (device_is_compatible(irqctrler, "gatwick"))
 515                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
 516                 }
 517         } else {
 518                 /* older powermacs have a GC (grand central) or ohare at
 519                    f3000000, with interrupt control registers at f3000020. */
 520                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
 521                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
 522         }
 523
 524         /* PowerBooks 3400 and 3500 can have a second controller in a second
 525            ohare chip, on the combo ethernet/modem card */
 526         if (machine_is_compatible("AAPL,3400/2400")
 527              || machine_is_compatible("AAPL,3500"))
 528                 irq_cascade = enable_second_ohare();
 529
 530         /* disable all interrupts in all controllers */
 531         for (i = 0; i * 32 < max_irqs; ++i)
 532                 out_le32(&pmac_irq_hw[i]->enable, 0);
 533         /* mark level interrupts */
 534         for (i = 0; i < max_irqs; i++)
 535                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
 536                         irq_desc[i].status = IRQ_LEVEL;
 537
 538         /* get interrupt line of secondary interrupt controller */
 539         if (irq_cascade >= 0) {
 540                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
 541                         (int)irq_cascade);
 542                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
 543                         irq_desc[i].handler = &gatwick_pic;
 544                 request_irq( irq_cascade, gatwick_action, SA_INTERRUPT,
 545                              "cascade", 0 );
 546         }
 547         printk("System has %d possible interrupts\n", max_irqs);
 548         if (max_irqs != max_real_irqs)
 549                 printk(KERN_DEBUG "%d interrupts on main controller\n",
 550                         max_real_irqs);
 551
 552 #ifdef CONFIG_XMON
 553         request_irq(20, xmon_irq, 0, "NMI - XMON", 0);
 554 #endif  /* CONFIG_XMON */
 555 }
 556
 557 #ifdef CONFIG_PM
 558 /*
 559  * These procedures are used in implementing sleep on the powerbooks.
 560  * sleep_save_intrs() saves the states of all interrupt enables
 561  * and disables all interrupts except for the nominated one.
 562  * sleep_restore_intrs() restores the states of all interrupt enables.
 563  */
 564 unsigned long sleep_save_mask[2];
 565
 566 /* This used to be passed by the PMU driver but that link got
 567  * broken with the new driver model. We use this tweak for now...
 568  */
 569 static int pmacpic_find_viaint(void)
 570 {
 571         int viaint = -1;
 572
 573 #ifdef CONFIG_ADB_PMU
 574         struct device_node *np;
 575
 576         if (pmu_get_model() != PMU_OHARE_BASED)
 577                 goto not_found;
 578         np = of_find_node_by_name(NULL, "via-pmu");
 579         if (np == NULL)
 580                 goto not_found;
 581         viaint = np->intrs[0].line;
 582 #endif /* CONFIG_ADB_PMU */
 583
 584 not_found:
 585         return viaint;
 586 }
 587
 588 static int pmacpic_suspend(struct sys_device *sysdev, u32 state)
 589 {
 590         int viaint = pmacpic_find_viaint();
 591
 592         sleep_save_mask[0] = ppc_cached_irq_mask[0];
 593         sleep_save_mask[1] = ppc_cached_irq_mask[1];
 594         ppc_cached_irq_mask[0] = 0;
 595         ppc_cached_irq_mask[1] = 0;
 596         if (viaint > 0)
 597                 set_bit(viaint, ppc_cached_irq_mask);
 598         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 599         if (max_real_irqs > 32)
 600                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 601         (void)in_le32(&pmac_irq_hw[0]->event);
 602         /* make sure mask gets to controller before we return to caller */
 603         mb();
 604         (void)in_le32(&pmac_irq_hw[0]->enable);
 605
 606         return 0;
 607 }
 608
 609 static int pmacpic_resume(struct sys_device *sysdev)
 610 {
 611         int i;
 612
 613         out_le32(&pmac_irq_hw[0]->enable, 0);
 614         if (max_real_irqs > 32)
 615                 out_le32(&pmac_irq_hw[1]->enable, 0);
 616         mb();
 617         for (i = 0; i < max_real_irqs; ++i)
 618                 if (test_bit(i, sleep_save_mask))
 619                         pmac_unmask_irq(i);
 620
 621         return 0;
 622 }
 623
 624 #endif /* CONFIG_PM */
 625
 626 static struct sysdev_class pmacpic_sysclass = {
 627         set_kset_name("pmac_pic"),
 628 };
 629
 630 static struct sys_device device_pmacpic = {
 631         .id             = 0,
 632         .cls            = &pmacpic_sysclass,
 633 };
 634
 635 static struct sysdev_driver driver_pmacpic = {
 636 #ifdef CONFIG_PM
 637         .suspend        = &pmacpic_suspend,
 638         .resume         = &pmacpic_resume,
 639 #endif /* CONFIG_PM */
 640 };
 641
 642 static int __init init_pmacpic_sysfs(void)
 643 {
 644         if (max_irqs == 0)
 645                 return -ENODEV;
 646
 647         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
 648         sysdev_class_register(&pmacpic_sysclass);
 649         sysdev_register(&device_pmacpic);
 650         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
 651         return 0;
 652 }
 653
 654 subsys_initcall(init_pmacpic_sysfs);
 655