arch/ppc/platforms/sbc82xx.c

   1 /*
   2  * arch/ppc/platforms/sbc82xx.c
   3  *
   4  * SBC82XX platform support
   5  *
   6  * Author: Guy Streeter <streeter@redhat.com>
   7  *
   8  * Derived from: est8260_setup.c by Allen Curtis, ONZ
   9  *
  10  * Copyright 2004 Red Hat, Inc.
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/stddef.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23
  24 #include <asm/mpc8260.h>
  25 #include <asm/machdep.h>
  26 #include <asm/io.h>
  27 #include <asm/todc.h>
  28 #include <asm/immap_cpm2.h>
  29 #include <asm/pci.h>
  30
  31 static void (*callback_setup_arch)(void);
  32 static void (*callback_init_IRQ)(void);
  33
  34 extern unsigned char __res[sizeof(bd_t)];
  35
  36 extern void m8260_init(unsigned long r3, unsigned long r4,
  37         unsigned long r5, unsigned long r6, unsigned long r7);
  38
  39 extern void (*late_time_init)(void);
  40
  41 static int
  42 sbc82xx_show_cpuinfo(struct seq_file *m)
  43 {
  44         bd_t    *binfo = (bd_t *)__res;
  45
  46         seq_printf(m, "vendor\t\t: Wind River\n"
  47                       "machine\t\t: SBC PowerQUICC II\n"
  48                       "\n"
  49                       "mem size\t\t: 0x%08lx\n"
  50                       "console baud\t\t: %ld\n"
  51                       "\n",
  52                       binfo->bi_memsize,
  53                       binfo->bi_baudrate);
  54         return 0;
  55 }
  56
  57 static void __init
  58 sbc82xx_setup_arch(void)
  59 {
  60         printk("SBC PowerQUICC II Port\n");
  61         callback_setup_arch();
  62 }
  63
  64 #ifdef CONFIG_GEN_RTC
  65 TODC_ALLOC();
  66
  67 /*
  68  * Timer init happens before mem_init but after paging init, so we cannot
  69  * directly use ioremap() at that time.
  70  * late_time_init() is call after paging init.
  71  */
  72
  73 static void sbc82xx_time_init(void)
  74 {
  75         volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
  76
  77         /* Set up CS11 for RTC chip */
  78         mc->memc_br11=0;
  79         mc->memc_or11=0xffff0836;
  80         mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
  81
  82         TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
  83
  84         todc_info->nvram_data =
  85                 (unsigned int)ioremap(todc_info->nvram_data, 0x2000);
  86         BUG_ON(!todc_info->nvram_data);
  87         ppc_md.get_rtc_time     = todc_get_rtc_time;
  88         ppc_md.set_rtc_time     = todc_set_rtc_time;
  89         ppc_md.nvram_read_val   = todc_direct_read_val;
  90         ppc_md.nvram_write_val  = todc_direct_write_val;
  91         todc_time_init();
  92 }
  93 #endif /* CONFIG_GEN_RTC */
  94
  95 static volatile char *sbc82xx_i8259_map;
  96 static char sbc82xx_i8259_mask = 0xff;
  97 static spinlock_t sbc82xx_i8259_lock = SPIN_LOCK_UNLOCKED;
  98
  99 static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
 100 {
 101         unsigned long flags;
 102
 103         irq_nr -= NR_SIU_INTS;
 104
 105         spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
 106         sbc82xx_i8259_mask |= 1 << irq_nr;
 107         (void) sbc82xx_i8259_map[1];    /* Dummy read */
 108         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
 109         sbc82xx_i8259_map[0] = 0x20;    /* OCW2: Non-specific EOI */
 110         spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
 111 }
 112
 113 static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
 114 {
 115         unsigned long flags;
 116
 117         irq_nr -= NR_SIU_INTS;
 118
 119         spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
 120         sbc82xx_i8259_mask |= 1 << irq_nr;
 121         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
 122         spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
 123 }
 124
 125 static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
 126 {
 127         unsigned long flags;
 128
 129         irq_nr -= NR_SIU_INTS;
 130
 131         spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
 132         sbc82xx_i8259_mask &= ~(1 << irq_nr);
 133         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
 134         spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
 135 }
 136
 137 static void sbc82xx_i8259_end_irq(unsigned int irq)
 138 {
 139         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 140             && irq_desc[irq].action)
 141                 sbc82xx_i8259_unmask_irq(irq);
 142 }
 143
 144
 145 struct hw_interrupt_type sbc82xx_i8259_ic = {
 146         .typename = " i8259     ",
 147         .enable = sbc82xx_i8259_unmask_irq,
 148         .disable = sbc82xx_i8259_mask_irq,
 149         .ack = sbc82xx_i8259_mask_and_ack_irq,
 150         .end = sbc82xx_i8259_end_irq,
 151 };
 152
 153 static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id, struct pt_regs *regs)
 154 {
 155         spin_lock(&sbc82xx_i8259_lock);
 156
 157         sbc82xx_i8259_map[0] = 0x0c;    /* OCW3: Read IR register on RD# pulse */
 158         irq = sbc82xx_i8259_map[0] & 7; /* Read IRR */
 159
 160         if (irq == 7) {
 161                 /* Possible spurious interrupt */
 162                 int isr;
 163                 sbc82xx_i8259_map[0] = 0x0b;    /* OCW3: Read IS register on RD# pulse */
 164                 isr = sbc82xx_i8259_map[0];     /* Read ISR */
 165
 166                 if (!(isr & 0x80)) {
 167                         printk(KERN_INFO "Spurious i8259 interrupt\n");
 168                         return IRQ_HANDLED;
 169                 }
 170         }
 171         ppc_irq_dispatch_handler(regs, NR_SIU_INTS + irq);
 172         return IRQ_HANDLED;
 173 }
 174
 175 void __init sbc82xx_init_IRQ(void)
 176 {
 177         volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
 178         volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
 179         int i;
 180
 181         callback_init_IRQ();
 182
 183         /* u-boot doesn't always set the board up correctly */
 184         mc->memc_br5 = 0;
 185         mc->memc_or5 = 0xfff00856;
 186         mc->memc_br5 = 0x22000801;
 187
 188         sbc82xx_i8259_map = ioremap(0x22008000, 2);
 189         if (!sbc82xx_i8259_map) {
 190                 printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
 191                 return;
 192         }
 193
 194         /* Set up the interrupt handlers for the i8259 IRQs */
 195         for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
 196                 irq_desc[i].handler = &sbc82xx_i8259_ic;
 197                 irq_desc[i].status |= IRQ_LEVEL;
 198         }
 199
 200         /* make IRQ6 level sensitive */
 201         ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
 202         irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
 203
 204         /* Initialise the i8259 */
 205         sbc82xx_i8259_map[0] = 0x1b;    /* ICW1: Level, no cascade, ICW4 */
 206         sbc82xx_i8259_map[1] = 0x00;    /* ICW2: vector base */
 207                                         /* No ICW3 (no cascade) */
 208         sbc82xx_i8259_map[1] = 0x01;    /* ICW4: 8086 mode, normal EOI */
 209
 210         sbc82xx_i8259_map[0] = 0x0b;    /* OCW3: Read IS register on RD# pulse */
 211
 212         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
 213
 214         /* Request cascade IRQ */
 215         if (request_irq(SIU_INT_IRQ6, sbc82xx_i8259_demux, SA_INTERRUPT,
 216                         "i8259 demux", 0)) {
 217                 printk("Installation of i8259 IRQ demultiplexer failed.\n");
 218         }
 219 }
 220
 221 static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
 222                                unsigned char pin)
 223 {
 224         static char pci_irq_table[][4] = {
 225                 /*
 226                  * PCI IDSEL/INTPIN->INTLINE
 227                  *  A      B      C      D
 228                  */
 229                 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 16 - PMC slot */
 230                 { SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1,  -1  },                 /* IDSEL 17 - CardBus */
 231                 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
 232         };
 233
 234         const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
 235
 236         return PCI_IRQ_TABLE_LOOKUP;
 237 }
 238
 239
 240
 241 void __init
 242 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 243               unsigned long r6, unsigned long r7)
 244 {
 245         /* Generic 8260 platform initialization */
 246         m8260_init(r3, r4, r5, r6, r7);
 247
 248         /* u-boot may be using one of the FCC Ethernet devices.
 249            Use the MAC address to the SCC. */
 250         __res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
 251
 252         /* Anything special for this platform */
 253         ppc_md.show_cpuinfo     = sbc82xx_show_cpuinfo;
 254
 255         callback_setup_arch     = ppc_md.setup_arch;
 256         callback_init_IRQ       = ppc_md.init_IRQ;
 257
 258         ppc_md.setup_arch       = sbc82xx_setup_arch;
 259         ppc_md.init_IRQ         = sbc82xx_init_IRQ;
 260         ppc_md.pci_map_irq      = sbc82xx_pci_map_irq;
 261 #ifdef CONFIG_GEN_RTC
 262         ppc_md.time_init        = NULL;
 263         ppc_md.get_rtc_time     = NULL;
 264         ppc_md.set_rtc_time     = NULL;
 265         ppc_md.nvram_read_val   = NULL;
 266         ppc_md.nvram_write_val  = NULL;
 267         late_time_init          = sbc82xx_time_init;
 268 #endif /* CONFIG_GEN_RTC */
 269 }