arch/ppc/syslib/gt64260_common.c

   1 /*
   2  * arch/ppc/syslib/gt64260_common.c
   3  *
   4  * Common routines for the Marvell/Galileo GT64260 (Discovery) host bridge,
   5  * interrupt controller, memory controller, serial controller, enet controller,
   6  * etc.
   7  *
   8  * Author: Mark A. Greer <mgreer@mvista.com>
   9  *
  10  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 /*
  17  * The GT64260 port is the result of hard work from many people from
  18  * many companies.  In particular, employees of Marvell/Galileo, Mission
  19  * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
  20  */
  21
  22 /*
  23  * At last count, the 64260-B-0 has 65 errata and 24 restrictions.  The odds of
  24  * you getting it to work well, under stress, for a long period of time are
  25  * low.  If nothing else, you will likely run into an interrupt controller
  26  * bug.
  27  *
  28  * The newer 64260A-B-0 is much improved but has its own problems.
  29  * Dave Wilhardt <dwilhardt@zyterra.com> has discovered that you must set
  30  * up your PCI snoop regions to be prefetchable with 4-word bursts AND set the
  31  * "Memory Write and Invalidate bit" (bit 4) in the cmd reg of each PCI device
  32  * before coherency works between PCI and other devices.  Many thanks to Dave.
  33  *
  34  * So far this code has been tested on Marvell/Galileo EV-64260-BP and
  35  * an EV-64260A-BP uni-processor boards with 750 and 7400 processors.
  36  * It has not yet been tested with a 7410 or 7450, or on an smp system.
  37  *
  38  * Note: I have not had any luck moving the base register address of the bridge
  39  *       with the gt64260_set_base() routine.  I move it in the bootloader
  40  *       before starting the kernel.  I haven't really looked into it so it
  41  *       may be an easy fix. -- MAG
  42  */
  43 #include <linux/kernel.h>
  44 #include <linux/init.h>
  45 #include <linux/pci.h>
  46 #include <linux/slab.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/uaccess.h>
  52 #include <asm/machdep.h>
  53 #include <asm/pci-bridge.h>
  54 #include <asm/gt64260.h>
  55 #include <asm/delay.h>
  56
  57
  58 u32     gt64260_base; /* Virtual base address of 64260's regs */
  59 u32     gt64260_revision; /* Revision of the chip */
  60 u8      gt64260_pci_exclude_bridge = TRUE;
  61
  62
  63 /*
  64  *****************************************************************************
  65  *
  66  *      Bridge Initialization Routines
  67  *
  68  *****************************************************************************
  69  */
  70 static void gt64260_check_errata(struct pci_controller *hose_a,
  71                                  struct pci_controller *hose_b);
  72
  73 /*
  74  * Typical '_find_bridges()' routine for boards with a GT64260 bridge.
  75  */
  76 int __init
  77 gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
  78         int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)))
  79 {
  80         struct pci_controller           *hose_a, *hose_b;
  81         u32                             io_base_a, io_base_b;
  82         int                             rc;
  83
  84
  85         gt64260_base = (u32)ioremap(phys_base_addr,GT64260_INTERNAL_SPACE_SIZE);
  86
  87         hose_a = pcibios_alloc_controller();
  88         if (!hose_a)
  89                 return -1;
  90
  91         hose_b = pcibios_alloc_controller();
  92         if (!hose_b)
  93                 return -1;
  94
  95         info->hose_a = hose_a;
  96         info->hose_b = hose_b;
  97
  98         /* Ends up mapping PCI Config addr/data pairs twice */
  99         setup_indirect_pci(hose_a,
 100                            phys_base_addr + GT64260_PCI_0_CONFIG_ADDR,
 101                            phys_base_addr + GT64260_PCI_0_CONFIG_DATA);
 102
 103         setup_indirect_pci(hose_b,
 104                            phys_base_addr + GT64260_PCI_1_CONFIG_ADDR,
 105                            phys_base_addr + GT64260_PCI_1_CONFIG_DATA);
 106
 107         if ((rc = gt64260_bridge_init(info)) != 0) {
 108                 iounmap((void *)hose_a->cfg_addr);
 109                 iounmap((void *)hose_a->cfg_data);
 110                 iounmap((void *)hose_b->cfg_addr);
 111                 iounmap((void *)hose_b->cfg_data);
 112                 iounmap((void *)gt64260_base);
 113                 return rc;
 114         }
 115
 116         /* ioremap PCI I/O regions */
 117         io_base_b = (u32)ioremap(info->pci_1_io_start_proc,info->pci_1_io_size);
 118         io_base_a = (u32)ioremap(info->pci_0_io_start_proc,info->pci_0_io_size);
 119         isa_io_base = io_base_a;
 120
 121         hose_a->first_busno = 0;
 122         hose_a->last_busno  = 0xff;
 123
 124         pci_init_resource(&hose_a->io_resource,
 125                           0,    /* really: io_base_a - isa_io_base */
 126                           info->pci_0_io_size - 1,
 127                           IORESOURCE_IO,
 128                           "host bridge PCI bus 0");
 129         hose_a->io_space.start = info->pci_0_io_start_pci;
 130         hose_a->io_space.end   = info->pci_0_io_start_pci +
 131                                         info->pci_0_io_size - 1;
 132         hose_a->io_base_virt = (void *)isa_io_base;
 133
 134         pci_init_resource(&hose_a->mem_resources[0],
 135                           info->pci_0_mem_start_proc,
 136                           info->pci_0_mem_start_proc + info->pci_0_mem_size - 1,
 137                           IORESOURCE_MEM,
 138                           "host bridge PCI bus 0");
 139         hose_a->mem_space.start = info->pci_0_mem_start_pci_lo;
 140         hose_a->mem_space.end   = info->pci_0_mem_start_pci_lo +
 141                                         info->pci_0_mem_size - 1;
 142         hose_a->pci_mem_offset = (info->pci_0_mem_start_proc -
 143                                         info->pci_0_mem_start_pci_lo);
 144
 145         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 146
 147
 148         hose_b->first_busno = hose_a->last_busno + 1;
 149         hose_b->bus_offset  = hose_b->first_busno;
 150         hose_b->last_busno  = 0xff;
 151
 152         pci_init_resource(&hose_b->io_resource,
 153                           io_base_b - isa_io_base,
 154                           io_base_b - isa_io_base + info->pci_1_io_size - 1,
 155                           IORESOURCE_IO,
 156                           "host bridge PCI bus 1");
 157         hose_b->io_space.start = info->pci_1_io_start_pci;
 158         hose_b->io_space.end   = info->pci_1_io_start_pci +
 159                                         info->pci_1_io_size - 1;
 160         hose_b->io_base_virt = (void *)isa_io_base;
 161
 162         pci_init_resource(&hose_b->mem_resources[0],
 163                           info->pci_1_mem_start_proc,
 164                           info->pci_1_mem_start_proc + info->pci_1_mem_size - 1,
 165                           IORESOURCE_MEM,
 166                           "host bridge PCI bus 1");
 167         hose_b->mem_space.start = info->pci_1_mem_start_pci_lo;
 168         hose_b->mem_space.end   = info->pci_1_mem_start_pci_lo +
 169                                         info->pci_1_mem_size - 1;
 170         hose_b->pci_mem_offset = (info->pci_1_mem_start_proc -
 171                                         info->pci_1_mem_start_pci_lo);
 172
 173         hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
 174
 175
 176         ppc_md.pci_exclude_device = gt64260_pci_exclude_device;
 177         ppc_md.pci_swizzle        = common_swizzle;
 178         ppc_md.pci_map_irq        = map_irq;
 179
 180         return 0;
 181 } /* gt64260_find_bridges() */
 182
 183 /*
 184  * gt64260_bridge_init()
 185  *
 186  * Perform bridge initialization for a "typical" setup for a PPC system.
 187  */
 188 int __init
 189 gt64260_bridge_init(gt64260_bridge_info_t *info)
 190 {
 191         int     window;
 192         u16     u16_val;
 193         u32     u32_val;
 194         int     rc = 0;
 195         u8      save_exclude;
 196
 197         /*
 198          * Count on firmware to set/clear other bits in this register.
 199          *
 200          * Set CPU CONFIG Reg bit:
 201          *      bit 13 - Pipeline
 202          *      bit 16 - RdOOO
 203          *
 204          * Clear CPU Config Reg bit:
 205          *      bit 12 - endianess
 206          *      bit 27 - RemapWrDis
 207          */
 208         u32_val = gt_read(GT64260_CPU_CONFIG);
 209         u32_val |= ((1<<13) | (1<<16));
 210         u32_val &= ~((1<<8) | (1<<12) | (1<<27));
 211         gt_write(GT64260_CPU_CONFIG, u32_val);
 212
 213         /* PCI 0/1 Timeout and Retry limits */
 214         u32_val = gt_read(GT64260_PCI_0_TO_RETRY);
 215         u32_val |= 0x0000ffff;
 216         gt_write(GT64260_PCI_0_TO_RETRY, u32_val);
 217
 218         u32_val = gt_read(GT64260_PCI_1_TO_RETRY);
 219         u32_val |= 0x0000ffff;
 220         gt_write(GT64260_PCI_1_TO_RETRY, u32_val);
 221
 222         save_exclude = gt64260_pci_exclude_bridge;
 223         gt64260_pci_exclude_bridge = FALSE;
 224
 225         /* Set class code to indicate host bridge */
 226         early_read_config_dword(info->hose_a,
 227                                 info->hose_a->first_busno,
 228                                 PCI_DEVFN(0,0),
 229                                 PCI_CLASS_REVISION,
 230                                 &u32_val);
 231         u32_val &= 0x000000ff;
 232         gt64260_revision = u32_val;     /* a 64260 or 64260A? */
 233         u32_val |= (PCI_CLASS_BRIDGE_HOST << 16);
 234         early_write_config_dword(info->hose_a,
 235                                  info->hose_a->first_busno,
 236                                  PCI_DEVFN(0,0),
 237                                  PCI_CLASS_REVISION,
 238                                  u32_val);
 239
 240         early_read_config_dword(info->hose_b,
 241                                 info->hose_b->first_busno,
 242                                 PCI_DEVFN(0,0),
 243                                 PCI_CLASS_REVISION,
 244                                 &u32_val);
 245         u32_val &= 0x000000ff;
 246         u32_val |= (PCI_CLASS_BRIDGE_HOST << 16);
 247         early_write_config_dword(info->hose_b,
 248                                  info->hose_b->first_busno,
 249                                  PCI_DEVFN(0,0),
 250                                  PCI_CLASS_REVISION,
 251                                  u32_val);
 252
 253         /* Enable 64260 to be PCI master & respond to PCI MEM cycles */
 254         early_read_config_word(info->hose_a,
 255                                info->hose_a->first_busno,
 256                                PCI_DEVFN(0,0),
 257                                PCI_COMMAND,
 258                                &u16_val);
 259         u16_val |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 260         early_write_config_word(info->hose_a,
 261                                 info->hose_a->first_busno,
 262                                 PCI_DEVFN(0,0),
 263                                 PCI_COMMAND,
 264                                 u16_val);
 265
 266         early_read_config_word(info->hose_b,
 267                                info->hose_b->first_busno,
 268                                PCI_DEVFN(0,0),
 269                                PCI_COMMAND,
 270                                &u16_val);
 271         u16_val |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 272         early_write_config_word(info->hose_b,
 273                                 info->hose_b->first_busno,
 274                                 PCI_DEVFN(0,0),
 275                                 PCI_COMMAND,
 276                                 u16_val);
 277
 278         gt64260_pci_exclude_bridge = save_exclude;
 279
 280         /*
 281          * Disable all CPU windows on the bridge except for SCS 0 which
 282          * is covering all of system memory.:
 283          */
 284         gt64260_cpu_disable_all_windows();
 285
 286         /*
 287          * Set CPU snoop window to indicate all of system memory
 288          * is covered with wirte-back cache.
 289          */
 290         gt64260_cpu_snoop_set_window(0,
 291                                      0x00000000,
 292                                      info->mem_size,
 293                                      GT64260_CPU_SNOOP_WB);
 294
 295         /*
 296          * Set up CPU->PCI mappings (so CPU can get at PCI dev regs/mem).
 297          * Will only use one of the four CPU->PCI MEM windows on each bus.
 298          */
 299         gt64260_cpu_set_pci_io_window(0,
 300                                       info->pci_0_io_start_proc,
 301                                       info->pci_0_io_start_pci,
 302                                       info->pci_0_io_size,
 303                                       info->pci_0_io_swap);
 304
 305         gt64260_cpu_set_pci_mem_window(0,
 306                                        0,
 307                                        info->pci_0_mem_start_proc,
 308                                        info->pci_0_mem_start_pci_hi,
 309                                        info->pci_0_mem_start_pci_lo,
 310                                        info->pci_0_mem_size,
 311                                        info->pci_0_mem_swap);
 312
 313         gt64260_cpu_set_pci_io_window(1,
 314                                       info->pci_1_io_start_proc,
 315                                       info->pci_1_io_start_pci,
 316                                       info->pci_1_io_size,
 317                                       info->pci_1_io_swap);
 318
 319         gt64260_cpu_set_pci_mem_window(1,
 320                                        0,
 321                                        info->pci_1_mem_start_proc,
 322                                        info->pci_1_mem_start_pci_hi,
 323                                        info->pci_1_mem_start_pci_lo,
 324                                        info->pci_1_mem_size,
 325                                        info->pci_1_mem_swap);
 326
 327         /*
 328          * Set up PCI MEM->system memory mapping (bridge slave PCI window).
 329          *
 330          * Set BAR enables to allow only the SCS0 slave window to respond
 331          * to PCI read/write cycles.
 332          */
 333         gt64260_pci_bar_enable(0, GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0);
 334         gt64260_pci_bar_enable(1, GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0);
 335
 336         /*
 337          * For virt_to_bus & bus_to_virt to work correctly, this mapping
 338          * must be the same on both PCI buses.
 339          */
 340         gt64260_pci_slave_scs_set_window(info->hose_a,
 341                                          0,
 342                                          0x00000000,
 343                                          0x00000000,
 344                                          info->mem_size);
 345
 346         gt64260_pci_slave_scs_set_window(info->hose_b,
 347                                          0,
 348                                          0x00000000,
 349                                          0x00000000,
 350                                          info->mem_size);
 351         pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
 352
 353         /* Disable all the access control windows */
 354         for (window=0; window<GT64260_PCI_ACC_CNTL_WINDOWS; window++) {
 355                 gt64260_pci_acc_cntl_set_window(0, window, 0, 0, 0, 0);
 356                 gt64260_pci_acc_cntl_set_window(1, window, 0, 0, 0, 0);
 357         }
 358
 359         /* Disable all the PCI snoop regions */
 360         for (window=0; window<GT64260_PCI_SNOOP_WINDOWS; window++) {
 361                 gt64260_pci_snoop_set_window(0, window, 0, 0, 0, 0);
 362                 gt64260_pci_snoop_set_window(1, window, 0, 0, 0, 0);
 363         }
 364
 365         gt64260_pci_acc_cntl_set_window(0,
 366                                         0,
 367                                         0x00000000,
 368                                         0x00000000,
 369                                         info->mem_size,
 370                                         (GT64260_PCI_ACC_CNTL_PREFETCHEN |
 371                                          GT64260_PCI_ACC_CNTL_MBURST_4_WORDS |
 372                                          GT64260_PCI_ACC_CNTL_SWAP_BYTE));
 373
 374         gt64260_pci_acc_cntl_set_window(1,
 375                                         0,
 376                                         0x00000000,
 377                                         0x00000000,
 378                                         info->mem_size,
 379                                         (GT64260_PCI_ACC_CNTL_PREFETCHEN |
 380                                          GT64260_PCI_ACC_CNTL_MBURST_4_WORDS |
 381                                          GT64260_PCI_ACC_CNTL_SWAP_BYTE));
 382
 383         gt64260_pci_snoop_set_window(0,
 384                                      0,
 385                                      0x00000000,
 386                                      0x00000000,
 387                                      info->mem_size,
 388                                      GT64260_PCI_SNOOP_WB);
 389
 390         gt64260_pci_snoop_set_window(1,
 391                                      0,
 392                                      0x00000000,
 393                                      0x00000000,
 394                                      info->mem_size,
 395                                      GT64260_PCI_SNOOP_WB);
 396
 397         gt64260_check_errata(info->hose_a, info->hose_b);
 398
 399
 400         /* Set latency timer (to 64) & cacheline size; clear BIST */
 401         gt64260_pci_exclude_bridge = FALSE;
 402         u32_val = ((0x04 << 8) | (L1_CACHE_LINE_SIZE / 4));
 403
 404         early_write_config_dword(info->hose_a,
 405                                  info->hose_a->first_busno,
 406                                  PCI_DEVFN(0,0),
 407                                  PCI_CACHE_LINE_SIZE,
 408                                  u32_val);
 409         early_write_config_dword(info->hose_b,
 410                                  info->hose_b->first_busno,
 411                                  PCI_DEVFN(0,0),
 412                                  PCI_CACHE_LINE_SIZE,
 413                                  u32_val);
 414         gt64260_pci_exclude_bridge = TRUE;
 415
 416         return rc;
 417 } /* gt64260_bridge_init() */
 418
 419 /*
 420  * gt64260_check_errata()
 421  *
 422  * Apply applicable errata and restrictions from 0.5 of the
 423  * Errata and Restrictions document from Marvell/Galileo.
 424  */
 425 static void __init
 426 gt64260_check_errata(struct pci_controller *hose_a,
 427                      struct pci_controller *hose_b)
 428 {
 429         u32     val;
 430         u8      save_exclude;
 431
 432         /* Currently 2 versions, 64260 and 64260A */
 433         if (gt64260_revision == GT64260) {
 434                 save_exclude = gt64260_pci_exclude_bridge;
 435                 gt64260_pci_exclude_bridge = FALSE;
 436
 437                 /* FEr#5, FEr#12 */
 438                 early_read_config_dword(hose_a,
 439                                         hose_a->first_busno,
 440                                         PCI_DEVFN(0,0),
 441                                         PCI_COMMAND,
 442                                         &val);
 443                 val &= ~(PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
 444                 early_write_config_dword(hose_a,
 445                                          hose_a->first_busno,
 446                                          PCI_DEVFN(0,0),
 447                                          PCI_COMMAND,
 448                                          val);
 449
 450                 early_read_config_dword(hose_b,
 451                                         hose_b->first_busno,
 452                                         PCI_DEVFN(0,0),
 453                                         PCI_COMMAND,
 454                                         &val);
 455                 val &= ~(PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
 456                 early_write_config_dword(hose_b,
 457                                          hose_b->first_busno,
 458                                          PCI_DEVFN(0,0),
 459                                          PCI_COMMAND,
 460                                          val);
 461                 gt64260_pci_exclude_bridge = save_exclude;
 462
 463                 /* FEr#12, FEr#13 */
 464                 gt_clr_bits(GT64260_PCI_0_CMD, ((1<<4) | (1<<5) | (1<<9)));
 465                 gt_clr_bits(GT64260_PCI_1_CMD, ((1<<4) | (1<<5) | (1<<9)));
 466
 467                 /* FEr#54 */
 468                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_0, 0xfffcf000);
 469                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_1, 0xfffcf000);
 470                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_2, 0xfffcf000);
 471                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_3, 0xfffcf000);
 472
 473                 /* R#18 */
 474                 gt_set_bits(GT64260_SDRAM_CONFIG, (1<<26));
 475
 476         } else if (gt64260_revision == GT64260A) {
 477                 /* R#18 */
 478                 gt_set_bits(GT64260_SDRAM_CONFIG, (1<<26));
 479
 480                 /* No longer errata so turn on */
 481                 gt_set_bits(GT64260_PCI_0_CMD, ((1<<4) | (1<<5) | (1<<9)));
 482                 gt_set_bits(GT64260_PCI_1_CMD, ((1<<4) | (1<<5) | (1<<9)));
 483         }
 484 } /* gt64260_check_errata() */
 485
 486
 487 /*
 488  *****************************************************************************
 489  *
 490  *      General Window Setting Routines
 491  *
 492  *****************************************************************************
 493  */
 494
 495 static int
 496 gt64260_set_32bit_window(u32 base_addr,
 497                          u32 size,
 498                          u32 other_bits,
 499                          u32 bot_reg,
 500                          u32 top_reg)
 501 {
 502         u32     val;
 503
 504         if (size > 0) {
 505                 /* Set up the window on the CPU side */
 506                 gt_write(bot_reg, (base_addr >> 20) | other_bits);
 507                 gt_write(top_reg, (base_addr + size - 1) >> 20);
 508         } else { /* Disable window */
 509                 gt_write(top_reg, 0x00000000);
 510                 gt_write(bot_reg, 0x00000fff | other_bits);
 511         }
 512
 513         val = gt_read(bot_reg); /* Flush FIFO */
 514         return 0;
 515 } /* gt64260_set_32bit_window() */
 516
 517 static int
 518 gt64260_set_64bit_window(u32 base_addr_hi,
 519                          u32 base_addr_lo,
 520                          u32 size,
 521                          u32 other_bits,
 522                          u32 bot_reg_hi,
 523                          u32 bot_reg_lo,
 524                          u32 top_reg)
 525 {
 526         int     rc;
 527
 528         if ((rc = gt64260_set_32bit_window(base_addr_lo,
 529                                            size,
 530                                            other_bits,
 531                                            bot_reg_lo,
 532                                            top_reg)) == 0) {
 533
 534                 gt_write(bot_reg_hi, base_addr_hi);
 535                 base_addr_hi = gt_read(bot_reg_hi); /* Flush FIFO */
 536         }
 537
 538         return rc;
 539 } /* gt64260_set_64bit_window() */
 540
 541
 542 /*
 543  *****************************************************************************
 544  *
 545  *      CPU Configuration Routines
 546  *
 547  *****************************************************************************
 548  */
 549
 550 int
 551 gt64260_cpu_scs_set_window(u32 window,
 552                            u32 base_addr,
 553                            u32 size)
 554 {
 555         static u32
 556         cpu_scs_windows[GT64260_CPU_SCS_DECODE_WINDOWS][2] = {
 557                 { GT64260_CPU_SCS_DECODE_0_BOT, GT64260_CPU_SCS_DECODE_0_TOP },
 558                 { GT64260_CPU_SCS_DECODE_1_BOT, GT64260_CPU_SCS_DECODE_1_TOP },
 559                 { GT64260_CPU_SCS_DECODE_2_BOT, GT64260_CPU_SCS_DECODE_2_TOP },
 560                 { GT64260_CPU_SCS_DECODE_3_BOT, GT64260_CPU_SCS_DECODE_3_TOP },
 561         }; /* cpu_scs_windows[][] */
 562         int     rc = -1;
 563
 564         if (window < GT64260_CPU_SCS_DECODE_WINDOWS) {
 565                 rc = gt64260_set_32bit_window(base_addr,
 566                                               size,
 567                                               0,
 568                                               cpu_scs_windows[window][0],
 569                                               cpu_scs_windows[window][1]);
 570         }
 571
 572         return rc;
 573 } /* gt64260_cpu_scs_set_window() */
 574
 575 int
 576 gt64260_cpu_cs_set_window(u32 window,
 577                           u32 base_addr,
 578                           u32 size)
 579 {
 580         static u32
 581         cpu_cs_windows[GT64260_CPU_CS_DECODE_WINDOWS][2] = {
 582                 { GT64260_CPU_CS_DECODE_0_BOT, GT64260_CPU_CS_DECODE_0_TOP },
 583                 { GT64260_CPU_CS_DECODE_1_BOT, GT64260_CPU_CS_DECODE_1_TOP },
 584                 { GT64260_CPU_CS_DECODE_2_BOT, GT64260_CPU_CS_DECODE_2_TOP },
 585                 { GT64260_CPU_CS_DECODE_3_BOT, GT64260_CPU_CS_DECODE_3_TOP },
 586         }; /* cpu_cs_windows[][] */
 587         int     rc = -1;
 588
 589         if (window < GT64260_CPU_CS_DECODE_WINDOWS) {
 590                 rc = gt64260_set_32bit_window(base_addr,
 591                                               size,
 592                                               0,
 593                                               cpu_cs_windows[window][0],
 594                                               cpu_cs_windows[window][1]);
 595         }
 596
 597         return rc;
 598 } /* gt64260_cpu_cs_set_window() */
 599
 600 int
 601 gt64260_cpu_boot_set_window(u32 base_addr,
 602                             u32 size)
 603 {
 604         int     rc;
 605
 606         rc = gt64260_set_32bit_window(base_addr,
 607                                       size,
 608                                       0,
 609                                       GT64260_CPU_BOOT_CS_DECODE_0_BOT,
 610                                       GT64260_CPU_BOOT_CS_DECODE_0_TOP);
 611
 612         return rc;
 613 } /* gt64260_cpu_boot_set_window() */
 614
 615 /*
 616  * gt64260_cpu_set_pci_io_window()
 617  *
 618  * Set up a CPU window into PCI I/O or MEM space.
 619  * Always do Read/Modify/Write to window regs.
 620  */
 621 static int
 622 gt64260_cpu_pci_set_window(u32 cpu_base_addr,
 623                            u32 pci_base_addr,
 624                            u32 size,
 625                            u32 other_bits,
 626                            u32 bot_reg,
 627                            u32 top_reg,
 628                            u32 remap_reg)
 629 {
 630         u32     val;
 631         int     rc;
 632
 633         if ((rc = gt64260_set_32bit_window(cpu_base_addr,
 634                                            size,
 635                                            other_bits,
 636                                            bot_reg,
 637                                            top_reg)) == 0) {
 638
 639                 /* Set up CPU->PCI remapping (on lower 32 bits) */
 640                 gt_write(remap_reg, pci_base_addr >> 20);
 641                 val = gt_read(bot_reg); /* Flush FIFO */
 642         }
 643
 644         return rc;
 645 } /* gt64260_cpu_pci_set_window() */
 646
 647
 648 /*
 649  * gt64260_cpu_set_pci_io_window()
 650  *
 651  * Set up a CPU window into PCI I/O space.
 652  * Always do Read/Modify/Write to window regs.
 653  */
 654 int
 655 gt64260_cpu_set_pci_io_window(u32 pci_bus,
 656                               u32 cpu_base_addr,
 657                               u32 pci_base_addr,
 658                               u32 size,
 659                               u32 swap)
 660 {
 661         /* 2 PCI buses with 1 I/O window each (from CPU point of view) */
 662         static u32
 663         cpu_pci_io_windows[GT64260_PCI_BUSES][3] = {
 664                 { GT64260_CPU_PCI_0_IO_DECODE_BOT,
 665                   GT64260_CPU_PCI_0_IO_DECODE_TOP,
 666                   GT64260_CPU_PCI_0_IO_REMAP },
 667
 668                 { GT64260_CPU_PCI_1_IO_DECODE_BOT,
 669                   GT64260_CPU_PCI_1_IO_DECODE_TOP,
 670                   GT64260_CPU_PCI_1_IO_REMAP },
 671         }; /* cpu_pci_io_windows[][] */
 672         int     rc = -1;
 673
 674         if (pci_bus < GT64260_PCI_BUSES) {
 675                 rc =  gt64260_cpu_pci_set_window(cpu_base_addr,
 676                                           pci_base_addr,
 677                                           size,
 678                                           swap,
 679                                           cpu_pci_io_windows[pci_bus][0],
 680                                           cpu_pci_io_windows[pci_bus][1],
 681                                           cpu_pci_io_windows[pci_bus][2]);
 682         }
 683
 684         return rc;
 685 } /* gt64260_cpu_set_pci_io_window() */
 686
 687 /*
 688  * gt64260_cpu_set_pci_mem_window()
 689  *
 690  * Set up a CPU window into PCI MEM space (4 PCI MEM windows per PCI bus).
 691  * Always do Read/Modify/Write to window regs.
 692  */
 693 int
 694 gt64260_cpu_set_pci_mem_window(u32 pci_bus,
 695                                u32 window,
 696                                u32 cpu_base_addr,
 697                                u32 pci_base_addr_hi,
 698                                u32 pci_base_addr_lo,
 699                                u32 size,
 700                                u32 swap_64bit)
 701 {
 702         /* 2 PCI buses with 4 memory windows each (from CPU point of view) */
 703         static u32
 704         cpu_pci_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_MEM_WINDOWS_PER_BUS][4] = {
 705                 { /* PCI 0 */
 706                         { GT64260_CPU_PCI_0_MEM_0_DECODE_BOT,
 707                           GT64260_CPU_PCI_0_MEM_0_DECODE_TOP,
 708                           GT64260_CPU_PCI_0_MEM_0_REMAP_HI,
 709                           GT64260_CPU_PCI_0_MEM_0_REMAP_LO },
 710
 711                         { GT64260_CPU_PCI_0_MEM_1_DECODE_BOT,
 712                           GT64260_CPU_PCI_0_MEM_1_DECODE_TOP,
 713                           GT64260_CPU_PCI_0_MEM_1_REMAP_HI,
 714                           GT64260_CPU_PCI_0_MEM_1_REMAP_LO },
 715
 716                         { GT64260_CPU_PCI_0_MEM_2_DECODE_BOT,
 717                           GT64260_CPU_PCI_0_MEM_2_DECODE_TOP,
 718                           GT64260_CPU_PCI_0_MEM_2_REMAP_HI,
 719                           GT64260_CPU_PCI_0_MEM_2_REMAP_LO },
 720
 721                         { GT64260_CPU_PCI_0_MEM_3_DECODE_BOT,
 722                           GT64260_CPU_PCI_0_MEM_3_DECODE_TOP,
 723                           GT64260_CPU_PCI_0_MEM_3_REMAP_HI,
 724                           GT64260_CPU_PCI_0_MEM_3_REMAP_LO }
 725                 },
 726
 727                 { /* PCI 1 */
 728                         { GT64260_CPU_PCI_1_MEM_0_DECODE_BOT,
 729                           GT64260_CPU_PCI_1_MEM_0_DECODE_TOP,
 730                           GT64260_CPU_PCI_1_MEM_0_REMAP_HI,
 731                           GT64260_CPU_PCI_1_MEM_0_REMAP_LO },
 732
 733                         { GT64260_CPU_PCI_1_MEM_1_DECODE_BOT,
 734                           GT64260_CPU_PCI_1_MEM_1_DECODE_TOP,
 735                           GT64260_CPU_PCI_1_MEM_1_REMAP_HI,
 736                           GT64260_CPU_PCI_1_MEM_1_REMAP_LO },
 737
 738                         { GT64260_CPU_PCI_1_MEM_2_DECODE_BOT,
 739                           GT64260_CPU_PCI_1_MEM_2_DECODE_TOP,
 740                           GT64260_CPU_PCI_1_MEM_2_REMAP_HI,
 741                           GT64260_CPU_PCI_1_MEM_2_REMAP_LO },
 742
 743                         { GT64260_CPU_PCI_1_MEM_3_DECODE_BOT,
 744                           GT64260_CPU_PCI_1_MEM_3_DECODE_TOP,
 745                           GT64260_CPU_PCI_1_MEM_3_REMAP_HI,
 746                           GT64260_CPU_PCI_1_MEM_3_REMAP_LO },
 747                 }
 748         }; /* cpu_pci_mem_windows[][][] */
 749         u32             remap_reg, remap;
 750         int             rc = -1;
 751
 752         if ((pci_bus < GT64260_PCI_BUSES) &&
 753             (window < GT64260_PCI_MEM_WINDOWS_PER_BUS)) {
 754
 755                 if (gt64260_cpu_pci_set_window(
 756                         cpu_base_addr,
 757                         pci_base_addr_lo,
 758                         size,
 759                         swap_64bit,
 760                         cpu_pci_mem_windows[pci_bus][window][0],
 761                         cpu_pci_mem_windows[pci_bus][window][1],
 762                         cpu_pci_mem_windows[pci_bus][window][3]) == 0) {
 763
 764                         remap_reg = cpu_pci_mem_windows[pci_bus][window][2];
 765                         gt_write(remap_reg, pci_base_addr_hi);
 766
 767                         remap = gt_read(remap_reg); /* Flush FIFO */
 768
 769                         rc = 0;
 770                 }
 771         }
 772
 773         return rc;
 774 } /* gt64260_cpu_set_pci_mem_window() */
 775
 776 int
 777 gt64260_cpu_prot_set_window(u32 window,
 778                             u32 base_addr,
 779                             u32 size,
 780                             u32 access_bits)
 781 {
 782         static u32
 783         cpu_prot_windows[GT64260_CPU_PROT_WINDOWS][2] = {
 784                 { GT64260_CPU_PROT_BASE_0, GT64260_CPU_PROT_TOP_0 },
 785                 { GT64260_CPU_PROT_BASE_1, GT64260_CPU_PROT_TOP_1 },
 786                 { GT64260_CPU_PROT_BASE_2, GT64260_CPU_PROT_TOP_2 },
 787                 { GT64260_CPU_PROT_BASE_3, GT64260_CPU_PROT_TOP_3 },
 788                 { GT64260_CPU_PROT_BASE_4, GT64260_CPU_PROT_TOP_4 },
 789                 { GT64260_CPU_PROT_BASE_5, GT64260_CPU_PROT_TOP_5 },
 790                 { GT64260_CPU_PROT_BASE_6, GT64260_CPU_PROT_TOP_6 },
 791                 { GT64260_CPU_PROT_BASE_7, GT64260_CPU_PROT_TOP_7 },
 792         }; /* cpu_prot_windows[][] */
 793         int     rc = -1;
 794
 795         if (window < GT64260_CPU_PROT_WINDOWS) {
 796                 rc = gt64260_set_32bit_window(base_addr,
 797                                               size,
 798                                               access_bits,
 799                                               cpu_prot_windows[window][0],
 800                                               cpu_prot_windows[window][1]);
 801         }
 802
 803         return rc;
 804 } /* gt64260_cpu_prot_set_window() */
 805
 806 int
 807 gt64260_cpu_snoop_set_window(u32 window,
 808                              u32 base_addr,
 809                              u32 size,
 810                              u32  snoop_type)
 811 {
 812         static u32
 813         cpu_snoop_windows[GT64260_CPU_SNOOP_WINDOWS][2] = {
 814                 { GT64260_CPU_SNOOP_BASE_0, GT64260_CPU_SNOOP_TOP_0 },
 815                 { GT64260_CPU_SNOOP_BASE_1, GT64260_CPU_SNOOP_TOP_1 },
 816                 { GT64260_CPU_SNOOP_BASE_2, GT64260_CPU_SNOOP_TOP_2 },
 817                 { GT64260_CPU_SNOOP_BASE_3, GT64260_CPU_SNOOP_TOP_3 },
 818         }; /* cpu_snoop_windows[][] */
 819         int     rc = -1;
 820
 821         if ((window < GT64260_CPU_SNOOP_WINDOWS) &&
 822             (snoop_type <= GT64260_CPU_SNOOP_WB)) {
 823
 824                 rc = gt64260_set_32bit_window(base_addr,
 825                                               size,
 826                                               snoop_type,
 827                                               cpu_snoop_windows[window][0],
 828                                               cpu_snoop_windows[window][1]);
 829         }
 830
 831         return rc;
 832 } /* gt64260_cpu_snoop_set_window() */
 833
 834 void
 835 gt64260_cpu_disable_all_windows(void)
 836 {
 837         int     pci_bus, window;
 838
 839         /* Don't disable SCS windows b/c we need to access system memory */
 840
 841         for (window=0; window<GT64260_CPU_CS_DECODE_WINDOWS; window++) {
 842                 gt64260_cpu_cs_set_window(window, 0, 0);
 843         }
 844
 845         gt64260_cpu_boot_set_window(0, 0);
 846
 847         for (pci_bus=0; pci_bus<GT64260_PCI_BUSES; pci_bus++) {
 848                 gt64260_cpu_set_pci_io_window(pci_bus, 0, 0, 0, 0);
 849
 850                 for (window=0;window<GT64260_PCI_MEM_WINDOWS_PER_BUS;window++) {
 851                         gt64260_cpu_set_pci_mem_window(pci_bus,
 852                                                        window,
 853                                                        0, 0, 0, 0, 0);
 854                 }
 855         }
 856
 857         for (window=0; window<GT64260_CPU_PROT_WINDOWS; window++) {
 858                 gt64260_cpu_prot_set_window(window, 0, 0, 0);
 859         }
 860
 861         for (window=0; window<GT64260_CPU_SNOOP_WINDOWS; window++) {
 862                 gt64260_cpu_snoop_set_window(window, 0, 0, 0);
 863         }
 864
 865         return;
 866 } /* gt64260_cpu_disable_all_windows() */
 867
 868
 869 /*
 870  *****************************************************************************
 871  *
 872  *      PCI Slave Window Configuration Routines
 873  *
 874  *****************************************************************************
 875  */
 876
 877 int
 878 gt64260_pci_bar_enable(u32 pci_bus,
 879                        u32 enable_bits)
 880 {
 881         u32     reg, val;
 882         int     rc = -1;
 883
 884         if (pci_bus < GT64260_PCI_BUSES) {
 885                 reg = (pci_bus == 0) ? GT64260_PCI_0_SLAVE_BAR_REG_ENABLES :
 886                                        GT64260_PCI_1_SLAVE_BAR_REG_ENABLES;
 887
 888
 889                 /* Note: '0' enables, '1' disables */
 890                 val = gt_read(reg);
 891                 val |= 0xffffffff;      /* Disable everything by default */
 892                 val &= ~enable_bits;
 893                 gt_write(reg, val);
 894
 895                 gt_read(reg); /* Flush FIFO */
 896
 897                 rc = 0;
 898         }
 899
 900         return rc;
 901 } /* gt64260_pci_bar_enable() */
 902
 903 static int
 904 gt64260_pci_slave_set_window(struct pci_controller *hose,
 905                              u32 pci_base_addr,
 906                              u32 cpu_base_addr,
 907                              u32 bar_size,
 908                              u32 pci_cfg_fcn,
 909                              u32 pci_cfg_hdr_offset,
 910                              u32 bar_size_reg,
 911                              u32 remap_reg)
 912 {
 913         u32     val;
 914         int     devfn;
 915         u8      save_exclude;
 916
 917         pci_base_addr &= 0xfffff000;
 918         cpu_base_addr &= 0xfffff000;
 919         bar_size &= 0xfffff000;
 920         devfn = PCI_DEVFN(0, pci_cfg_fcn);
 921
 922         gt_write(bar_size_reg, (bar_size - 1) & 0xfffff000);
 923         gt_write(remap_reg, cpu_base_addr);
 924         gt_read(remap_reg); /* Flush FIFO */
 925
 926         save_exclude = gt64260_pci_exclude_bridge;
 927         gt64260_pci_exclude_bridge = FALSE;
 928         early_read_config_dword(hose,
 929                                 hose->first_busno,
 930                                 devfn,
 931                                 pci_cfg_hdr_offset,
 932                                 &val);
 933         val &= 0x0000000f;
 934         early_write_config_dword(hose,
 935                                  hose->first_busno,
 936                                  devfn,
 937                                  pci_cfg_hdr_offset,
 938                                  pci_base_addr | val);
 939         gt64260_pci_exclude_bridge = save_exclude;
 940
 941         return 0;
 942 } /* gt64260_pci_slave_set_window() */
 943
 944 int
 945 gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
 946                                  u32 window,
 947                                  u32 pci_base_addr,
 948                                  u32 cpu_base_addr,
 949                                  u32 size)
 950 {
 951         static u32
 952         pci_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_SCS_WINDOWS][4] = {
 953                 { /* PCI 0 */
 954                         { 0, 0x10,
 955                           GT64260_PCI_0_SLAVE_SCS_0_SIZE,
 956                           GT64260_PCI_0_SLAVE_SCS_0_REMAP },
 957                         { 0, 0x14,
 958                           GT64260_PCI_0_SLAVE_SCS_1_SIZE,
 959                           GT64260_PCI_0_SLAVE_SCS_1_REMAP },
 960                         { 0, 0x18,
 961                           GT64260_PCI_0_SLAVE_SCS_2_SIZE,
 962                           GT64260_PCI_0_SLAVE_SCS_2_REMAP },
 963                         { 0, 0x1c,
 964                           GT64260_PCI_0_SLAVE_SCS_3_SIZE,
 965                           GT64260_PCI_0_SLAVE_SCS_3_REMAP },
 966                 },
 967                 { /* PCI 1 */
 968                         { 0, 0x10,
 969                           GT64260_PCI_1_SLAVE_SCS_0_SIZE,
 970                           GT64260_PCI_1_SLAVE_SCS_0_REMAP },
 971                         { 0, 0x14,
 972                           GT64260_PCI_1_SLAVE_SCS_1_SIZE,
 973                           GT64260_PCI_1_SLAVE_SCS_1_REMAP },
 974                         { 0, 0x18,
 975                           GT64260_PCI_1_SLAVE_SCS_2_SIZE,
 976                           GT64260_PCI_1_SLAVE_SCS_2_REMAP },
 977                         { 0, 0x1c,
 978                           GT64260_PCI_1_SLAVE_SCS_3_SIZE,
 979                           GT64260_PCI_1_SLAVE_SCS_3_REMAP },
 980                 }
 981         }; /* pci_scs_windows[][][] */
 982         int     pci_bus;
 983         int     rc = -1;
 984
 985         if (window < GT64260_PCI_SCS_WINDOWS) {
 986                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
 987
 988                 rc = gt64260_pci_slave_set_window(
 989                                 hose,
 990                                 pci_base_addr,
 991                                 cpu_base_addr,
 992                                 size,
 993                                 pci_scs_windows[pci_bus][window][0],
 994                                 pci_scs_windows[pci_bus][window][1],
 995                                 pci_scs_windows[pci_bus][window][2],
 996                                 pci_scs_windows[pci_bus][window][3]);
 997         }
 998
 999         return rc;
1000 } /* gt64260_pci_slave_scs_set_window() */
1001
1002 int
1003 gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
1004                                 u32 window,
1005                                 u32 pci_base_addr,
1006                                 u32 cpu_base_addr,
1007                                 u32 size)
1008 {
1009         static u32
1010         pci_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_CS_WINDOWS][4] = {
1011                 { /* PCI 0 */
1012                         { 1, 0x10,
1013                           GT64260_PCI_0_SLAVE_CS_0_SIZE,
1014                           GT64260_PCI_0_SLAVE_CS_0_REMAP },
1015                         { 1, 0x14,
1016                           GT64260_PCI_0_SLAVE_CS_1_SIZE,
1017                           GT64260_PCI_0_SLAVE_CS_1_REMAP },
1018                         { 1, 0x18,
1019                           GT64260_PCI_0_SLAVE_CS_2_SIZE,
1020                           GT64260_PCI_0_SLAVE_CS_2_REMAP },
1021                         { 1, 0x1c,
1022                           GT64260_PCI_0_SLAVE_CS_3_SIZE,
1023                           GT64260_PCI_0_SLAVE_CS_3_REMAP },
1024                 },
1025                 { /* PCI 1 */
1026                         { 1, 0x10,
1027                           GT64260_PCI_1_SLAVE_CS_0_SIZE,
1028                           GT64260_PCI_1_SLAVE_CS_0_REMAP },
1029                         { 1, 0x14,
1030                           GT64260_PCI_1_SLAVE_CS_1_SIZE,
1031                           GT64260_PCI_1_SLAVE_CS_1_REMAP },
1032                         { 1, 0x18,
1033                           GT64260_PCI_1_SLAVE_CS_2_SIZE,
1034                           GT64260_PCI_1_SLAVE_CS_2_REMAP },
1035                         { 1, 0x1c,
1036                           GT64260_PCI_1_SLAVE_CS_3_SIZE,
1037                           GT64260_PCI_1_SLAVE_CS_3_REMAP },
1038                 }
1039         }; /* pci_cs_windows[][][] */
1040         int     pci_bus;
1041         int     rc = -1;
1042
1043         if (window < GT64260_PCI_CS_WINDOWS) {
1044                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1045
1046                 rc = gt64260_pci_slave_set_window(
1047                                 hose,
1048                                 pci_base_addr,
1049                                 cpu_base_addr,
1050                                 size,
1051                                 pci_cs_windows[pci_bus][window][0],
1052                                 pci_cs_windows[pci_bus][window][1],
1053                                 pci_cs_windows[pci_bus][window][2],
1054                                 pci_cs_windows[pci_bus][window][3]);
1055         }
1056
1057         return rc;
1058 } /* gt64260_pci_slave_cs_set_window() */
1059
1060 int
1061 gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
1062                                   u32 pci_base_addr,
1063                                   u32 cpu_base_addr,
1064                                   u32 size)
1065 {
1066         int     rc;
1067
1068         rc = gt64260_pci_slave_set_window(hose,
1069                                           pci_base_addr,
1070                                           cpu_base_addr,
1071                                           size,
1072                                           1,
1073                                           0x20,
1074                                           GT64260_PCI_1_SLAVE_BOOT_SIZE,
1075                                           GT64260_PCI_1_SLAVE_BOOT_REMAP);
1076
1077         return rc;
1078 } /* gt64260_pci_slave_boot_set_window() */
1079
1080 int
1081 gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
1082                                      u32 window,
1083                                      u32 pci_base_addr,
1084                                      u32 other_bus_base_addr,
1085                                      u32 size)
1086 {
1087         static u32
1088         pci_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_P2P_MEM_WINDOWS][4]={
1089                 { /* PCI 0 */
1090                         { 2, 0x10,
1091                           GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE,
1092                           GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO },
1093                         { 2, 0x14,
1094                           GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE,
1095                           GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO },
1096                 },
1097                 { /* PCI 1 */
1098                         { 2, 0x10,
1099                           GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE,
1100                           GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO },
1101                         { 2, 0x14,
1102                           GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE,
1103                           GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO },
1104                 }
1105         }; /* pci_p2p_mem_windows[][][] */
1106         int     pci_bus;
1107         int     rc = -1;
1108
1109         if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
1110                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1111
1112                 rc = gt64260_pci_slave_set_window(
1113                                 hose,
1114                                 pci_base_addr,
1115                                 other_bus_base_addr,
1116                                 size,
1117                                 pci_p2p_mem_windows[pci_bus][window][0],
1118                                 pci_p2p_mem_windows[pci_bus][window][1],
1119                                 pci_p2p_mem_windows[pci_bus][window][2],
1120                                 pci_p2p_mem_windows[pci_bus][window][3]);
1121         }
1122
1123         return rc;
1124 } /* gt64260_pci_slave_p2p_mem_set_window() */
1125
1126 int
1127 gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
1128                                     u32 pci_base_addr,
1129                                     u32 other_bus_base_addr,
1130                                     u32 size)
1131 {
1132         int     rc;
1133
1134         rc = gt64260_pci_slave_set_window(hose,
1135                                           pci_base_addr,
1136                                           other_bus_base_addr,
1137                                           size,
1138                                           2,
1139                                           0x18,
1140                                           GT64260_PCI_1_SLAVE_P2P_IO_SIZE,
1141                                           GT64260_PCI_1_SLAVE_P2P_IO_REMAP);
1142
1143         return rc;
1144 } /* gt64260_pci_slave_p2p_io_set_window() */
1145
1146 int
1147 gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
1148                                      u32 window,
1149                                      u32 pci_base_addr_hi,
1150                                      u32 pci_base_addr_lo,
1151                                      u32 cpu_base_addr,
1152                                      u32 size)
1153 {
1154         static u32
1155         pci_dac_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_SCS_WINDOWS][5]={
1156                 { /* PCI 0 */
1157                         { 4, 0x10, 0x14,
1158                           GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE,
1159                           GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP },
1160                         { 4, 0x18, 0x1c,
1161                           GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE,
1162                           GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP },
1163                         { 5, 0x10, 0x14,
1164                           GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE,
1165                           GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP },
1166                         { 5, 0x18, 0x1c,
1167                           GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE,
1168                           GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP },
1169                 },
1170                 { /* PCI 1 */
1171                         { 4, 0x10, 0x14,
1172                           GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE,
1173                           GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP },
1174                         { 4, 0x18, 0x1c,
1175                           GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE,
1176                           GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP },
1177                         { 5, 0x10, 0x14,
1178                           GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE,
1179                           GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP },
1180                         { 5, 0x18, 0x1c,
1181                           GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE,
1182                           GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP },
1183                 }
1184         }; /* pci_dac_scs_windows[][][] */
1185         int     pci_bus;
1186         int     rc = -1;
1187
1188         if (window < GT64260_PCI_DAC_SCS_WINDOWS) {
1189                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1190
1191                 rc = gt64260_pci_slave_set_window(
1192                                 hose,
1193                                 pci_base_addr_lo,
1194                                 cpu_base_addr,
1195                                 size,
1196                                 pci_dac_scs_windows[pci_bus][window][0],
1197                                 pci_dac_scs_windows[pci_bus][window][1],
1198                                 pci_dac_scs_windows[pci_bus][window][3],
1199                                 pci_dac_scs_windows[pci_bus][window][4]);
1200
1201                 early_write_config_dword(
1202                         hose,
1203                         hose->first_busno,
1204                         PCI_DEVFN(0, pci_dac_scs_windows[pci_bus][window][0]),
1205                         pci_dac_scs_windows[pci_bus][window][2],
1206                         pci_base_addr_hi);
1207         }
1208
1209         return rc;
1210 } /* gt64260_pci_slave_dac_scs_set_window() */
1211
1212 int
1213 gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
1214                                     u32 window,
1215                                     u32 pci_base_addr_hi,
1216                                     u32 pci_base_addr_lo,
1217                                     u32 cpu_base_addr,
1218                                     u32 size)
1219 {
1220         static u32
1221         pci_dac_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_CS_WINDOWS][5] = {
1222                 { /* PCI 0 */
1223                         { 6, 0x10, 0x14,
1224                           GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE,
1225                           GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP },
1226                         { 6, 0x18, 0x1c,
1227                           GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE,
1228                           GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP },
1229                         { 6, 0x20, 0x24,
1230                           GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE,
1231                           GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP },
1232                         { 7, 0x10, 0x14,
1233                           GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE,
1234                           GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP },
1235                 },
1236                 { /* PCI 1 */
1237                         { 6, 0x10, 0x14,
1238                           GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE,
1239                           GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP },
1240                         { 6, 0x18, 0x1c,
1241                           GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE,
1242                           GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP },
1243                         { 6, 0x20, 0x24,
1244                           GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE,
1245                           GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP },
1246                         { 7, 0x10, 0x14,
1247                           GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE,
1248                           GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP },
1249                 }
1250         }; /* pci_dac_cs_windows[][][] */
1251         int     pci_bus;
1252         int     rc = -1;
1253
1254         if (window < GT64260_PCI_CS_WINDOWS) {
1255                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1256
1257                 rc = gt64260_pci_slave_set_window(
1258                                 hose,
1259                                 pci_base_addr_lo,
1260                                 cpu_base_addr,
1261                                 size,
1262                                 pci_dac_cs_windows[pci_bus][window][0],
1263                                 pci_dac_cs_windows[pci_bus][window][1],
1264                                 pci_dac_cs_windows[pci_bus][window][3],
1265                                 pci_dac_cs_windows[pci_bus][window][4]);
1266
1267                 early_write_config_dword(
1268                         hose,
1269                         hose->first_busno,
1270                         PCI_DEVFN(0, pci_dac_cs_windows[pci_bus][window][0]),
1271                         pci_dac_cs_windows[pci_bus][window][2],
1272                         pci_base_addr_hi);
1273         }
1274
1275         return rc;
1276 } /* gt64260_pci_slave_dac_cs_set_window() */
1277
1278 int
1279 gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
1280                                       u32 pci_base_addr_hi,
1281                                       u32 pci_base_addr_lo,
1282                                       u32 cpu_base_addr,
1283                                       u32 size)
1284 {
1285         int     rc;
1286
1287         rc = gt64260_pci_slave_set_window(hose,
1288                                           pci_base_addr_lo,
1289                                           cpu_base_addr,
1290                                           size,
1291                                           7,
1292                                           0x18,
1293                                           GT64260_PCI_1_SLAVE_BOOT_SIZE,
1294                                           GT64260_PCI_1_SLAVE_BOOT_REMAP);
1295
1296         early_write_config_dword(hose,
1297                                  hose->first_busno,
1298                                  PCI_DEVFN(0, 7),
1299                                  0x1c,
1300                                  pci_base_addr_hi);
1301
1302         return rc;
1303 } /* gt64260_pci_slave_dac_boot_set_window() */
1304
1305 int
1306 gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
1307                                          u32 window,
1308                                          u32 pci_base_addr_hi,
1309                                          u32 pci_base_addr_lo,
1310                                          u32 other_bus_base_addr,
1311                                          u32 size)
1312 {
1313         static u32
1314         pci_dac_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_P2P_MEM_WINDOWS][5] = {
1315                 { /* PCI 0 */
1316                         { 4, 0x20, 0x24,
1317                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
1318                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
1319                         { 5, 0x20, 0x24,
1320                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
1321                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
1322                 },
1323                 { /* PCI 1 */
1324                         { 4, 0xa0, 0xa4,
1325                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
1326                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
1327                         { 5, 0xa0, 0xa4,
1328                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
1329                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
1330                 }
1331         }; /* pci_dac_p2p_windows[][][] */
1332         int     pci_bus;
1333         int     rc = -1;
1334
1335         if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
1336                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1337
1338                 rc = gt64260_pci_slave_set_window(
1339                                 hose,
1340                                 pci_base_addr_lo,
1341                                 other_bus_base_addr,
1342                                 size,
1343                                 pci_dac_p2p_mem_windows[pci_bus][window][0],
1344                                 pci_dac_p2p_mem_windows[pci_bus][window][1],
1345                                 pci_dac_p2p_mem_windows[pci_bus][window][3],
1346                                 pci_dac_p2p_mem_windows[pci_bus][window][4]);
1347
1348                 early_write_config_dword(
1349                     hose,
1350                     hose->first_busno,
1351                     PCI_DEVFN(0, pci_dac_p2p_mem_windows[pci_bus][window][0]),
1352                     pci_dac_p2p_mem_windows[pci_bus][window][2],
1353                     pci_base_addr_hi);
1354         }
1355
1356         return rc;
1357 } /* gt64260_pci_slave_dac_p2p_mem_set_window() */
1358
1359
1360 /*
1361  *****************************************************************************
1362  *
1363  *      PCI Control Configuration Routines
1364  *
1365  *****************************************************************************
1366  */
1367
1368
1369 int
1370 gt64260_pci_acc_cntl_set_window(u32 pci_bus,
1371                                 u32 window,
1372                                 u32 base_addr_hi,
1373                                 u32 base_addr_lo,
1374                                 u32 size,
1375                                 u32 features)
1376 {
1377         static u32
1378         pci_acc_cntl_windows[GT64260_PCI_BUSES][GT64260_PCI_ACC_CNTL_WINDOWS][3] = {
1379                 { /* PCI 0 */
1380                         { GT64260_PCI_0_ACC_CNTL_0_BASE_HI,
1381                           GT64260_PCI_0_ACC_CNTL_0_BASE_LO,
1382                           GT64260_PCI_0_ACC_CNTL_0_TOP },
1383
1384                         { GT64260_PCI_0_ACC_CNTL_1_BASE_HI,
1385                           GT64260_PCI_0_ACC_CNTL_1_BASE_LO,
1386                           GT64260_PCI_0_ACC_CNTL_1_TOP },
1387
1388                         { GT64260_PCI_0_ACC_CNTL_2_BASE_HI,
1389                           GT64260_PCI_0_ACC_CNTL_2_BASE_LO,
1390                           GT64260_PCI_0_ACC_CNTL_2_TOP },
1391
1392                         { GT64260_PCI_0_ACC_CNTL_3_BASE_HI,
1393                           GT64260_PCI_0_ACC_CNTL_3_BASE_LO,
1394                           GT64260_PCI_0_ACC_CNTL_3_TOP },
1395
1396                         { GT64260_PCI_0_ACC_CNTL_4_BASE_HI,
1397                           GT64260_PCI_0_ACC_CNTL_4_BASE_LO,
1398                           GT64260_PCI_0_ACC_CNTL_4_TOP },
1399
1400                         { GT64260_PCI_0_ACC_CNTL_5_BASE_HI,
1401                           GT64260_PCI_0_ACC_CNTL_5_BASE_LO,
1402                           GT64260_PCI_0_ACC_CNTL_5_TOP },
1403
1404                         { GT64260_PCI_0_ACC_CNTL_6_BASE_HI,
1405                           GT64260_PCI_0_ACC_CNTL_6_BASE_LO,
1406                           GT64260_PCI_0_ACC_CNTL_6_TOP },
1407
1408                         { GT64260_PCI_0_ACC_CNTL_7_BASE_HI,
1409                           GT64260_PCI_0_ACC_CNTL_7_BASE_LO,
1410                           GT64260_PCI_0_ACC_CNTL_7_TOP },
1411                 },
1412                 { /* PCI 1 */
1413                         { GT64260_PCI_1_ACC_CNTL_0_BASE_HI,
1414                           GT64260_PCI_1_ACC_CNTL_0_BASE_LO,
1415                           GT64260_PCI_1_ACC_CNTL_0_TOP },
1416
1417                         { GT64260_PCI_1_ACC_CNTL_1_BASE_HI,
1418                           GT64260_PCI_1_ACC_CNTL_1_BASE_LO,
1419                           GT64260_PCI_1_ACC_CNTL_1_TOP },
1420
1421                         { GT64260_PCI_1_ACC_CNTL_2_BASE_HI,
1422                           GT64260_PCI_1_ACC_CNTL_2_BASE_LO,
1423                           GT64260_PCI_1_ACC_CNTL_2_TOP },
1424
1425                         { GT64260_PCI_1_ACC_CNTL_3_BASE_HI,
1426                           GT64260_PCI_1_ACC_CNTL_3_BASE_LO,
1427                           GT64260_PCI_1_ACC_CNTL_3_TOP },
1428
1429                         { GT64260_PCI_1_ACC_CNTL_4_BASE_HI,
1430                           GT64260_PCI_1_ACC_CNTL_4_BASE_LO,
1431                           GT64260_PCI_1_ACC_CNTL_4_TOP },
1432
1433                         { GT64260_PCI_1_ACC_CNTL_5_BASE_HI,
1434                           GT64260_PCI_1_ACC_CNTL_5_BASE_LO,
1435                           GT64260_PCI_1_ACC_CNTL_5_TOP },
1436
1437                         { GT64260_PCI_1_ACC_CNTL_6_BASE_HI,
1438                           GT64260_PCI_1_ACC_CNTL_6_BASE_LO,
1439                           GT64260_PCI_1_ACC_CNTL_6_TOP },
1440
1441                         { GT64260_PCI_1_ACC_CNTL_7_BASE_HI,
1442                           GT64260_PCI_1_ACC_CNTL_7_BASE_LO,
1443                           GT64260_PCI_1_ACC_CNTL_7_TOP },
1444                 }
1445         }; /* pci_acc_cntl_windows[][][] */
1446         int     rc = -1;
1447
1448         if ((pci_bus < GT64260_PCI_BUSES) &&
1449             (window < GT64260_PCI_ACC_CNTL_WINDOWS)) {
1450
1451                 rc = gt64260_set_64bit_window(
1452                               base_addr_hi,
1453                               base_addr_lo,
1454                               size,
1455                               features,
1456                               pci_acc_cntl_windows[pci_bus][window][0],
1457                               pci_acc_cntl_windows[pci_bus][window][1],
1458                               pci_acc_cntl_windows[pci_bus][window][2]);
1459         }
1460
1461         return rc;
1462 } /* gt64260_pci_acc_cntl_set_window() */
1463
1464 int
1465 gt64260_pci_snoop_set_window(u32 pci_bus,
1466                              u32 window,
1467                              u32 base_addr_hi,
1468                              u32 base_addr_lo,
1469                              u32 size,
1470                              u32 snoop_type)
1471 {
1472         static u32
1473         pci_snoop_windows[GT64260_PCI_BUSES][GT64260_PCI_SNOOP_WINDOWS][3] = {
1474                 { /* PCI 0 */
1475                         { GT64260_PCI_0_SNOOP_0_BASE_HI,
1476                           GT64260_PCI_0_SNOOP_0_BASE_LO,
1477                           GT64260_PCI_0_SNOOP_0_TOP },
1478
1479                         { GT64260_PCI_0_SNOOP_1_BASE_HI,
1480                           GT64260_PCI_0_SNOOP_1_BASE_LO,
1481                           GT64260_PCI_0_SNOOP_1_TOP },
1482
1483                         { GT64260_PCI_0_SNOOP_2_BASE_HI,
1484                           GT64260_PCI_0_SNOOP_2_BASE_LO,
1485                           GT64260_PCI_0_SNOOP_2_TOP },
1486
1487                         { GT64260_PCI_0_SNOOP_3_BASE_HI,
1488                           GT64260_PCI_0_SNOOP_3_BASE_LO,
1489                           GT64260_PCI_0_SNOOP_3_TOP },
1490                 },
1491                 { /* PCI 1 */
1492                         { GT64260_PCI_1_SNOOP_0_BASE_HI,
1493                           GT64260_PCI_1_SNOOP_0_BASE_LO,
1494                           GT64260_PCI_1_SNOOP_0_TOP },
1495
1496                         { GT64260_PCI_1_SNOOP_1_BASE_HI,
1497                           GT64260_PCI_1_SNOOP_1_BASE_LO,
1498                           GT64260_PCI_1_SNOOP_1_TOP },
1499
1500                         { GT64260_PCI_1_SNOOP_2_BASE_HI,
1501                           GT64260_PCI_1_SNOOP_2_BASE_LO,
1502                           GT64260_PCI_1_SNOOP_2_TOP },
1503
1504                         { GT64260_PCI_1_SNOOP_3_BASE_HI,
1505                           GT64260_PCI_1_SNOOP_3_BASE_LO,
1506                           GT64260_PCI_1_SNOOP_3_TOP },
1507                 },
1508         }; /* pci_snoop_windows[][][] */
1509         int     rc = -1;
1510
1511         if ((pci_bus < GT64260_PCI_BUSES) &&
1512             (window < GT64260_PCI_SNOOP_WINDOWS)) {
1513
1514                 rc = gt64260_set_64bit_window(
1515                               base_addr_hi,
1516                               base_addr_lo,
1517                               size,
1518                               snoop_type,
1519                               pci_snoop_windows[pci_bus][window][0],
1520                               pci_snoop_windows[pci_bus][window][1],
1521                               pci_snoop_windows[pci_bus][window][2]);
1522         }
1523
1524         return rc;
1525 } /* gt64260_pci_snoop_set_window() */
1526
1527 /*
1528  *****************************************************************************
1529  *
1530  *      64260's Register Base Address Routines
1531  *
1532  *****************************************************************************
1533  */
1534
1535 /*
1536  * gt64260_remap_bridge_regs()
1537  *
1538  * Move the bridge's register to the specified base address.
1539  * Assume that there are no other windows overlapping this area and that
1540  * all but the highest 3 nibbles are 0.
1541  */
1542 int
1543 gt64260_set_base(u32 new_base)
1544 {
1545         u32     val;
1546         int     limit = 100000;
1547         int     rc = 0;
1548
1549         val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
1550         val = (new_base >> 20) | (val & 0xffff0000);
1551         gt_write(GT64260_INTERNAL_SPACE_DECODE, val);
1552
1553         iounmap((void *)gt64260_base);
1554         gt64260_base = (u32)ioremap((new_base & 0xfff00000),
1555                                     GT64260_INTERNAL_SPACE_SIZE);
1556
1557         do { /* Wait for bridge to move its regs */
1558                 val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
1559         } while ((val != 0xffffffff) && (limit-- > 0));
1560
1561         if (limit <= 0) {
1562                 rc = -1;
1563         }
1564
1565         return rc;
1566 } /* gt64260_remap_bridge_regs() */
1567
1568 /*
1569  * gt64260_get_base()
1570  *
1571  * Return the current virtual base address of the 64260's registers.
1572  */
1573 int
1574 gt64260_get_base(u32 *base)
1575 {
1576         *base = gt64260_base;
1577         return 0;
1578 } /* gt64260_remap_bridge_regs() */
1579
1580 /*
1581  *****************************************************************************
1582  *
1583  *      Exclude PCI config space access to bridge itself
1584  *
1585  *****************************************************************************
1586  */
1587
1588 /*
1589  * gt64260_exclude_pci_device()
1590  *
1591  * This routine causes the PCI subsystem to skip the PCI device in slot 0
1592  * (which is the 64260 itself) unless explicitly allowed.
1593  */
1594 int
1595 gt64260_pci_exclude_device(u8 bus, u8 devfn)
1596 {
1597         struct pci_controller   *hose;
1598
1599         hose = pci_bus_to_hose(bus);
1600
1601         /* Skip slot 0 and 1 on both hoses */
1602         if ((gt64260_pci_exclude_bridge == TRUE) &&
1603             (PCI_SLOT(devfn) == 0) &&
1604             (hose->first_busno == bus)) {
1605
1606                 return PCIBIOS_DEVICE_NOT_FOUND;
1607         }
1608         else {
1609                 return PCIBIOS_SUCCESSFUL;
1610         }
1611 } /* gt64260_pci_exclude_device() */
1612
1613 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
1614
1615 /*
1616  * gt64260_putc()
1617  *
1618  * Dump a character out the MPSC port for gt64260_mpsc_progress
1619  * this assumes the baud rate has already been set up and the
1620  * MPSC initialized by the bootloader or firmware.
1621  */
1622
1623 static inline void
1624 gt_putc(char c){
1625         mb();
1626         gt_write(GT64260_MPSC_0_CHR_1, c);
1627         mb();
1628         gt_write(GT64260_MPSC_0_CHR_2, 0x200);
1629         mb();
1630
1631         udelay(10000);
1632 }
1633
1634 void
1635 puthex(unsigned long val){
1636
1637         int i;
1638
1639         for (i = 7;  i >= 0;  i--) {
1640                 gt_putc("0123456789ABCDEF"[(val>>28) & 0x0f]);
1641                 val <<= 4;
1642         }
1643         gt_putc('\r');
1644         gt_putc('\n');
1645
1646 }
1647
1648
1649 void
1650 gt64260_mpsc_progress(char *s, unsigned short hex){
1651         /* spit stuff out the 64260 mpsc */
1652
1653         volatile char   c;
1654         while ((c = *s++) != 0){
1655                 gt_putc(c);
1656                 if ( c == '\n' ) gt_putc('\r');
1657         }
1658         gt_putc('\n');
1659         gt_putc('\r');
1660
1661         return;
1662 }
1663
1664 #endif /* CONFIG_DEBUG_TEXT */