2 * arch/ppc/syslib/gt64260_pic.c
4 * Interrupt controller support for Galileo's GT64260.
6 * Author: Chris Zankel <source@mvista.com>
7 * Modified by: Mark A. Greer <mgreer@mvista.com>
9 * Based on sources from Rabeeh Khoury / Galileo Technology
11 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
18 * This file contains the specific functions to support the GT64260
19 * interrupt controller.
21 * The GT64260 has two main interrupt registers (high and low) that
22 * summarizes the interrupts generated by the units of the GT64260.
23 * Each bit is assigned to an interrupt number, where the low register
24 * are assigned from IRQ0 to IRQ31 and the high cause register
26 * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
28 * get_irq() returns the lowest interrupt number that is currently asserted.
31 * - This driver does not initialize the GPP when used as an interrupt
35 #include <linux/stddef.h>
36 #include <linux/init.h>
37 #include <linux/sched.h>
38 #include <linux/signal.h>
39 #include <linux/stddef.h>
40 #include <linux/delay.h>
41 #include <linux/irq.h>
44 #include <asm/system.h>
47 #include <asm/mv64x60.h>
50 /* ========================== forward declaration ========================== */
52 static void gt64260_unmask_irq(unsigned int);
53 static void gt64260_mask_irq(unsigned int);
55 /* ========================== local declarations =========================== */
57 struct hw_interrupt_type gt64260_pic = {
58 " GT64260_PIC ", /* typename */
61 gt64260_unmask_irq, /* enable */
62 gt64260_mask_irq, /* disable */
63 gt64260_mask_irq, /* ack */
65 NULL /* set_affinity */
68 u32 gt64260_irq_base = 0; /* GT64260 handles the next 96 IRQs from here */
70 static mv64x60_handle_t base_bh;
71 static mv64x60_handle_t ic_bh;
75 * This function initializes the interrupt controller. It assigns
76 * all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller.
88 * We register all GPP inputs as interrupt source, but disable them.
92 gt64260_init_irq(void)
97 /* XXXX extract reg base, irq base from ocp */
98 /* XXXX rewrite read/write macros to not use 'bh'?? */
99 /* XXXX Have to use ocp b/c can pass arg to this routine */
101 if ( ppc_md.progress ) ppc_md.progress("gt64260_init_irq: enter", 0x0);
103 if ((def = ocp_get_one_device(OCP_VENDOR_MARVELL, OCP_FUNC_HB,
104 OCP_ANY_INDEX)) == NULL) {
108 base_bh.v_base = (u32)ioremap(def->paddr, 0x10000); /* XXXX */
110 if ((def = ocp_get_one_device(OCP_VENDOR_MARVELL, OCP_FUNC_PIC,
111 OCP_ANY_INDEX)) == NULL) {
115 ic_bh.v_base = (u32)ioremap(def->paddr, 0x1000); /* XXXX */
117 ppc_cached_irq_mask[0] = 0;
118 ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
119 ppc_cached_irq_mask[2] = 0;
121 /* disable all interrupts and clear current interrupts */
122 mv64x60_write(&base_bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
123 mv64x60_write(&base_bh, MV64x60_GPP_INTR_CAUSE,0);
124 mv64x60_write(&ic_bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
125 mv64x60_write(&ic_bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
127 /* use the gt64260 for all (possible) interrupt sources */
128 for( i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++ ) {
129 irq_desc[i].handler = >64260_pic;
132 if ( ppc_md.progress ) ppc_md.progress("gt64260_init_irq: exit", 0x0);
139 * This function returns the lowest interrupt number of all interrupts that
140 * are currently asserted.
143 * struct pt_regs* not used
145 * Output Variable(s):
149 * int <interrupt number> or -2 (bogus interrupt)
153 gt64260_get_irq(struct pt_regs *regs)
158 irq = mv64x60_read(&ic_bh, GT64260_IC_MAIN_CAUSE_LO);
159 irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
162 irq = mv64x60_read(&ic_bh, GT64260_IC_MAIN_CAUSE_HI);
163 irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
166 irq = -2; /* bogus interrupt, should never happen */
169 irq_gpp = mv64x60_read(&base_bh, MV64x60_GPP_INTR_CAUSE);
170 irq_gpp = __ilog2(irq_gpp &
171 ppc_cached_irq_mask[2]);
177 mv64x60_write(&base_bh, MV64x60_GPP_INTR_CAUSE, ~(1<<(irq-64)));
188 return( gt64260_irq_base + irq );
192 /* gt64260_unmask_irq()
194 * This function enables an interrupt.
197 * unsigned int interrupt number (IRQ0...IRQ95).
199 * Output Variable(s):
207 gt64260_unmask_irq(unsigned int irq)
210 printk("XXXX: *** unmask irq: %d\n", irq);
212 irq -= gt64260_irq_base;
216 mv64x60_write(&base_bh, MV64x60_GPP_INTR_MASK,
217 ppc_cached_irq_mask[2] |= (1<<(irq-64)));
219 /* mask high interrupt register */
220 mv64x60_write(&ic_bh, GT64260_IC_CPU_INTR_MASK_HI,
221 ppc_cached_irq_mask[1] |= (1<<(irq-32)));
224 /* mask low interrupt register */
225 mv64x60_write(&ic_bh, GT64260_IC_CPU_INTR_MASK_LO,
226 ppc_cached_irq_mask[0] |= (1<<irq));
231 /* gt64260_mask_irq()
233 * This funktion disables the requested interrupt.
236 * unsigned int interrupt number (IRQ0...IRQ95).
238 * Output Variable(s):
246 gt64260_mask_irq(unsigned int irq)
249 printk("XXXX: *** mask irq: %d\n", irq);
251 irq -= gt64260_irq_base;
255 mv64x60_write(&base_bh, MV64x60_GPP_INTR_MASK,
256 ppc_cached_irq_mask[2] &= ~(1<<(irq-64)));
258 /* mask high interrupt register */
259 mv64x60_write(&ic_bh, GT64260_IC_CPU_INTR_MASK_HI,
260 ppc_cached_irq_mask[1] &= ~(1<<(irq-32)));
263 /* mask low interrupt register */
264 mv64x60_write(&ic_bh, GT64260_IC_CPU_INTR_MASK_LO,
265 ppc_cached_irq_mask[0] &= ~(1<<irq));
268 if (irq == 36) { /* Seems necessary for SDMA interrupts */