arch/ppc/syslib/mpc10x_common.c

   1 /*
   2  * arch/ppc/syslib/mpc10x_common.c
   3  *
   4  * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
   5  * Mem ctlr, EPIC, etc.
   6  *
   7  * Author: Mark A. Greer
   8  *         mgreer@mvista.com
   9  *
  10  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 /*
  17  * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/pci.h>
  23 #include <linux/slab.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/machdep.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/open_pic.h>
  32 #include <asm/mpc10x.h>
  33 #include <asm/ocp.h>
  34
  35 /* The OCP structure is fixed by code below, before OCP initialises.
  36    paddr depends on where the board places the EUMB.
  37     - fixed in mpc10x_bridge_init().
  38    irq depends on two things:
  39     > does the board use the EPIC at all? (PCORE does not).
  40     > is the EPIC in serial or parallel mode?
  41     - fixed in mpc10x_set_openpic().
  42 */
  43
  44 #ifdef CONFIG_MPC10X_OPENPIC
  45 #ifdef CONFIG_EPIC_SERIAL_MODE
  46 #define EPIC_IRQ_BASE 16
  47 #else
  48 #define EPIC_IRQ_BASE 5
  49 #endif
  50 #define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
  51 #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
  52 #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
  53 #else
  54 #define MPC10X_I2C_IRQ OCP_IRQ_NA
  55 #define MPC10X_DMA0_IRQ OCP_IRQ_NA
  56 #define MPC10X_DMA1_IRQ OCP_IRQ_NA
  57 #endif
  58
  59
  60 struct ocp_def core_ocp[] = {
  61         { .vendor       = OCP_VENDOR_INVALID
  62         }
  63 };
  64
  65 static struct ocp_fs_i2c_data mpc10x_i2c_data = {
  66         .flags          = 0
  67 };
  68 static struct ocp_def mpc10x_i2c_ocp = {
  69         .vendor         = OCP_VENDOR_MOTOROLA,
  70         .function       = OCP_FUNC_IIC,
  71         .index          = 0,
  72         .irq            = MPC10X_I2C_IRQ,
  73         .additions      = &mpc10x_i2c_data
  74 };
  75
  76 static struct ocp_def mpc10x_dma_ocp[2] = {
  77 {       .vendor         = OCP_VENDOR_MOTOROLA,
  78         .function       = OCP_FUNC_DMA,
  79         .index          = 0,
  80         .irq            = MPC10X_DMA0_IRQ
  81 },
  82 {       .vendor         = OCP_VENDOR_MOTOROLA,
  83         .function       = OCP_FUNC_DMA,
  84         .index          = 1,
  85         .irq            = MPC10X_DMA1_IRQ }
  86 };
  87
  88 /* Set resources to match bridge memory map */
  89 void __init
  90 mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
  91 {
  92
  93         switch (map) {
  94                 case MPC10X_MEM_MAP_A:
  95                         pci_init_resource(&hose->io_resource,
  96                                         0x00000000,
  97                                         0x3f7fffff,
  98                                         IORESOURCE_IO,
  99                                         "PCI host bridge");
 100
 101                         pci_init_resource (&hose->mem_resources[0],
 102                                         0xc0000000,
 103                                         0xfeffffff,
 104                                         IORESOURCE_MEM,
 105                                         "PCI host bridge");
 106                         break;
 107                 case MPC10X_MEM_MAP_B:
 108                         pci_init_resource(&hose->io_resource,
 109                                         0x00000000,
 110                                         0x00bfffff,
 111                                         IORESOURCE_IO,
 112                                         "PCI host bridge");
 113
 114                         pci_init_resource (&hose->mem_resources[0],
 115                                         0x80000000,
 116                                         0xfcffffff,
 117                                         IORESOURCE_MEM,
 118                                         "PCI host bridge");
 119                         break;
 120                 default:
 121                         printk("mpc10x_bridge_set_resources: "
 122                                         "Invalid map specified\n");
 123                         if (ppc_md.progress)
 124                                 ppc_md.progress("mpc10x:exit1", 0x100);
 125         }
 126 }
 127 /*
 128  * Do some initialization and put the EUMB registers at the specified address
 129  * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
 130  *
 131  * The EPIC is not on the 106, only the 8240 and 107.
 132  */
 133 int __init
 134 mpc10x_bridge_init(struct pci_controller *hose,
 135                    uint current_map,
 136                    uint new_map,
 137                    uint phys_eumb_base)
 138 {
 139         int     host_bridge, picr1, picr1_bit;
 140         ulong   pci_config_addr, pci_config_data;
 141         u_char  pir, byte;
 142
 143         if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100);
 144
 145         /* Set up for current map so we can get at config regs */
 146         switch (current_map) {
 147                 case MPC10X_MEM_MAP_A:
 148                         setup_indirect_pci(hose,
 149                                            MPC10X_MAPA_CNFG_ADDR,
 150                                            MPC10X_MAPA_CNFG_DATA);
 151                         break;
 152                 case MPC10X_MEM_MAP_B:
 153                         setup_indirect_pci(hose,
 154                                            MPC10X_MAPB_CNFG_ADDR,
 155                                            MPC10X_MAPB_CNFG_DATA);
 156                         break;
 157                 default:
 158                         printk("mpc10x_bridge_init: %s\n",
 159                                 "Invalid current map specified");
 160                         if (ppc_md.progress)
 161                                 ppc_md.progress("mpc10x:exit1", 0x100);
 162                         return -1;
 163         }
 164
 165         /* Make sure it's a supported bridge */
 166         early_read_config_dword(hose,
 167                                 0,
 168                                 PCI_DEVFN(0,0),
 169                                 PCI_VENDOR_ID,
 170                                 &host_bridge);
 171
 172         switch (host_bridge) {
 173                 case MPC10X_BRIDGE_106:
 174                 case MPC10X_BRIDGE_8240:
 175                 case MPC10X_BRIDGE_107:
 176                 case MPC10X_BRIDGE_8245:
 177                         break;
 178                 default:
 179                         if (ppc_md.progress)
 180                                 ppc_md.progress("mpc10x:exit2", 0x100);
 181                         return -1;
 182         }
 183
 184         switch (new_map) {
 185                 case MPC10X_MEM_MAP_A:
 186                         MPC10X_SETUP_HOSE(hose, A);
 187                         pci_config_addr = MPC10X_MAPA_CNFG_ADDR;
 188                         pci_config_data = MPC10X_MAPA_CNFG_DATA;
 189                         picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A;
 190                         break;
 191                 case MPC10X_MEM_MAP_B:
 192                         MPC10X_SETUP_HOSE(hose, B);
 193                         pci_config_addr = MPC10X_MAPB_CNFG_ADDR;
 194                         pci_config_data = MPC10X_MAPB_CNFG_DATA;
 195                         picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B;
 196                         break;
 197                 default:
 198                         printk("mpc10x_bridge_init: %s\n",
 199                                 "Invalid new map specified");
 200                         if (ppc_md.progress)
 201                                 ppc_md.progress("mpc10x:exit3", 0x100);
 202                         return -1;
 203         }
 204
 205         /* Make bridge use the 'new_map', if not already usng it */
 206         if (current_map != new_map) {
 207                 early_read_config_dword(hose,
 208                                         0,
 209                                         PCI_DEVFN(0,0),
 210                                         MPC10X_CFG_PICR1_REG,
 211                                         &picr1);
 212
 213                 picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |
 214                          picr1_bit;
 215
 216                 early_write_config_dword(hose,
 217                                          0,
 218                                          PCI_DEVFN(0,0),
 219                                          MPC10X_CFG_PICR1_REG,
 220                                          picr1);
 221
 222                 asm volatile("sync");
 223
 224                 /* Undo old mappings & map in new cfg data/addr regs */
 225                 iounmap((void *)hose->cfg_addr);
 226                 iounmap((void *)hose->cfg_data);
 227
 228                 setup_indirect_pci(hose,
 229                                    pci_config_addr,
 230                                    pci_config_data);
 231         }
 232
 233         /* Setup resources to match map */
 234         mpc10x_bridge_set_resources(new_map, hose);
 235
 236         /*
 237          * Want processor accesses of 0xFDxxxxxx to be mapped
 238          * to PCI memory space at 0x00000000.  Do not want
 239          * host bridge to respond to PCI memory accesses of
 240          * 0xFDxxxxxx.  Do not want host bridge to respond
 241          * to PCI memory addresses 0xFD000000-0xFDFFFFFF;
 242          * want processor accesses from 0x000A0000-0x000BFFFF
 243          * to be forwarded to system memory.
 244          *
 245          * Only valid if not in agent mode and using MAP B.
 246          */
 247         if (new_map == MPC10X_MEM_MAP_B) {
 248                 early_read_config_byte(hose,
 249                                        0,
 250                                        PCI_DEVFN(0,0),
 251                                        MPC10X_CFG_MAPB_OPTIONS_REG,
 252                                        &byte);
 253
 254                 byte &= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE  |
 255                           MPC10X_CFG_MAPB_OPTIONS_PCICH |
 256                           MPC10X_CFG_MAPB_OPTIONS_PROCCH);
 257
 258                 if (host_bridge != MPC10X_BRIDGE_106) {
 259                         byte |= MPC10X_CFG_MAPB_OPTIONS_CFAE;
 260                 }
 261
 262                 early_write_config_byte(hose,
 263                                         0,
 264                                         PCI_DEVFN(0,0),
 265                                         MPC10X_CFG_MAPB_OPTIONS_REG,
 266                                         byte);
 267         }
 268
 269         if (host_bridge != MPC10X_BRIDGE_106) {
 270                 early_read_config_byte(hose,
 271                                        0,
 272                                        PCI_DEVFN(0,0),
 273                                        MPC10X_CFG_PIR_REG,
 274                                        &pir);
 275
 276                 if (pir != MPC10X_CFG_PIR_HOST_BRIDGE) {
 277                         printk("Host bridge in Agent mode\n");
 278                         /* Read or Set LMBAR & PCSRBAR? */
 279                 }
 280
 281                 /* Set base addr of the 8240/107 EUMB.  */
 282                 early_write_config_dword(hose,
 283                                          0,
 284                                          PCI_DEVFN(0,0),
 285                                          MPC10X_CFG_EUMBBAR,
 286                                          phys_eumb_base);
 287 #ifdef CONFIG_MPC10X_OPENPIC
 288                 /* Map EPIC register part of EUMB into vitual memory  - PCORE
 289                    uses an i8259 instead of EPIC. */
 290                 OpenPIC_Addr =
 291                         ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
 292                                 MPC10X_EUMB_EPIC_SIZE);
 293 #endif
 294                 mpc10x_i2c_ocp.paddr = phys_eumb_base + MPC10X_EUMB_I2C_OFFSET;
 295                 ocp_add_one_device(&mpc10x_i2c_ocp);
 296                 mpc10x_dma_ocp[0].paddr = phys_eumb_base +
 297                                         MPC10X_EUMB_DMA_OFFSET + 0x100;
 298                 ocp_add_one_device(&mpc10x_dma_ocp[0]);
 299                 mpc10x_dma_ocp[1].paddr = phys_eumb_base +
 300                                         MPC10X_EUMB_DMA_OFFSET + 0x200;
 301                 ocp_add_one_device(&mpc10x_dma_ocp[1]);
 302         }
 303
 304 #ifdef CONFIG_MPC10X_STORE_GATHERING
 305         mpc10x_enable_store_gathering(hose);
 306 #else
 307         mpc10x_disable_store_gathering(hose);
 308 #endif
 309
 310         if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100);
 311         return 0;
 312 }
 313
 314 /*
 315  * Need to make our own PCI config space access macros because
 316  * mpc10x_get_mem_size() is called before the data structures are set up for
 317  * the 'early_xxx' and 'indirect_xxx' routines to work.
 318  * Assumes bus 0.
 319  */
 320 #define MPC10X_CFG_read(val, addr, type, op)    *val = op((type)(addr))
 321 #define MPC10X_CFG_write(val, addr, type, op)   op((type *)(addr), (val))
 322
 323 #define MPC10X_PCI_OP(rw, size, type, op, mask)                         \
 324 static void                                                             \
 325 mpc10x_##rw##_config_##size(uint *cfg_addr, uint *cfg_data, int devfn, int offset, type val) \
 326 {                                                                       \
 327         out_be32(cfg_addr,                                              \
 328                  ((offset & 0xfc) << 24) | (devfn << 16)                \
 329                  | (0 << 8) | 0x80);                                    \
 330         MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op);     \
 331         return;                                                         \
 332 }
 333
 334 MPC10X_PCI_OP(read,  byte,  u8 *, in_8, 3)
 335 MPC10X_PCI_OP(read,  dword, u32 *, in_le32, 0)
 336 #if 0   /* Not used */
 337 MPC10X_PCI_OP(write, byte,  u8, out_8, 3)
 338 MPC10X_PCI_OP(read,  word,  u16 *, in_le16, 2)
 339 MPC10X_PCI_OP(write, word,  u16, out_le16, 2)
 340 MPC10X_PCI_OP(write, dword, u32, out_le32, 0)
 341 #endif
 342
 343 /*
 344  * Read the memory controller registers to determine the amount of memory in
 345  * the system.  This assumes that the firmware has correctly set up the memory
 346  * controller registers.
 347  */
 348 unsigned long __init
 349 mpc10x_get_mem_size(uint mem_map)
 350 {
 351         uint                    *config_addr, *config_data, val;
 352         ulong                   start, end, total, offset;
 353         int                     i;
 354         u_char                  bank_enables;
 355
 356         switch (mem_map) {
 357                 case MPC10X_MEM_MAP_A:
 358                         config_addr = (uint *)MPC10X_MAPA_CNFG_ADDR;
 359                         config_data = (uint *)MPC10X_MAPA_CNFG_DATA;
 360                         break;
 361                 case MPC10X_MEM_MAP_B:
 362                         config_addr = (uint *)MPC10X_MAPB_CNFG_ADDR;
 363                         config_data = (uint *)MPC10X_MAPB_CNFG_DATA;
 364                         break;
 365                 default:
 366                         return 0;
 367         }
 368
 369         mpc10x_read_config_byte(config_addr,
 370                                 config_data,
 371                                 PCI_DEVFN(0,0),
 372                                 MPC10X_MCTLR_MEM_BANK_ENABLES,
 373                                 &bank_enables);
 374
 375         total = 0;
 376
 377         for (i=0; i<8; i++) {
 378                 if (bank_enables & (1 << i)) {
 379                         offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
 380                         mpc10x_read_config_dword(config_addr,
 381                                                  config_data,
 382                                                  PCI_DEVFN(0,0),
 383                                                  offset,
 384                                                  &val);
 385                         start = (val >> ((i & 3) << 3)) & 0xff;
 386
 387                         offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
 388                         mpc10x_read_config_dword(config_addr,
 389                                                  config_data,
 390                                                  PCI_DEVFN(0,0),
 391                                                  offset,
 392                                                  &val);
 393                         val = (val >> ((i & 3) << 3)) & 0x03;
 394                         start = (val << 28) | (start << 20);
 395
 396                         offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
 397                         mpc10x_read_config_dword(config_addr,
 398                                                  config_data,
 399                                                  PCI_DEVFN(0,0),
 400                                                  offset,
 401                                                  &val);
 402                         end = (val >> ((i & 3) << 3)) & 0xff;
 403
 404                         offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
 405                         mpc10x_read_config_dword(config_addr,
 406                                                  config_data,
 407                                                  PCI_DEVFN(0,0),
 408                                                  offset,
 409                                                  &val);
 410                         val = (val >> ((i & 3) << 3)) & 0x03;
 411                         end = (val << 28) | (end << 20) | 0xfffff;
 412
 413                         total += (end - start + 1);
 414                 }
 415         }
 416
 417         return total;
 418 }
 419
 420 int __init
 421 mpc10x_enable_store_gathering(struct pci_controller *hose)
 422 {
 423         uint picr1;
 424
 425         early_read_config_dword(hose,
 426                                 0,
 427                                 PCI_DEVFN(0,0),
 428                                 MPC10X_CFG_PICR1_REG,
 429                                 &picr1);
 430
 431         picr1 |= MPC10X_CFG_PICR1_ST_GATH_EN;
 432
 433         early_write_config_dword(hose,
 434                                 0,
 435                                 PCI_DEVFN(0,0),
 436                                 MPC10X_CFG_PICR1_REG,
 437                                 picr1);
 438
 439         return 0;
 440 }
 441
 442 int __init
 443 mpc10x_disable_store_gathering(struct pci_controller *hose)
 444 {
 445         uint picr1;
 446
 447         early_read_config_dword(hose,
 448                                 0,
 449                                 PCI_DEVFN(0,0),
 450                                 MPC10X_CFG_PICR1_REG,
 451                                 &picr1);
 452
 453         picr1 &= ~MPC10X_CFG_PICR1_ST_GATH_EN;
 454
 455         early_write_config_dword(hose,
 456                                 0,
 457                                 PCI_DEVFN(0,0),
 458                                 MPC10X_CFG_PICR1_REG,
 459                                 picr1);
 460
 461         return 0;
 462 }
 463
 464 #ifdef CONFIG_MPC10X_OPENPIC
 465 void __init mpc10x_set_openpic(void)
 466 {
 467         /* Map external IRQs */
 468         openpic_set_sources(0, EPIC_IRQ_BASE, OpenPIC_Addr + 0x10200);
 469         /* Skip reserved space and map i2c and DMA Ch[01] */
 470         openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
 471         /* Skip reserved space and map Message Unit Interrupt (I2O) */
 472         openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
 473
 474         openpic_init(NUM_8259_INTERRUPTS);
 475 }
 476 #endif