arch/ppc/syslib/open_pic.c

   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/errno.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/signal.h>
  22 #include <asm/io.h>
  23 #include <asm/irq.h>
  24 #include <asm/prom.h>
  25 #include <asm/sections.h>
  26 #include <asm/open_pic.h>
  27 #include <asm/i8259.h>
  28
  29 #include "open_pic_defs.h"
  30
  31 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
  32 #define OPENPIC_BIG_ENDIAN
  33 #endif
  34
  35 void __iomem *OpenPIC_Addr;
  36 static volatile struct OpenPIC __iomem *OpenPIC = NULL;
  37
  38 /*
  39  * We define OpenPIC_InitSenses table thusly:
  40  * bit 0x1: sense, 0 for edge and 1 for level.
  41  * bit 0x2: polarity, 0 for negative, 1 for positive.
  42  */
  43 u_int OpenPIC_NumInitSenses __initdata = 0;
  44 u_char *OpenPIC_InitSenses __initdata = NULL;
  45 extern int use_of_interrupt_tree;
  46
  47 static u_int NumProcessors;
  48 static u_int NumSources;
  49 static int open_pic_irq_offset;
  50 static volatile OpenPIC_Source __iomem *ISR[NR_IRQS];
  51 static int openpic_cascade_irq = -1;
  52 static int (*openpic_cascade_fn)(struct pt_regs *);
  53
  54 /* Global Operations */
  55 static void openpic_disable_8259_pass_through(void);
  56 static void openpic_set_spurious(u_int vector);
  57
  58 #ifdef CONFIG_SMP
  59 /* Interprocessor Interrupts */
  60 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  61 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
  62 #endif
  63
  64 /* Timer Interrupts */
  65 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  66 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
  67
  68 /* Interrupt Sources */
  69 static void openpic_enable_irq(u_int irq);
  70 static void openpic_disable_irq(u_int irq);
  71 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  72                             int is_level);
  73 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
  74
  75 /*
  76  * These functions are not used but the code is kept here
  77  * for completeness and future reference.
  78  */
  79 #ifdef notused
  80 static void openpic_enable_8259_pass_through(void);
  81 static u_int openpic_get_spurious(void);
  82 static void openpic_set_sense(u_int irq, int sense);
  83 #endif /* notused */
  84
  85 /*
  86  * Description of the openpic for the higher-level irq code
  87  */
  88 static void openpic_end_irq(unsigned int irq_nr);
  89 static void openpic_ack_irq(unsigned int irq_nr);
  90 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
  91
  92 struct hw_interrupt_type open_pic = {
  93         .typename       = " OpenPIC  ",
  94         .enable         = openpic_enable_irq,
  95         .disable        = openpic_disable_irq,
  96         .ack            = openpic_ack_irq,
  97         .end            = openpic_end_irq,
  98         .set_affinity   = openpic_set_affinity,
  99 };
 100
 101 #ifdef CONFIG_SMP
 102 static void openpic_end_ipi(unsigned int irq_nr);
 103 static void openpic_ack_ipi(unsigned int irq_nr);
 104 static void openpic_enable_ipi(unsigned int irq_nr);
 105 static void openpic_disable_ipi(unsigned int irq_nr);
 106
 107 struct hw_interrupt_type open_pic_ipi = {
 108         .typename       = " OpenPIC  ",
 109         .enable         = openpic_enable_ipi,
 110         .disable        = openpic_disable_ipi,
 111         .ack            = openpic_ack_ipi,
 112         .end            = openpic_end_ipi,
 113 };
 114 #endif /* CONFIG_SMP */
 115
 116 /*
 117  *  Accesses to the current processor's openpic registers
 118  */
 119 #ifdef CONFIG_SMP
 120 #define THIS_CPU                Processor[cpu]
 121 #define DECL_THIS_CPU           int cpu = smp_hw_index[smp_processor_id()]
 122 #define CHECK_THIS_CPU          check_arg_cpu(cpu)
 123 #else
 124 #define THIS_CPU                Processor[0]
 125 #define DECL_THIS_CPU
 126 #define CHECK_THIS_CPU
 127 #endif /* CONFIG_SMP */
 128
 129 #if 1
 130 #define check_arg_ipi(ipi) \
 131     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 132         printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
 133 #define check_arg_timer(timer) \
 134     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 135         printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
 136 #define check_arg_vec(vec) \
 137     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 138         printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
 139 #define check_arg_pri(pri) \
 140     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 141         printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
 142 /*
 143  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 144  * data has probably been corrupted and we're going to panic or deadlock later
 145  * anyway --Troy
 146  */
 147 #define check_arg_irq(irq) \
 148     if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
 149         || ISR[irq - open_pic_irq_offset] == 0) { \
 150       printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
 151       dump_stack(); }
 152 #define check_arg_cpu(cpu) \
 153     if (cpu < 0 || cpu >= NumProcessors){ \
 154         printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
 155         dump_stack(); }
 156 #else
 157 #define check_arg_ipi(ipi)      do {} while (0)
 158 #define check_arg_timer(timer)  do {} while (0)
 159 #define check_arg_vec(vec)      do {} while (0)
 160 #define check_arg_pri(pri)      do {} while (0)
 161 #define check_arg_irq(irq)      do {} while (0)
 162 #define check_arg_cpu(cpu)      do {} while (0)
 163 #endif
 164
 165 u_int openpic_read(volatile u_int __iomem *addr)
 166 {
 167         u_int val;
 168
 169 #ifdef OPENPIC_BIG_ENDIAN
 170         val = in_be32(addr);
 171 #else
 172         val = in_le32(addr);
 173 #endif
 174         return val;
 175 }
 176
 177 static inline void openpic_write(volatile u_int __iomem *addr, u_int val)
 178 {
 179 #ifdef OPENPIC_BIG_ENDIAN
 180         out_be32(addr, val);
 181 #else
 182         out_le32(addr, val);
 183 #endif
 184 }
 185
 186 static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask)
 187 {
 188         u_int val = openpic_read(addr);
 189         return val & mask;
 190 }
 191
 192 inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask,
 193                                u_int field)
 194 {
 195         u_int val = openpic_read(addr);
 196         openpic_write(addr, (val & ~mask) | (field & mask));
 197 }
 198
 199 static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask)
 200 {
 201         openpic_writefield(addr, mask, 0);
 202 }
 203
 204 static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask)
 205 {
 206         openpic_writefield(addr, mask, mask);
 207 }
 208
 209 static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,
 210                                     u_int field)
 211 {
 212         openpic_setfield(addr, OPENPIC_MASK);
 213         while (openpic_read(addr) & OPENPIC_ACTIVITY);
 214         openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 215 }
 216
 217 #ifdef CONFIG_SMP
 218 /* yes this is right ... bug, feature, you decide! -- tgall */
 219 u_int openpic_read_IPI(volatile u_int __iomem * addr)
 220 {
 221          u_int val = 0;
 222 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
 223         val = in_be32(addr);
 224 #else
 225         val = in_le32(addr);
 226 #endif
 227         return val;
 228 }
 229
 230 /* because of the power3 be / le above, this is needed */
 231 inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field)
 232 {
 233         u_int  val = openpic_read_IPI(addr);
 234         openpic_write(addr, (val & ~mask) | (field & mask));
 235 }
 236
 237 static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask)
 238 {
 239         openpic_writefield_IPI(addr, mask, 0);
 240 }
 241
 242 static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask)
 243 {
 244         openpic_writefield_IPI(addr, mask, mask);
 245 }
 246
 247 static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field)
 248 {
 249         openpic_setfield_IPI(addr, OPENPIC_MASK);
 250
 251         /* wait until it's not in use */
 252         /* BenH: Is this code really enough ? I would rather check the result
 253          *       and eventually retry ...
 254          */
 255         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
 256
 257         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 258 }
 259 #endif /* CONFIG_SMP */
 260
 261 #ifdef CONFIG_EPIC_SERIAL_MODE
 262 /* On platforms that may use EPIC serial mode, the default is enabled. */
 263 int epic_serial_mode = 1;
 264
 265 static void __init openpic_eicr_set_clk(u_int clkval)
 266 {
 267         openpic_writefield(&OpenPIC->Global.Global_Configuration1,
 268                         OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
 269 }
 270
 271 static void __init openpic_enable_sie(void)
 272 {
 273         openpic_setfield(&OpenPIC->Global.Global_Configuration1,
 274                         OPENPIC_EICR_SIE);
 275 }
 276 #endif
 277
 278 #if defined(CONFIG_EPIC_SERIAL_MODE)
 279 static void openpic_reset(void)
 280 {
 281         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 282                          OPENPIC_CONFIG_RESET);
 283         while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
 284                                  OPENPIC_CONFIG_RESET))
 285                 mb();
 286 }
 287 #endif
 288
 289 void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR)
 290 {
 291         volatile OpenPIC_Source __iomem *src = first_ISR;
 292         int i, last_irq;
 293
 294         last_irq = first_irq + num_irqs;
 295         if (last_irq > NumSources)
 296                 NumSources = last_irq;
 297         if (src == 0)
 298                 src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq];
 299         for (i = first_irq; i < last_irq; ++i, ++src)
 300                 ISR[i] = src;
 301 }
 302
 303 /*
 304  * The `offset' parameter defines where the interrupts handled by the
 305  * OpenPIC start in the space of interrupt numbers that the kernel knows
 306  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 307  * kernel's interrupt numbering scheme.
 308  * We assume there is only one OpenPIC.
 309  */
 310 void __init openpic_init(int offset)
 311 {
 312         u_int t, i;
 313         u_int timerfreq;
 314         const char *version;
 315
 316         if (!OpenPIC_Addr) {
 317                 printk("No OpenPIC found !\n");
 318                 return;
 319         }
 320         OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr;
 321
 322 #ifdef CONFIG_EPIC_SERIAL_MODE
 323         /* Have to start from ground zero.
 324         */
 325         openpic_reset();
 326 #endif
 327
 328         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 329
 330         t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
 331         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 332         case 1:
 333                 version = "1.0";
 334                 break;
 335         case 2:
 336                 version = "1.2";
 337                 break;
 338         case 3:
 339                 version = "1.3";
 340                 break;
 341         default:
 342                 version = "?";
 343                 break;
 344         }
 345         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 346                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 347         if (NumSources == 0)
 348                 openpic_set_sources(0,
 349                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 350                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 351                                     NULL);
 352         printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
 353                version, NumProcessors, NumSources, OpenPIC);
 354         timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
 355         if (timerfreq)
 356                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 357                        timerfreq / 1000000, timerfreq % 1000000);
 358
 359         open_pic_irq_offset = offset;
 360
 361         /* Initialize timer interrupts */
 362         if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
 363         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 364                 /* Disabled, Priority 0 */
 365                 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
 366                 /* No processor */
 367                 openpic_maptimer(i, CPU_MASK_NONE);
 368         }
 369
 370 #ifdef CONFIG_SMP
 371         /* Initialize IPI interrupts */
 372         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
 373         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
 374                 /* Disabled, Priority 10..13 */
 375                 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
 376                 /* IPIs are per-CPU */
 377                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
 378                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
 379         }
 380 #endif
 381
 382         /* Initialize external interrupts */
 383         if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
 384
 385         openpic_set_priority(0xf);
 386
 387         /* Init all external sources, including possibly the cascade. */
 388         for (i = 0; i < NumSources; i++) {
 389                 int sense;
 390
 391                 if (ISR[i] == 0)
 392                         continue;
 393
 394                 /* the bootloader may have left it enabled (bad !) */
 395                 openpic_disable_irq(i+offset);
 396
 397                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 398                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 399
 400                 if (sense & IRQ_SENSE_MASK)
 401                         irq_desc[i+offset].status = IRQ_LEVEL;
 402
 403                 /* Enabled, Priority 8 */
 404                 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
 405                                 (sense & IRQ_SENSE_MASK));
 406                 /* Processor 0 */
 407                 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
 408         }
 409
 410         /* Init descriptors */
 411         for (i = offset; i < NumSources + offset; i++)
 412                 irq_desc[i].handler = &open_pic;
 413
 414         /* Initialize the spurious interrupt */
 415         if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
 416         openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
 417         openpic_disable_8259_pass_through();
 418 #ifdef CONFIG_EPIC_SERIAL_MODE
 419         if (epic_serial_mode) {
 420                 openpic_eicr_set_clk(7);        /* Slowest value until we know better */
 421                 openpic_enable_sie();
 422         }
 423 #endif
 424         openpic_set_priority(0);
 425
 426         if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
 427 }
 428
 429 #ifdef notused
 430 static void openpic_enable_8259_pass_through(void)
 431 {
 432         openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
 433                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 434 }
 435 #endif /* notused */
 436
 437 static void openpic_disable_8259_pass_through(void)
 438 {
 439         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 440                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 441 }
 442
 443 /*
 444  *  Find out the current interrupt
 445  */
 446 u_int openpic_irq(void)
 447 {
 448         u_int vec;
 449         DECL_THIS_CPU;
 450
 451         CHECK_THIS_CPU;
 452         vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
 453                                 OPENPIC_VECTOR_MASK);
 454         return vec;
 455 }
 456
 457 void openpic_eoi(void)
 458 {
 459         DECL_THIS_CPU;
 460
 461         CHECK_THIS_CPU;
 462         openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
 463         /* Handle PCI write posting */
 464         (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
 465 }
 466
 467 u_int openpic_get_priority(void)
 468 {
 469         DECL_THIS_CPU;
 470
 471         CHECK_THIS_CPU;
 472         return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 473                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 474 }
 475
 476 void openpic_set_priority(u_int pri)
 477 {
 478         DECL_THIS_CPU;
 479
 480         CHECK_THIS_CPU;
 481         check_arg_pri(pri);
 482         openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 483                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 484 }
 485
 486 /*
 487  *  Get/set the spurious vector
 488  */
 489 #ifdef notused
 490 static u_int openpic_get_spurious(void)
 491 {
 492         return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
 493                                  OPENPIC_VECTOR_MASK);
 494 }
 495 #endif /* notused */
 496
 497 static void openpic_set_spurious(u_int vec)
 498 {
 499         check_arg_vec(vec);
 500         openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 501                            vec);
 502 }
 503
 504 #ifdef CONFIG_SMP
 505 /*
 506  * Convert a cpu mask from logical to physical cpu numbers.
 507  */
 508 static inline cpumask_t physmask(cpumask_t cpumask)
 509 {
 510         int i;
 511         cpumask_t mask = CPU_MASK_NONE;
 512
 513         cpus_and(cpumask, cpu_online_map, cpumask);
 514
 515         for (i = 0; i < NR_CPUS; i++)
 516                 if (cpu_isset(i, cpumask))
 517                         cpu_set(smp_hw_index[i], mask);
 518
 519         return mask;
 520 }
 521 #else
 522 #define physmask(cpumask)       (cpumask)
 523 #endif
 524
 525 void openpic_reset_processor_phys(u_int mask)
 526 {
 527         openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
 528 }
 529
 530 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
 531 static DEFINE_SPINLOCK(openpic_setup_lock);
 532 #endif
 533
 534 #ifdef CONFIG_SMP
 535 /*
 536  *  Initialize an interprocessor interrupt (and disable it)
 537  *
 538  *  ipi: OpenPIC interprocessor interrupt number
 539  *  pri: interrupt source priority
 540  *  vec: the vector it will produce
 541  */
 542 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
 543 {
 544         check_arg_ipi(ipi);
 545         check_arg_pri(pri);
 546         check_arg_vec(vec);
 547         openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
 548                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 549                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 550 }
 551
 552 /*
 553  *  Send an IPI to one or more CPUs
 554  *
 555  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
 556  *  and not a system-wide interrupt number
 557  */
 558 void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
 559 {
 560         DECL_THIS_CPU;
 561
 562         CHECK_THIS_CPU;
 563         check_arg_ipi(ipi);
 564         openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
 565                       cpus_addr(physmask(cpumask))[0]);
 566 }
 567
 568 void openpic_request_IPIs(void)
 569 {
 570         int i;
 571
 572         /*
 573          * Make sure this matches what is defined in smp.c for
 574          * smp_message_{pass|recv}() or what shows up in
 575          * /proc/interrupts will be wrong!!! --Troy */
 576
 577         if (OpenPIC == NULL)
 578                 return;
 579
 580         /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 581         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
 582                     openpic_ipi_action, SA_INTERRUPT,
 583                     "IPI0 (call function)", NULL);
 584         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
 585                     openpic_ipi_action, SA_INTERRUPT,
 586                     "IPI1 (reschedule)", NULL);
 587         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
 588                     openpic_ipi_action, SA_INTERRUPT,
 589                     "IPI2 (invalidate tlb)", NULL);
 590         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
 591                     openpic_ipi_action, SA_INTERRUPT,
 592                     "IPI3 (xmon break)", NULL);
 593
 594         for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
 595                 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
 596 }
 597
 598 /*
 599  * Do per-cpu setup for SMP systems.
 600  *
 601  * Get IPI's working and start taking interrupts.
 602  *   -- Cort
 603  */
 604
 605 void __devinit do_openpic_setup_cpu(void)
 606 {
 607 #ifdef CONFIG_IRQ_ALL_CPUS
 608         int i;
 609         cpumask_t msk = CPU_MASK_NONE;
 610 #endif
 611         spin_lock(&openpic_setup_lock);
 612
 613 #ifdef CONFIG_IRQ_ALL_CPUS
 614         cpu_set(smp_hw_index[smp_processor_id()], msk);
 615
 616         /* let the openpic know we want intrs. default affinity
 617          * is 0xffffffff until changed via /proc
 618          * That's how it's done on x86. If we want it differently, then
 619          * we should make sure we also change the default values of irq_affinity
 620          * in irq.c.
 621          */
 622         for (i = 0; i < NumSources; i++)
 623                 openpic_mapirq(i, msk, CPU_MASK_ALL);
 624 #endif /* CONFIG_IRQ_ALL_CPUS */
 625         openpic_set_priority(0);
 626
 627         spin_unlock(&openpic_setup_lock);
 628 }
 629 #endif /* CONFIG_SMP */
 630
 631 /*
 632  *  Initialize a timer interrupt (and disable it)
 633  *
 634  *  timer: OpenPIC timer number
 635  *  pri: interrupt source priority
 636  *  vec: the vector it will produce
 637  */
 638 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
 639 {
 640         check_arg_timer(timer);
 641         check_arg_pri(pri);
 642         check_arg_vec(vec);
 643         openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
 644                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 645                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 646 }
 647
 648 /*
 649  *  Map a timer interrupt to one or more CPUs
 650  */
 651 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
 652 {
 653         cpumask_t phys = physmask(cpumask);
 654         check_arg_timer(timer);
 655         openpic_write(&OpenPIC->Global.Timer[timer].Destination,
 656                       cpus_addr(phys)[0]);
 657 }
 658
 659 /*
 660  * Initalize the interrupt source which will generate an NMI.
 661  * This raises the interrupt's priority from 8 to 9.
 662  *
 663  * irq: The logical IRQ which generates an NMI.
 664  */
 665 void __init
 666 openpic_init_nmi_irq(u_int irq)
 667 {
 668         check_arg_irq(irq);
 669         openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
 670                                 OPENPIC_PRIORITY_MASK,
 671                                 9 << OPENPIC_PRIORITY_SHIFT);
 672 }
 673
 674 /*
 675  *
 676  * All functions below take an offset'ed irq argument
 677  *
 678  */
 679
 680 /*
 681  * Hookup a cascade to the OpenPIC.
 682  */
 683
 684 static struct irqaction openpic_cascade_irqaction = {
 685         .handler = no_action,
 686         .flags = SA_INTERRUPT,
 687         .mask = CPU_MASK_NONE,
 688 };
 689
 690 void __init
 691 openpic_hookup_cascade(u_int irq, char *name,
 692         int (*cascade_fn)(struct pt_regs *))
 693 {
 694         openpic_cascade_irq = irq;
 695         openpic_cascade_fn = cascade_fn;
 696
 697         if (setup_irq(irq, &openpic_cascade_irqaction))
 698                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 699                                 irq - open_pic_irq_offset);
 700 }
 701
 702 /*
 703  *  Enable/disable an external interrupt source
 704  *
 705  *  Externally called, irq is an offseted system-wide interrupt number
 706  */
 707 static void openpic_enable_irq(u_int irq)
 708 {
 709         volatile u_int __iomem *vpp;
 710
 711         check_arg_irq(irq);
 712         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 713         openpic_clearfield(vpp, OPENPIC_MASK);
 714         /* make sure mask gets to controller before we return to user */
 715         do {
 716                 mb(); /* sync is probably useless here */
 717         } while (openpic_readfield(vpp, OPENPIC_MASK));
 718 }
 719
 720 static void openpic_disable_irq(u_int irq)
 721 {
 722         volatile u_int __iomem *vpp;
 723         u32 vp;
 724
 725         check_arg_irq(irq);
 726         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 727         openpic_setfield(vpp, OPENPIC_MASK);
 728         /* make sure mask gets to controller before we return to user */
 729         do {
 730                 mb();  /* sync is probably useless here */
 731                 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 732         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 733 }
 734
 735 #ifdef CONFIG_SMP
 736 /*
 737  *  Enable/disable an IPI interrupt source
 738  *
 739  *  Externally called, irq is an offseted system-wide interrupt number
 740  */
 741 void openpic_enable_ipi(u_int irq)
 742 {
 743         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 744         check_arg_ipi(irq);
 745         openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 746
 747 }
 748
 749 void openpic_disable_ipi(u_int irq)
 750 {
 751         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 752         check_arg_ipi(irq);
 753         openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 754 }
 755 #endif
 756
 757 /*
 758  *  Initialize an interrupt source (and disable it!)
 759  *
 760  *  irq: OpenPIC interrupt number
 761  *  pri: interrupt source priority
 762  *  vec: the vector it will produce
 763  *  pol: polarity (1 for positive, 0 for negative)
 764  *  sense: 1 for level, 0 for edge
 765  */
 766 static void __init
 767 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 768 {
 769         openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 770                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 771                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 772                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 773                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 774                                         OPENPIC_POLARITY_NEGATIVE) |
 775                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 776 }
 777
 778 /*
 779  *  Map an interrupt source to one or more CPUs
 780  */
 781 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
 782 {
 783         if (ISR[irq] == 0)
 784                 return;
 785         if (!cpus_empty(keepmask)) {
 786                 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
 787                 cpus_and(irqdest, irqdest, keepmask);
 788                 cpus_or(physmask, physmask, irqdest);
 789         }
 790         openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
 791 }
 792
 793 #ifdef notused
 794 /*
 795  *  Set the sense for an interrupt source (and disable it!)
 796  *
 797  *  sense: 1 for level, 0 for edge
 798  */
 799 static void openpic_set_sense(u_int irq, int sense)
 800 {
 801         if (ISR[irq] != 0)
 802                 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 803                                         OPENPIC_SENSE_LEVEL,
 804                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 805 }
 806 #endif /* notused */
 807
 808 /* No spinlocks, should not be necessary with the OpenPIC
 809  * (1 register = 1 interrupt and we have the desc lock).
 810  */
 811 static void openpic_ack_irq(unsigned int irq_nr)
 812 {
 813 #ifdef __SLOW_VERSION__
 814         openpic_disable_irq(irq_nr);
 815         openpic_eoi();
 816 #else
 817         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 818                 openpic_eoi();
 819 #endif
 820 }
 821
 822 static void openpic_end_irq(unsigned int irq_nr)
 823 {
 824 #ifdef __SLOW_VERSION__
 825         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 826             && irq_desc[irq_nr].action)
 827                 openpic_enable_irq(irq_nr);
 828 #else
 829         if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
 830                 openpic_eoi();
 831 #endif
 832 }
 833
 834 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
 835 {
 836         openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
 837 }
 838
 839 #ifdef CONFIG_SMP
 840 static void openpic_ack_ipi(unsigned int irq_nr)
 841 {
 842         openpic_eoi();
 843 }
 844
 845 static void openpic_end_ipi(unsigned int irq_nr)
 846 {
 847 }
 848
 849 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 850 {
 851         smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
 852         return IRQ_HANDLED;
 853 }
 854
 855 #endif /* CONFIG_SMP */
 856
 857 int
 858 openpic_get_irq(struct pt_regs *regs)
 859 {
 860         int irq = openpic_irq();
 861
 862         /*
 863          * Check for the cascade interrupt and call the cascaded
 864          * interrupt controller function (usually i8259_irq) if so.
 865          * This should move to irq.c eventually.  -- paulus
 866          */
 867         if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
 868                 int cirq = openpic_cascade_fn(regs);
 869
 870                 /* Allow for the cascade being shared with other devices */
 871                 if (cirq != -1) {
 872                         irq = cirq;
 873                         openpic_eoi();
 874                 }
 875         } else if (irq == OPENPIC_VEC_SPURIOUS)
 876                 irq = -1;
 877         return irq;
 878 }
 879
 880 #ifdef CONFIG_SMP
 881 void
 882 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
 883 {
 884         cpumask_t mask = CPU_MASK_ALL;
 885         /* make sure we're sending something that translates to an IPI */
 886         if (msg > 0x3) {
 887                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 888                        smp_processor_id(), msg);
 889                 return;
 890         }
 891         switch (target) {
 892         case MSG_ALL:
 893                 openpic_cause_IPI(msg, mask);
 894                 break;
 895         case MSG_ALL_BUT_SELF:
 896                 cpu_clear(smp_processor_id(), mask);
 897                 openpic_cause_IPI(msg, mask);
 898                 break;
 899         default:
 900                 openpic_cause_IPI(msg, cpumask_of_cpu(target));
 901                 break;
 902         }
 903 }
 904 #endif /* CONFIG_SMP */
 905
 906 #ifdef CONFIG_PM
 907
 908 /*
 909  * We implement the IRQ controller as a sysdev and put it
 910  * to sleep at powerdown stage (the callback is named suspend,
 911  * but it's old semantics, for the Device Model, it's really
 912  * powerdown). The possible problem is that another sysdev that
 913  * happens to be suspend after this one will have interrupts off,
 914  * that may be an issue... For now, this isn't an issue on pmac
 915  * though...
 916  */
 917
 918 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 919 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 920 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 921 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 922 static int openpic_suspend_count;
 923
 924 static void openpic_cached_enable_irq(u_int irq)
 925 {
 926         check_arg_irq(irq);
 927         save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
 928 }
 929
 930 static void openpic_cached_disable_irq(u_int irq)
 931 {
 932         check_arg_irq(irq);
 933         save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
 934 }
 935
 936 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 937  * we need something better to deal with that... Maybe switch to S1 for
 938  * cpufreq changes
 939  */
 940 int openpic_suspend(struct sys_device *sysdev, u32 state)
 941 {
 942         int     i;
 943         unsigned long flags;
 944
 945         spin_lock_irqsave(&openpic_setup_lock, flags);
 946
 947         if (openpic_suspend_count++ > 0) {
 948                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 949                 return 0;
 950         }
 951
 952         openpic_set_priority(0xf);
 953
 954         open_pic.enable = openpic_cached_enable_irq;
 955         open_pic.disable = openpic_cached_disable_irq;
 956
 957         for (i=0; i<NumProcessors; i++) {
 958                 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
 959                 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
 960                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 961         }
 962
 963         for (i=0; i<OPENPIC_NUM_IPI; i++)
 964                 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
 965         for (i=0; i<NumSources; i++) {
 966                 if (ISR[i] == 0)
 967                         continue;
 968                 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 969                 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
 970         }
 971
 972         spin_unlock_irqrestore(&openpic_setup_lock, flags);
 973
 974         return 0;
 975 }
 976
 977 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 978  * we need something better to deal with that... Maybe switch to S1 for
 979  * cpufreq changes
 980  */
 981 int openpic_resume(struct sys_device *sysdev)
 982 {
 983         int             i;
 984         unsigned long   flags;
 985         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 986                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 987                                         OPENPIC_MASK;
 988
 989         spin_lock_irqsave(&openpic_setup_lock, flags);
 990
 991         if ((--openpic_suspend_count) > 0) {
 992                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 993                 return 0;
 994         }
 995
 996         /* OpenPIC sometimes seem to need some time to be fully back up... */
 997         do {
 998                 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
 999         } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
1000                         != OPENPIC_VEC_SPURIOUS);
1001
1002         openpic_disable_8259_pass_through();
1003
1004         for (i=0; i<OPENPIC_NUM_IPI; i++)
1005                 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
1006                               save_ipi_vp[i]);
1007         for (i=0; i<NumSources; i++) {
1008                 if (ISR[i] == 0)
1009                         continue;
1010                 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1011                 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1012                 /* make sure mask gets to controller before we return to user */
1013                 do {
1014                         openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1015                 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1016                          != (save_irq_src_vp[i] & vppmask));
1017         }
1018         for (i=0; i<NumProcessors; i++)
1019                 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1020                               save_cpu_task_pri[i]);
1021
1022         open_pic.enable = openpic_enable_irq;
1023         open_pic.disable = openpic_disable_irq;
1024
1025         openpic_set_priority(0);
1026
1027         spin_unlock_irqrestore(&openpic_setup_lock, flags);
1028
1029         return 0;
1030 }
1031
1032 #endif /* CONFIG_PM */
1033
1034 static struct sysdev_class openpic_sysclass = {
1035         set_kset_name("openpic"),
1036 };
1037
1038 static struct sys_device device_openpic = {
1039         .id             = 0,
1040         .cls            = &openpic_sysclass,
1041 };
1042
1043 static struct sysdev_driver driver_openpic = {
1044 #ifdef CONFIG_PM
1045         .suspend        = &openpic_suspend,
1046         .resume         = &openpic_resume,
1047 #endif /* CONFIG_PM */
1048 };
1049
1050 static int __init init_openpic_sysfs(void)
1051 {
1052         int rc;
1053
1054         if (!OpenPIC_Addr)
1055                 return -ENODEV;
1056         printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1057         rc = sysdev_class_register(&openpic_sysclass);
1058         if (rc) {
1059                 printk(KERN_ERR "Failed registering openpic sys class\n");
1060                 return -ENODEV;
1061         }
1062         rc = sysdev_register(&device_openpic);
1063         if (rc) {
1064                 printk(KERN_ERR "Failed registering openpic sys device\n");
1065                 return -ENODEV;
1066         }
1067         rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1068         if (rc) {
1069                 printk(KERN_ERR "Failed registering openpic sys driver\n");
1070                 return -ENODEV;
1071         }
1072         return 0;
1073 }
1074
1075 subsys_initcall(init_openpic_sysfs);
1076