arch/ppc/syslib/open_pic.c

   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/sysdev.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/signal.h>
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/prom.h>
  24 #include <asm/sections.h>
  25 #include <asm/open_pic.h>
  26 #include <asm/i8259.h>
  27 #include <asm/hardirq.h>
  28
  29 #include "open_pic_defs.h"
  30
  31 #ifdef CONFIG_PRPMC800
  32 #define OPENPIC_BIG_ENDIAN
  33 #endif
  34
  35 void* OpenPIC_Addr;
  36 static volatile struct OpenPIC *OpenPIC = NULL;
  37
  38 /*
  39  * We define OpenPIC_InitSenses table thusly:
  40  * bit 0x1: sense, 0 for edge and 1 for level.
  41  * bit 0x2: polarity, 0 for negative, 1 for positive.
  42  */
  43 u_int OpenPIC_NumInitSenses __initdata = 0;
  44 u_char *OpenPIC_InitSenses __initdata = NULL;
  45 extern int use_of_interrupt_tree;
  46
  47 static u_int NumProcessors;
  48 static u_int NumSources;
  49 static int open_pic_irq_offset;
  50 static volatile OpenPIC_Source *ISR[NR_IRQS];
  51 static int openpic_cascade_irq = -1;
  52 static int (*openpic_cascade_fn)(struct pt_regs *);
  53
  54 /* Global Operations */
  55 static void openpic_disable_8259_pass_through(void);
  56 static void openpic_set_priority(u_int pri);
  57 static void openpic_set_spurious(u_int vector);
  58
  59 #ifdef CONFIG_SMP
  60 /* Interprocessor Interrupts */
  61 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  62 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
  63 #endif
  64
  65 /* Timer Interrupts */
  66 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  67 static void openpic_maptimer(u_int timer, u_int cpumask);
  68
  69 /* Interrupt Sources */
  70 static void openpic_enable_irq(u_int irq);
  71 static void openpic_disable_irq(u_int irq);
  72 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  73                             int is_level);
  74 static void openpic_mapirq(u_int irq, u_int cpumask, u_int keepmask);
  75
  76 /*
  77  * These functions are not used but the code is kept here
  78  * for completeness and future reference.
  79  */
  80 #ifdef notused
  81 static void openpic_enable_8259_pass_through(void);
  82 static u_int openpic_get_priority(void);
  83 static u_int openpic_get_spurious(void);
  84 static void openpic_set_sense(u_int irq, int sense);
  85 #endif /* notused */
  86
  87 /*
  88  * Description of the openpic for the higher-level irq code
  89  */
  90 static void openpic_end_irq(unsigned int irq_nr);
  91 static void openpic_ack_irq(unsigned int irq_nr);
  92 static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask);
  93
  94 struct hw_interrupt_type open_pic = {
  95         " OpenPIC  ",
  96         NULL,
  97         NULL,
  98         openpic_enable_irq,
  99         openpic_disable_irq,
 100         openpic_ack_irq,
 101         openpic_end_irq,
 102         openpic_set_affinity
 103 };
 104
 105 #ifdef CONFIG_SMP
 106 static void openpic_end_ipi(unsigned int irq_nr);
 107 static void openpic_ack_ipi(unsigned int irq_nr);
 108 static void openpic_enable_ipi(unsigned int irq_nr);
 109 static void openpic_disable_ipi(unsigned int irq_nr);
 110
 111 struct hw_interrupt_type open_pic_ipi = {
 112         " OpenPIC  ",
 113         NULL,
 114         NULL,
 115         openpic_enable_ipi,
 116         openpic_disable_ipi,
 117         openpic_ack_ipi,
 118         openpic_end_ipi,
 119         0
 120 };
 121 #endif /* CONFIG_SMP */
 122
 123 /*
 124  *  Accesses to the current processor's openpic registers
 125  */
 126 #ifdef CONFIG_SMP
 127 #define THIS_CPU                Processor[cpu]
 128 #define DECL_THIS_CPU           int cpu = smp_hw_index[smp_processor_id()]
 129 #define CHECK_THIS_CPU          check_arg_cpu(cpu)
 130 #else
 131 #define THIS_CPU                Processor[0]
 132 #define DECL_THIS_CPU
 133 #define CHECK_THIS_CPU
 134 #endif /* CONFIG_SMP */
 135
 136 #if 1
 137 #define check_arg_ipi(ipi) \
 138     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 139         printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
 140 #define check_arg_timer(timer) \
 141     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 142         printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
 143 #define check_arg_vec(vec) \
 144     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 145         printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
 146 #define check_arg_pri(pri) \
 147     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 148         printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
 149 /*
 150  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 151  * data has probably been corrupted and we're going to panic or deadlock later
 152  * anyway --Troy
 153  */
 154 #define check_arg_irq(irq) \
 155     if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
 156         || ISR[irq - open_pic_irq_offset] == 0) { \
 157       printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
 158       dump_stack(); }
 159 #define check_arg_cpu(cpu) \
 160     if (cpu < 0 || cpu >= NumProcessors){ \
 161         printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
 162         dump_stack(); }
 163 #else
 164 #define check_arg_ipi(ipi)      do {} while (0)
 165 #define check_arg_timer(timer)  do {} while (0)
 166 #define check_arg_vec(vec)      do {} while (0)
 167 #define check_arg_pri(pri)      do {} while (0)
 168 #define check_arg_irq(irq)      do {} while (0)
 169 #define check_arg_cpu(cpu)      do {} while (0)
 170 #endif
 171
 172 u_int openpic_read(volatile u_int *addr)
 173 {
 174         u_int val;
 175
 176 #ifdef OPENPIC_BIG_ENDIAN
 177         val = in_be32(addr);
 178 #else
 179         val = in_le32(addr);
 180 #endif
 181         return val;
 182 }
 183
 184 static inline void openpic_write(volatile u_int *addr, u_int val)
 185 {
 186 #ifdef OPENPIC_BIG_ENDIAN
 187         out_be32(addr, val);
 188 #else
 189         out_le32(addr, val);
 190 #endif
 191 }
 192
 193 static inline u_int openpic_readfield(volatile u_int *addr, u_int mask)
 194 {
 195         u_int val = openpic_read(addr);
 196         return val & mask;
 197 }
 198
 199 inline void openpic_writefield(volatile u_int *addr, u_int mask,
 200                                u_int field)
 201 {
 202         u_int val = openpic_read(addr);
 203         openpic_write(addr, (val & ~mask) | (field & mask));
 204 }
 205
 206 static inline void openpic_clearfield(volatile u_int *addr, u_int mask)
 207 {
 208         openpic_writefield(addr, mask, 0);
 209 }
 210
 211 static inline void openpic_setfield(volatile u_int *addr, u_int mask)
 212 {
 213         openpic_writefield(addr, mask, mask);
 214 }
 215
 216 static void openpic_safe_writefield(volatile u_int *addr, u_int mask,
 217                                     u_int field)
 218 {
 219         openpic_setfield(addr, OPENPIC_MASK);
 220         while (openpic_read(addr) & OPENPIC_ACTIVITY);
 221         openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 222 }
 223
 224 #ifdef CONFIG_SMP
 225 /* yes this is right ... bug, feature, you decide! -- tgall */
 226 u_int openpic_read_IPI(volatile u_int* addr)
 227 {
 228          u_int val = 0;
 229 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
 230         val = in_be32(addr);
 231 #else
 232         val = in_le32(addr);
 233 #endif
 234         return val;
 235 }
 236
 237 /* because of the power3 be / le above, this is needed */
 238 inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
 239 {
 240         u_int  val = openpic_read_IPI(addr);
 241         openpic_write(addr, (val & ~mask) | (field & mask));
 242 }
 243
 244 static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
 245 {
 246         openpic_writefield_IPI(addr, mask, 0);
 247 }
 248
 249 static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
 250 {
 251         openpic_writefield_IPI(addr, mask, mask);
 252 }
 253
 254 static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
 255 {
 256         openpic_setfield_IPI(addr, OPENPIC_MASK);
 257
 258         /* wait until it's not in use */
 259         /* BenH: Is this code really enough ? I would rather check the result
 260          *       and eventually retry ...
 261          */
 262         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
 263
 264         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 265 }
 266 #endif /* CONFIG_SMP */
 267
 268 #ifdef CONFIG_EPIC_SERIAL_MODE
 269 static void __init openpic_eicr_set_clk(u_int clkval)
 270 {
 271         openpic_writefield(&OpenPIC->Global.Global_Configuration1,
 272                         OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
 273 }
 274
 275 static void __init openpic_enable_sie(void)
 276 {
 277         openpic_setfield(&OpenPIC->Global.Global_Configuration1,
 278                         OPENPIC_EICR_SIE);
 279 }
 280 #endif
 281
 282 #if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM)
 283 static void openpic_reset(void)
 284 {
 285         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 286                          OPENPIC_CONFIG_RESET);
 287         while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
 288                                  OPENPIC_CONFIG_RESET))
 289                 mb();
 290 }
 291 #endif
 292
 293 void __init openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
 294 {
 295         volatile OpenPIC_Source *src = first_ISR;
 296         int i, last_irq;
 297
 298         last_irq = first_irq + num_irqs;
 299         if (last_irq > NumSources)
 300                 NumSources = last_irq;
 301         if (src == 0)
 302                 src = &((struct OpenPIC *)OpenPIC_Addr)->Source[first_irq];
 303         for (i = first_irq; i < last_irq; ++i, ++src)
 304                 ISR[i] = src;
 305 }
 306
 307 /*
 308  * The `offset' parameter defines where the interrupts handled by the
 309  * OpenPIC start in the space of interrupt numbers that the kernel knows
 310  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 311  * kernel's interrupt numbering scheme.
 312  * We assume there is only one OpenPIC.
 313  */
 314 void __init openpic_init(int offset)
 315 {
 316         u_int t, i;
 317         u_int timerfreq;
 318         const char *version;
 319
 320         if (!OpenPIC_Addr) {
 321                 printk("No OpenPIC found !\n");
 322                 return;
 323         }
 324         OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
 325
 326 #ifdef CONFIG_EPIC_SERIAL_MODE
 327         /* Have to start from ground zero.
 328         */
 329         openpic_reset();
 330 #endif
 331
 332         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 333
 334         t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
 335         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 336         case 1:
 337                 version = "1.0";
 338                 break;
 339         case 2:
 340                 version = "1.2";
 341                 break;
 342         case 3:
 343                 version = "1.3";
 344                 break;
 345         default:
 346                 version = "?";
 347                 break;
 348         }
 349         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 350                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 351         if (NumSources == 0)
 352                 openpic_set_sources(0,
 353                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 354                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 355                                     NULL);
 356         printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
 357                version, NumProcessors, NumSources, OpenPIC);
 358         timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
 359         if (timerfreq)
 360                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 361                        timerfreq / 1000000, timerfreq % 1000000);
 362
 363         open_pic_irq_offset = offset;
 364
 365         /* Initialize timer interrupts */
 366         if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
 367         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 368                 /* Disabled, Priority 0 */
 369                 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
 370                 /* No processor */
 371                 openpic_maptimer(i, 0);
 372         }
 373
 374 #ifdef CONFIG_SMP
 375         /* Initialize IPI interrupts */
 376         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
 377         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
 378                 /* Disabled, Priority 10..13 */
 379                 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
 380                 /* IPIs are per-CPU */
 381                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
 382                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
 383         }
 384 #endif
 385
 386         /* Initialize external interrupts */
 387         if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
 388
 389         openpic_set_priority(0xf);
 390
 391         /* Init all external sources, including possibly the cascade. */
 392         for (i = 0; i < NumSources; i++) {
 393                 int sense;
 394
 395                 if (ISR[i] == 0)
 396                         continue;
 397
 398                 /* the bootloader may have left it enabled (bad !) */
 399                 openpic_disable_irq(i+offset);
 400
 401                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 402                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 403
 404                 if (sense & IRQ_SENSE_MASK)
 405                         irq_desc[i+offset].status = IRQ_LEVEL;
 406
 407                 /* Enabled, Priority 8 */
 408                 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
 409                                 (sense & IRQ_SENSE_MASK));
 410                 /* Processor 0 */
 411                 openpic_mapirq(i, 1<<0, 0);
 412         }
 413
 414         /* Init descriptors */
 415         for (i = offset; i < NumSources + offset; i++)
 416                 irq_desc[i].handler = &open_pic;
 417
 418         /* Initialize the spurious interrupt */
 419         if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
 420         openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
 421         openpic_disable_8259_pass_through();
 422 #ifdef CONFIG_EPIC_SERIAL_MODE
 423         openpic_eicr_set_clk(7);        /* Slowest value until we know better */
 424         openpic_enable_sie();
 425 #endif
 426         openpic_set_priority(0);
 427
 428         if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
 429 }
 430
 431 #ifdef notused
 432 static void openpic_enable_8259_pass_through(void)
 433 {
 434         openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
 435                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 436 }
 437 #endif /* notused */
 438
 439 static void openpic_disable_8259_pass_through(void)
 440 {
 441         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 442                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 443 }
 444
 445 /*
 446  *  Find out the current interrupt
 447  */
 448 u_int openpic_irq(void)
 449 {
 450         u_int vec;
 451         DECL_THIS_CPU;
 452
 453         CHECK_THIS_CPU;
 454         vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
 455                                 OPENPIC_VECTOR_MASK);
 456         return vec;
 457 }
 458
 459 void openpic_eoi(void)
 460 {
 461         DECL_THIS_CPU;
 462
 463         CHECK_THIS_CPU;
 464         openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
 465         /* Handle PCI write posting */
 466         (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
 467 }
 468
 469 #ifdef notused
 470 static u_int openpic_get_priority(void)
 471 {
 472         DECL_THIS_CPU;
 473
 474         CHECK_THIS_CPU;
 475         return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 476                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 477 }
 478 #endif /* notused */
 479
 480 static void __init openpic_set_priority(u_int pri)
 481 {
 482         DECL_THIS_CPU;
 483
 484         CHECK_THIS_CPU;
 485         check_arg_pri(pri);
 486         openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 487                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 488 }
 489
 490 /*
 491  *  Get/set the spurious vector
 492  */
 493 #ifdef notused
 494 static u_int openpic_get_spurious(void)
 495 {
 496         return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
 497                                  OPENPIC_VECTOR_MASK);
 498 }
 499 #endif /* notused */
 500
 501 static void openpic_set_spurious(u_int vec)
 502 {
 503         check_arg_vec(vec);
 504         openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 505                            vec);
 506 }
 507
 508 #ifdef CONFIG_SMP
 509 /*
 510  * Convert a cpu mask from logical to physical cpu numbers.
 511  */
 512 static inline u32 physmask(u32 cpumask)
 513 {
 514         int i;
 515         u32 mask = 0;
 516
 517         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 518                 if (cpu_online(i))
 519                         mask |= (cpumask & 1) << smp_hw_index[i];
 520         return mask;
 521 }
 522 #else
 523 #define physmask(cpumask)       (cpumask)
 524 #endif
 525
 526 void openpic_reset_processor_phys(u_int mask)
 527 {
 528         openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
 529 }
 530
 531 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
 532 static spinlock_t openpic_setup_lock = SPIN_LOCK_UNLOCKED;
 533 #endif
 534
 535 #ifdef CONFIG_SMP
 536 /*
 537  *  Initialize an interprocessor interrupt (and disable it)
 538  *
 539  *  ipi: OpenPIC interprocessor interrupt number
 540  *  pri: interrupt source priority
 541  *  vec: the vector it will produce
 542  */
 543 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
 544 {
 545         check_arg_ipi(ipi);
 546         check_arg_pri(pri);
 547         check_arg_vec(vec);
 548         openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
 549                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 550                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 551 }
 552
 553 /*
 554  *  Send an IPI to one or more CPUs
 555  *
 556  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
 557  *  and not a system-wide interrupt number
 558  */
 559 void openpic_cause_IPI(u_int ipi, u_int cpumask)
 560 {
 561         DECL_THIS_CPU;
 562
 563         CHECK_THIS_CPU;
 564         check_arg_ipi(ipi);
 565         openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
 566                       physmask(cpumask));
 567 }
 568
 569 void openpic_request_IPIs(void)
 570 {
 571         int i;
 572
 573         /*
 574          * Make sure this matches what is defined in smp.c for
 575          * smp_message_{pass|recv}() or what shows up in
 576          * /proc/interrupts will be wrong!!! --Troy */
 577
 578         if (OpenPIC == NULL)
 579                 return;
 580
 581         /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 582         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
 583                     openpic_ipi_action, SA_INTERRUPT,
 584                     "IPI0 (call function)", 0);
 585         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
 586                     openpic_ipi_action, SA_INTERRUPT,
 587                     "IPI1 (reschedule)", 0);
 588         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
 589                     openpic_ipi_action, SA_INTERRUPT,
 590                     "IPI2 (invalidate tlb)", 0);
 591         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
 592                     openpic_ipi_action, SA_INTERRUPT,
 593                     "IPI3 (xmon break)", 0);
 594
 595         for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
 596                 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
 597 }
 598
 599 /*
 600  * Do per-cpu setup for SMP systems.
 601  *
 602  * Get IPI's working and start taking interrupts.
 603  *   -- Cort
 604  */
 605
 606 void __devinit do_openpic_setup_cpu(void)
 607 {
 608 #ifdef CONFIG_IRQ_ALL_CPUS
 609         int i;
 610         u32 msk;
 611 #endif
 612         spin_lock(&openpic_setup_lock);
 613
 614 #ifdef CONFIG_IRQ_ALL_CPUS
 615         msk = 1 << smp_hw_index[smp_processor_id()];
 616
 617         /* let the openpic know we want intrs. default affinity
 618          * is 0xffffffff until changed via /proc
 619          * That's how it's done on x86. If we want it differently, then
 620          * we should make sure we also change the default values of irq_affinity
 621          * in irq.c.
 622          */
 623         for (i = 0; i < NumSources; i++)
 624                 openpic_mapirq(i, msk, ~0U);
 625 #endif /* CONFIG_IRQ_ALL_CPUS */
 626         openpic_set_priority(0);
 627
 628         spin_unlock(&openpic_setup_lock);
 629 }
 630 #endif /* CONFIG_SMP */
 631
 632 /*
 633  *  Initialize a timer interrupt (and disable it)
 634  *
 635  *  timer: OpenPIC timer number
 636  *  pri: interrupt source priority
 637  *  vec: the vector it will produce
 638  */
 639 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
 640 {
 641         check_arg_timer(timer);
 642         check_arg_pri(pri);
 643         check_arg_vec(vec);
 644         openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
 645                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 646                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 647 }
 648
 649 /*
 650  *  Map a timer interrupt to one or more CPUs
 651  */
 652 static void __init openpic_maptimer(u_int timer, u_int cpumask)
 653 {
 654         check_arg_timer(timer);
 655         openpic_write(&OpenPIC->Global.Timer[timer].Destination,
 656                       physmask(cpumask));
 657 }
 658
 659 /*
 660  * Initalize the interrupt source which will generate an NMI.
 661  * This raises the interrupt's priority from 8 to 9.
 662  *
 663  * irq: The logical IRQ which generates an NMI.
 664  */
 665 void __init
 666 openpic_init_nmi_irq(u_int irq)
 667 {
 668         check_arg_irq(irq);
 669         openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
 670                                 OPENPIC_PRIORITY_MASK,
 671                                 9 << OPENPIC_PRIORITY_SHIFT);
 672 }
 673
 674 /*
 675  *
 676  * All functions below take an offset'ed irq argument
 677  *
 678  */
 679
 680 /*
 681  * Hookup a cascade to the OpenPIC.
 682  */
 683 void __init
 684 openpic_hookup_cascade(u_int irq, char *name,
 685         int (*cascade_fn)(struct pt_regs *))
 686 {
 687         openpic_cascade_irq = irq;
 688         openpic_cascade_fn = cascade_fn;
 689         if (request_irq(irq, no_action, SA_INTERRUPT, name, NULL))
 690                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 691                                 irq - open_pic_irq_offset);
 692 }
 693
 694 /*
 695  *  Enable/disable an external interrupt source
 696  *
 697  *  Externally called, irq is an offseted system-wide interrupt number
 698  */
 699 static void openpic_enable_irq(u_int irq)
 700 {
 701         volatile u_int *vpp;
 702
 703         check_arg_irq(irq);
 704         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 705         openpic_clearfield(vpp, OPENPIC_MASK);
 706         /* make sure mask gets to controller before we return to user */
 707         do {
 708                 mb(); /* sync is probably useless here */
 709         } while (openpic_readfield(vpp, OPENPIC_MASK));
 710 }
 711
 712 static void openpic_disable_irq(u_int irq)
 713 {
 714         volatile u_int *vpp;
 715         u32 vp;
 716
 717         check_arg_irq(irq);
 718         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 719         openpic_setfield(vpp, OPENPIC_MASK);
 720         /* make sure mask gets to controller before we return to user */
 721         do {
 722                 mb();  /* sync is probably useless here */
 723                 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 724         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 725 }
 726
 727 #ifdef CONFIG_SMP
 728 /*
 729  *  Enable/disable an IPI interrupt source
 730  *
 731  *  Externally called, irq is an offseted system-wide interrupt number
 732  */
 733 void openpic_enable_ipi(u_int irq)
 734 {
 735         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 736         check_arg_ipi(irq);
 737         openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 738
 739 }
 740
 741 void openpic_disable_ipi(u_int irq)
 742 {
 743         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 744         check_arg_ipi(irq);
 745         openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 746 }
 747 #endif
 748
 749 /*
 750  *  Initialize an interrupt source (and disable it!)
 751  *
 752  *  irq: OpenPIC interrupt number
 753  *  pri: interrupt source priority
 754  *  vec: the vector it will produce
 755  *  pol: polarity (1 for positive, 0 for negative)
 756  *  sense: 1 for level, 0 for edge
 757  */
 758 static void __init
 759 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 760 {
 761         openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 762                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 763                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 764                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 765                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 766                                         OPENPIC_POLARITY_NEGATIVE) |
 767                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 768 }
 769
 770 /*
 771  *  Map an interrupt source to one or more CPUs
 772  */
 773 static void openpic_mapirq(u_int irq, u_int physmask, u_int keepmask)
 774 {
 775         if (ISR[irq] == 0)
 776                 return;
 777         if (keepmask != 0)
 778                 physmask |= openpic_read(&ISR[irq]->Destination) & keepmask;
 779         openpic_write(&ISR[irq]->Destination, physmask);
 780 }
 781
 782 #ifdef notused
 783 /*
 784  *  Set the sense for an interrupt source (and disable it!)
 785  *
 786  *  sense: 1 for level, 0 for edge
 787  */
 788 static void openpic_set_sense(u_int irq, int sense)
 789 {
 790         if (ISR[irq] != 0)
 791                 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 792                                         OPENPIC_SENSE_LEVEL,
 793                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 794 }
 795 #endif /* notused */
 796
 797 /* No spinlocks, should not be necessary with the OpenPIC
 798  * (1 register = 1 interrupt and we have the desc lock).
 799  */
 800 static void openpic_ack_irq(unsigned int irq_nr)
 801 {
 802 #ifdef __SLOW_VERSION__
 803         openpic_disable_irq(irq_nr);
 804         openpic_eoi();
 805 #else
 806         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 807                 openpic_eoi();
 808 #endif
 809 }
 810
 811 static void openpic_end_irq(unsigned int irq_nr)
 812 {
 813 #ifdef __SLOW_VERSION__
 814         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 815             && irq_desc[irq_nr].action)
 816                 openpic_enable_irq(irq_nr);
 817 #else
 818         if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
 819                 openpic_eoi();
 820 #endif
 821 }
 822
 823 static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask)
 824 {
 825         openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), 0);
 826 }
 827
 828 #ifdef CONFIG_SMP
 829 static void openpic_ack_ipi(unsigned int irq_nr)
 830 {
 831         openpic_eoi();
 832 }
 833
 834 static void openpic_end_ipi(unsigned int irq_nr)
 835 {
 836 }
 837
 838 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 839 {
 840         smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
 841         return IRQ_HANDLED;
 842 }
 843
 844 #endif /* CONFIG_SMP */
 845
 846 int
 847 openpic_get_irq(struct pt_regs *regs)
 848 {
 849         int irq = openpic_irq();
 850
 851         /*
 852          * Check for the cascade interrupt and call the cascaded
 853          * interrupt controller function (usually i8259_irq) if so.
 854          * This should move to irq.c eventually.  -- paulus
 855          */
 856         if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
 857                 int cirq = openpic_cascade_fn(regs);
 858
 859                 /* Allow for the cascade being shared with other devices */
 860                 if (cirq != -1) {
 861                         irq = cirq;
 862                         openpic_eoi();
 863                 }
 864         } else if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
 865                 irq = -1;
 866         return irq;
 867 }
 868
 869 #ifdef CONFIG_SMP
 870 void
 871 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
 872 {
 873         /* make sure we're sending something that translates to an IPI */
 874         if (msg > 0x3) {
 875                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 876                        smp_processor_id(), msg);
 877                 return;
 878         }
 879         switch (target) {
 880         case MSG_ALL:
 881                 openpic_cause_IPI(msg, 0xffffffff);
 882                 break;
 883         case MSG_ALL_BUT_SELF:
 884                 openpic_cause_IPI(msg,
 885                                   0xffffffff & ~(1 << smp_processor_id()));
 886                 break;
 887         default:
 888                 openpic_cause_IPI(msg, 1<<target);
 889                 break;
 890         }
 891 }
 892 #endif /* CONFIG_SMP */
 893
 894 #ifdef CONFIG_PM
 895
 896 /*
 897  * We implement the IRQ controller as a sysdev and put it
 898  * to sleep at powerdown stage (the callback is named suspend,
 899  * but it's old semantics, for the Device Model, it's really
 900  * powerdown). The possible problem is that another sysdev that
 901  * happens to be suspend after this one will have interrupts off,
 902  * that may be an issue... For now, this isn't an issue on pmac
 903  * though...
 904  */
 905
 906 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 907 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 908 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 909 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 910 static int openpic_suspend_count;
 911
 912 static void openpic_cached_enable_irq(u_int irq)
 913 {
 914         check_arg_irq(irq);
 915         save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
 916 }
 917
 918 static void openpic_cached_disable_irq(u_int irq)
 919 {
 920         check_arg_irq(irq);
 921         save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
 922 }
 923
 924 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 925  * we need something better to deal with that... Maybe switch to S1 for
 926  * cpufreq changes
 927  */
 928 int openpic_suspend(struct sys_device *sysdev, u32 state)
 929 {
 930         int     i;
 931         unsigned long flags;
 932
 933         spin_lock_irqsave(&openpic_setup_lock, flags);
 934
 935         if (openpic_suspend_count++ > 0) {
 936                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 937                 return 0;
 938         }
 939
 940         open_pic.enable = openpic_cached_enable_irq;
 941         open_pic.disable = openpic_cached_disable_irq;
 942
 943         for (i=0; i<NumProcessors; i++) {
 944                 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
 945                 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
 946                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 947         }
 948
 949         for (i=0; i<OPENPIC_NUM_IPI; i++)
 950                 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
 951         for (i=0; i<NumSources; i++) {
 952                 if (ISR[i] == 0)
 953                         continue;
 954                 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 955                 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
 956         }
 957
 958         spin_unlock_irqrestore(&openpic_setup_lock, flags);
 959
 960         return 0;
 961 }
 962
 963 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 964  * we need something better to deal with that... Maybe switch to S1 for
 965  * cpufreq changes
 966  */
 967 int openpic_resume(struct sys_device *sysdev)
 968 {
 969         int             i;
 970         unsigned long   flags;
 971         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 972                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 973                                         OPENPIC_MASK;
 974
 975         spin_lock_irqsave(&openpic_setup_lock, flags);
 976
 977         if ((--openpic_suspend_count) > 0) {
 978                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 979                 return 0;
 980         }
 981
 982         openpic_reset();
 983
 984         /* OpenPIC sometimes seem to need some time to be fully back up... */
 985         do {
 986                 openpic_set_spurious(OPENPIC_VEC_SPURIOUS+open_pic_irq_offset);
 987         } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
 988                         != (OPENPIC_VEC_SPURIOUS + open_pic_irq_offset));
 989
 990         openpic_disable_8259_pass_through();
 991
 992         for (i=0; i<OPENPIC_NUM_IPI; i++)
 993                 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
 994                               save_ipi_vp[i]);
 995         for (i=0; i<NumSources; i++) {
 996                 if (ISR[i] == 0)
 997                         continue;
 998                 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
 999                 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1000                 /* make sure mask gets to controller before we return to user */
1001                 do {
1002                         openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1003                 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1004                          != (save_irq_src_vp[i] & vppmask));
1005         }
1006         for (i=0; i<NumProcessors; i++)
1007                 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1008                               save_cpu_task_pri[i]);
1009
1010         open_pic.enable = openpic_enable_irq;
1011         open_pic.disable = openpic_disable_irq;
1012
1013         spin_unlock_irqrestore(&openpic_setup_lock, flags);
1014
1015         return 0;
1016 }
1017
1018 #endif /* CONFIG_PM */
1019
1020 static struct sysdev_class openpic_sysclass = {
1021         set_kset_name("openpic"),
1022 };
1023
1024 static struct sys_device device_openpic = {
1025         .id             = 0,
1026         .cls            = &openpic_sysclass,
1027 };
1028
1029 static struct sysdev_driver driver_openpic = {
1030 #ifdef CONFIG_PM
1031         .suspend        = &openpic_suspend,
1032         .resume         = &openpic_resume,
1033 #endif /* CONFIG_PM */
1034 };
1035
1036 static int __init init_openpic_sysfs(void)
1037 {
1038         int rc;
1039
1040         if (!OpenPIC_Addr)
1041                 return -ENODEV;
1042         printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1043         rc = sysdev_class_register(&openpic_sysclass);
1044         if (rc) {
1045                 printk(KERN_ERR "Failed registering openpic sys class\n");
1046                 return -ENODEV;
1047         }
1048         rc = sysdev_register(&device_openpic);
1049         if (rc) {
1050                 printk(KERN_ERR "Failed registering openpic sys device\n");
1051                 return -ENODEV;
1052         }
1053         rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1054         if (rc) {
1055                 printk(KERN_ERR "Failed registering openpic sys driver\n");
1056                 return -ENODEV;
1057         }
1058         return 0;
1059 }
1060
1061 subsys_initcall(init_openpic_sysfs);
1062