arch/ppc/syslib/ppc85xx_setup.c

   1 /*
   2  * arch/ppc/syslib/ppc85xx_setup.c
   3  *
   4  * MPC85XX common board code
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial.h>
  22 #include <linux/tty.h>  /* for linux/serial_core.h */
  23 #include <linux/serial_core.h>
  24
  25 #include <asm/prom.h>
  26 #include <asm/time.h>
  27 #include <asm/mpc85xx.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/mmu.h>
  30 #include <asm/ocp.h>
  31 #include <asm/kgdb.h>
  32
  33 /* Return the amount of memory */
  34 unsigned long __init
  35 mpc85xx_find_end_of_memory(void)
  36 {
  37         bd_t *binfo;
  38
  39         binfo = (bd_t *) __res;
  40
  41         return binfo->bi_memsize;
  42 }
  43
  44 /* The decrementer counts at the system (internal) clock freq divided by 8 */
  45 void __init
  46 mpc85xx_calibrate_decr(void)
  47 {
  48         bd_t *binfo = (bd_t *) __res;
  49         unsigned int freq, divisor;
  50
  51         /* get the core frequency */
  52         freq = binfo->bi_busfreq;
  53
  54         /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
  55         divisor = 8;
  56         tb_ticks_per_jiffy = freq / divisor / HZ;
  57         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  58
  59         /* Set the time base to zero */
  60         mtspr(SPRN_TBWL, 0);
  61         mtspr(SPRN_TBWU, 0);
  62
  63         /* Clear any pending timer interrupts */
  64         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  65
  66         /* Enable decrementer interrupt */
  67         mtspr(SPRN_TCR, TCR_DIE);
  68 }
  69
  70 #ifdef CONFIG_SERIAL_8250
  71 void __init
  72 mpc85xx_early_serial_map(void)
  73 {
  74         struct uart_port serial_req;
  75         bd_t *binfo = (bd_t *) __res;
  76         phys_addr_t duart_paddr = binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
  77
  78         /* Setup serial port access */
  79         memset(&serial_req, 0, sizeof (serial_req));
  80         serial_req.uartclk = binfo->bi_busfreq;
  81         serial_req.line = 0;
  82         serial_req.irq = MPC85xx_IRQ_DUART;
  83         serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
  84         serial_req.iotype = SERIAL_IO_MEM;
  85         serial_req.membase = ioremap(duart_paddr, MPC85xx_UART0_SIZE);
  86         serial_req.mapbase = duart_paddr;
  87         serial_req.regshift = 0;
  88
  89 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  90         gen550_init(0, &serial_req);
  91 #endif
  92
  93         if (early_serial_setup(&serial_req) != 0)
  94                 printk("Early serial init of port 0 failed\n");
  95
  96         /* Assume early_serial_setup() doesn't modify serial_req */
  97         duart_paddr = binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
  98         serial_req.line = 1;
  99         serial_req.mapbase = duart_paddr;
 100         serial_req.membase = ioremap(duart_paddr, MPC85xx_UART1_SIZE);
 101
 102 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 103         gen550_init(1, &serial_req);
 104 #endif
 105
 106         if (early_serial_setup(&serial_req) != 0)
 107                 printk("Early serial init of port 1 failed\n");
 108 }
 109 #endif
 110
 111 void
 112 mpc85xx_restart(char *cmd)
 113 {
 114         local_irq_disable();
 115         abort();
 116 }
 117
 118 void
 119 mpc85xx_power_off(void)
 120 {
 121         local_irq_disable();
 122         for(;;);
 123 }
 124
 125 void
 126 mpc85xx_halt(void)
 127 {
 128         local_irq_disable();
 129         for(;;);
 130 }
 131
 132 #ifdef CONFIG_PCI
 133 static void __init
 134 mpc85xx_setup_pci1(struct pci_controller *hose)
 135 {
 136         volatile struct ccsr_pci *pci;
 137         volatile struct ccsr_guts *guts;
 138         unsigned short temps;
 139         bd_t *binfo = (bd_t *) __res;
 140
 141         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
 142                     MPC85xx_PCI1_SIZE);
 143
 144         guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
 145                     MPC85xx_GUTS_SIZE);
 146
 147         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 148         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 149         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 150
 151 #define PORDEVSR_PCI    (0x00800000)    /* PCI Mode */
 152         if (guts->pordevsr & PORDEVSR_PCI) {
 153                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 154         } else {
 155                 /* PCI-X init */
 156                 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 157                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 158                 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
 159         }
 160
 161         /* Disable all windows (except powar0 since its ignored) */
 162         pci->powar1 = 0;
 163         pci->powar2 = 0;
 164         pci->powar3 = 0;
 165         pci->powar4 = 0;
 166         pci->piwar1 = 0;
 167         pci->piwar2 = 0;
 168         pci->piwar3 = 0;
 169
 170         /* Setup 512M Phys:PCI 1:1 outbound mem window @ 0x80000000 */
 171         pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 172         pci->potear1 = 0x00000000;
 173         pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 174         pci->powar1 = 0x8004401c;       /* Enable, Mem R/W, 512M */
 175
 176         /* Setup 16M outboud IO windows @ 0xe2000000 */
 177         pci->potar2 = 0x00000000;
 178         pci->potear2 = 0x00000000;
 179         pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
 180         pci->powar2 = 0x80088017;       /* Enable, IO R/W, 16M */
 181
 182         /* Setup 2G inbound Memory Window @ 0 */
 183         pci->pitar1 = 0x00000000;
 184         pci->piwbar1 = 0x00000000;
 185         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 186                                            Mem, Snoop R/W, 2G */
 187 }
 188
 189
 190 extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
 191 extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
 192
 193 #if CONFIG_85xx_PCI2
 194 static void __init
 195 mpc85xx_setup_pci2(struct pci_controller *hose)
 196 {
 197         volatile struct ccsr_pci *pci;
 198         unsigned short temps;
 199         bd_t *binfo = (bd_t *) __res;
 200
 201         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
 202                     MPC85xx_PCI2_SIZE);
 203
 204         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 205         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 206         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 207         early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 208
 209         /* Disable all windows (except powar0 since its ignored) */
 210         pci->powar1 = 0;
 211         pci->powar2 = 0;
 212         pci->powar3 = 0;
 213         pci->powar4 = 0;
 214         pci->piwar1 = 0;
 215         pci->piwar2 = 0;
 216         pci->piwar3 = 0;
 217
 218         /* Setup 512M Phys:PCI 1:1 outbound mem window @ 0xa0000000 */
 219         pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 220         pci->potear1 = 0x00000000;
 221         pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 222         pci->powar1 = 0x8004401c;       /* Enable, Mem R/W, 512M */
 223
 224         /* Setup 16M outboud IO windows @ 0xe3000000 */
 225         pci->potar2 = 0x00000000;
 226         pci->potear2 = 0x00000000;
 227         pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
 228         pci->powar2 = 0x80088017;       /* Enable, IO R/W, 16M */
 229
 230         /* Setup 2G inbound Memory Window @ 0 */
 231         pci->pitar1 = 0x00000000;
 232         pci->piwbar1 = 0x00000000;
 233         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 234                                            Mem, Snoop R/W, 2G */
 235 }
 236 #endif /* CONFIG_85xx_PCI2 */
 237
 238 void __init
 239 mpc85xx_setup_hose(void)
 240 {
 241         struct pci_controller *hose_a;
 242 #ifdef CONFIG_85xx_PCI2
 243         struct pci_controller *hose_b;
 244 #endif
 245         bd_t *binfo = (bd_t *) __res;
 246
 247         hose_a = pcibios_alloc_controller();
 248
 249         if (!hose_a)
 250                 return;
 251
 252         ppc_md.pci_swizzle = common_swizzle;
 253         ppc_md.pci_map_irq = mpc85xx_map_irq;
 254
 255         hose_a->first_busno = 0;
 256         hose_a->bus_offset = 0;
 257         hose_a->last_busno = 0xff;
 258
 259         setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 260                            binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 261         hose_a->set_cfg_type = 1;
 262
 263         mpc85xx_setup_pci1(hose_a);
 264
 265         hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
 266         hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
 267         hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
 268
 269         hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
 270         hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
 271         hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
 272 #if CONFIG_85xx_PCI2
 273         isa_io_base =
 274                 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
 275                                         MPC85XX_PCI1_IO_SIZE +
 276                                         MPC85XX_PCI2_IO_SIZE);
 277 #else
 278         isa_io_base =
 279                 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
 280                                         MPC85XX_PCI1_IO_SIZE);
 281 #endif
 282         hose_a->io_base_virt = (void *) isa_io_base;
 283
 284         /* setup resources */
 285         pci_init_resource(&hose_a->mem_resources[0],
 286                         MPC85XX_PCI1_LOWER_MEM,
 287                         MPC85XX_PCI1_UPPER_MEM,
 288                         IORESOURCE_MEM, "PCI1 host bridge");
 289
 290         pci_init_resource(&hose_a->io_resource,
 291                         MPC85XX_PCI1_LOWER_IO,
 292                         MPC85XX_PCI1_UPPER_IO,
 293                         IORESOURCE_IO, "PCI1 host bridge");
 294
 295         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 296
 297         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 298
 299 #if CONFIG_85xx_PCI2
 300         hose_b = pcibios_alloc_controller();
 301
 302         if (!hose_b)
 303                 return;
 304
 305         hose_b->bus_offset = hose_a->last_busno + 1;
 306         hose_b->first_busno = hose_a->last_busno + 1;
 307         hose_b->last_busno = 0xff;
 308
 309         setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 310                            binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 311         hose_b->set_cfg_type = 1;
 312
 313         mpc85xx_setup_pci2(hose_b);
 314
 315         hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
 316         hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
 317         hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
 318
 319         hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
 320         hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
 321         hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
 322         hose_b->io_base_virt = (void *) isa_io_base + MPC85XX_PCI1_IO_SIZE;
 323
 324         /* setup resources */
 325         pci_init_resource(&hose_b->mem_resources[0],
 326                         MPC85XX_PCI2_LOWER_MEM,
 327                         MPC85XX_PCI2_UPPER_MEM,
 328                         IORESOURCE_MEM, "PCI2 host bridge");
 329
 330         pci_init_resource(&hose_b->io_resource,
 331                         MPC85XX_PCI2_LOWER_IO,
 332                         MPC85XX_PCI2_UPPER_IO,
 333                         IORESOURCE_IO, "PCI2 host bridge");
 334
 335         hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
 336 #endif
 337         return;
 338 }
 339 #endif /* CONFIG_PCI */
 340
 341