arch/ppc/syslib/todc_time.c

   1 /*
   2  * arch/ppc/syslib/todc_time.c
   3  *
   4  * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
   5  * Real Time Clocks/Timekeepers.
   6  *
   7  * Author: Mark A. Greer
   8  *         mgreer@mvista.com
   9  *
  10  * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15 #include <linux/errno.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/time.h>
  19 #include <linux/timex.h>
  20 #include <linux/bcd.h>
  21
  22 #include <asm/machdep.h>
  23 #include <asm/io.h>
  24 #include <asm/time.h>
  25 #include <asm/todc.h>
  26
  27 /*
  28  * Depending on the hardware on your board and your board design, the
  29  * RTC/NVRAM may be accessed either directly (like normal memory) or via
  30  * address/data registers.  If your board uses the direct method, set
  31  * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
  32  * 'nvram_as1' NULL.  If your board uses address/data regs to access nvram,
  33  * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
  34  * address of the upper byte (leave NULL if using mc146818), and set
  35  * 'nvram_data' to the address of the 8-bit data register.
  36  *
  37  * In order to break the assumption that the RTC and NVRAM are accessed by
  38  * the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and
  39  * 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val'
  40  * and 'ppc_md.rtc_write_val' will be used.
  41  *
  42  * Note: Even though the documentation for the various RTC chips say that it
  43  *       take up to a second before it starts updating once the 'R' bit is
  44  *       cleared, they always seem to update even though we bang on it many
  45  *       times a second.  This is true, except for the Dallas Semi 1746/1747
  46  *       (possibly others).  Those chips seem to have a real problem whenever
  47  *       we set the 'R' bit before reading them, they basically stop counting.
  48  *                                              --MAG
  49  */
  50
  51 extern spinlock_t       rtc_lock;
  52
  53 /*
  54  * 'todc_info' should be initialized in your *_setup.c file to
  55  * point to a fully initialized 'todc_info_t' structure.
  56  * This structure holds all the register offsets for your particular
  57  * TODC/RTC chip.
  58  * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
  59  */
  60
  61 #ifdef  RTC_FREQ_SELECT
  62 #undef  RTC_FREQ_SELECT
  63 #define RTC_FREQ_SELECT         control_b       /* Register A */
  64 #endif
  65
  66 #ifdef  RTC_CONTROL
  67 #undef  RTC_CONTROL
  68 #define RTC_CONTROL             control_a       /* Register B */
  69 #endif
  70
  71 #ifdef  RTC_INTR_FLAGS
  72 #undef  RTC_INTR_FLAGS
  73 #define RTC_INTR_FLAGS          watchdog        /* Register C */
  74 #endif
  75
  76 #ifdef  RTC_VALID
  77 #undef  RTC_VALID
  78 #define RTC_VALID               interrupts      /* Register D */
  79 #endif
  80
  81 /* Access routines when RTC accessed directly (like normal memory) */
  82 u_char
  83 todc_direct_read_val(int addr)
  84 {
  85         return readb(todc_info->nvram_data + addr);
  86 }
  87
  88 void
  89 todc_direct_write_val(int addr, unsigned char val)
  90 {
  91         writeb(val, todc_info->nvram_data + addr);
  92         return;
  93 }
  94
  95 /* Access routines for accessing m48txx type chips via addr/data regs */
  96 u_char
  97 todc_m48txx_read_val(int addr)
  98 {
  99         outb(addr, todc_info->nvram_as0);
 100         outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
 101         return inb(todc_info->nvram_data);
 102 }
 103
 104 void
 105 todc_m48txx_write_val(int addr, unsigned char val)
 106 {
 107         outb(addr, todc_info->nvram_as0);
 108         outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
 109         outb(val, todc_info->nvram_data);
 110         return;
 111 }
 112
 113 /* Access routines for accessing mc146818 type chips via addr/data regs */
 114 u_char
 115 todc_mc146818_read_val(int addr)
 116 {
 117         outb_p(addr, todc_info->nvram_as0);
 118         return inb_p(todc_info->nvram_data);
 119 }
 120
 121 void
 122 todc_mc146818_write_val(int addr, unsigned char val)
 123 {
 124         outb_p(addr, todc_info->nvram_as0);
 125         outb_p(val, todc_info->nvram_data);
 126 }
 127
 128
 129 /*
 130  * Routines to make RTC chips with NVRAM buried behind an addr/data pair
 131  * have the NVRAM and clock regs appear at the same level.
 132  * The NVRAM will appear to start at addr 0 and the clock regs will appear
 133  * to start immediately after the NVRAM (actually, start at offset
 134  * todc_info->nvram_size).
 135  */
 136 static inline u_char
 137 todc_read_val(int addr)
 138 {
 139         u_char  val;
 140
 141         if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
 142                 if (addr < todc_info->nvram_size) { /* NVRAM */
 143                         ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
 144                         val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
 145                 }
 146                 else { /* Clock Reg */
 147                         addr -= todc_info->nvram_size;
 148                         val = ppc_md.rtc_read_val(addr);
 149                 }
 150         }
 151         else {
 152                 val = ppc_md.rtc_read_val(addr);
 153         }
 154
 155         return val;
 156 }
 157
 158 static inline void
 159 todc_write_val(int addr, u_char val)
 160 {
 161         if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
 162                 if (addr < todc_info->nvram_size) { /* NVRAM */
 163                         ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
 164                         ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
 165                 }
 166                 else { /* Clock Reg */
 167                         addr -= todc_info->nvram_size;
 168                         ppc_md.rtc_write_val(addr, val);
 169                 }
 170         }
 171         else {
 172                 ppc_md.rtc_write_val(addr, val);
 173         }
 174 }
 175
 176 /*
 177  * TODC routines
 178  *
 179  * There is some ugly stuff in that there are assumptions for the mc146818.
 180  *
 181  * Assumptions:
 182  *      - todc_info->control_a has the offset as mc146818 Register B reg
 183  *      - todc_info->control_b has the offset as mc146818 Register A reg
 184  *      - m48txx control reg's write enable or 'W' bit is same as
 185  *        mc146818 Register B 'SET' bit (i.e., 0x80)
 186  *
 187  * These assumptions were made to make the code simpler.
 188  */
 189 long __init
 190 todc_time_init(void)
 191 {
 192         u_char  cntl_b;
 193
 194         if (!ppc_md.rtc_read_val)
 195                 ppc_md.rtc_read_val = ppc_md.nvram_read_val;
 196         if (!ppc_md.rtc_write_val)
 197                 ppc_md.rtc_write_val = ppc_md.nvram_write_val;
 198
 199         cntl_b = todc_read_val(todc_info->control_b);
 200
 201         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 202                 if ((cntl_b & 0x70) != 0x20) {
 203                         printk(KERN_INFO "TODC %s %s\n",
 204                                 "real-time-clock was stopped.",
 205                                 "Now starting...");
 206                         cntl_b &= ~0x70;
 207                         cntl_b |= 0x20;
 208                 }
 209
 210                 todc_write_val(todc_info->control_b, cntl_b);
 211         } else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
 212                 u_char mode;
 213
 214                 mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
 215                 /* Make sure countdown clear is not set */
 216                 mode &= ~0x40;
 217                 /* Enable oscillator, extended register set */
 218                 mode |= 0x30;
 219                 todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
 220
 221         } else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
 222                 u_char  month;
 223
 224                 todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
 225                 todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
 226
 227                 month = todc_read_val(todc_info->month);
 228
 229                 if ((month & 0x80) == 0x80) {
 230                         printk(KERN_INFO "TODC %s %s\n",
 231                                 "real-time-clock was stopped.",
 232                                 "Now starting...");
 233                         month &= ~0x80;
 234                         todc_write_val(todc_info->month, month);
 235                 }
 236
 237                 cntl_b &= ~TODC_DS1501_CNTL_B_TE;
 238                 todc_write_val(todc_info->control_b, cntl_b);
 239         } else { /* must be a m48txx type */
 240                 u_char  cntl_a;
 241
 242                 todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
 243                 todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
 244
 245                 cntl_a = todc_read_val(todc_info->control_a);
 246
 247                 /* Check & clear STOP bit in control B register */
 248                 if (cntl_b & TODC_MK48TXX_DAY_CB) {
 249                         printk(KERN_INFO "TODC %s %s\n",
 250                                 "real-time-clock was stopped.",
 251                                 "Now starting...");
 252
 253                         cntl_a |= todc_info->enable_write;
 254                         cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
 255
 256                         todc_write_val(todc_info->control_a, cntl_a);
 257                         todc_write_val(todc_info->control_b, cntl_b);
 258                 }
 259
 260                 /* Make sure READ & WRITE bits are cleared. */
 261                 cntl_a &= ~(todc_info->enable_write |
 262                             todc_info->enable_read);
 263                 todc_write_val(todc_info->control_a, cntl_a);
 264         }
 265
 266         return 0;
 267 }
 268
 269 /*
 270  * There is some ugly stuff in that there are assumptions that for a mc146818,
 271  * the todc_info->control_a has the offset of the mc146818 Register B reg and
 272  * that the register'ss 'SET' bit is the same as the m48txx's write enable
 273  * bit in the control register of the m48txx (i.e., 0x80).
 274  *
 275  * It was done to make the code look simpler.
 276  */
 277 ulong
 278 todc_get_rtc_time(void)
 279 {
 280         uint    year = 0, mon = 0, day = 0, hour = 0, min = 0, sec = 0;
 281         uint    limit, i;
 282         u_char  save_control, uip = 0;
 283
 284         spin_lock(&rtc_lock);
 285         save_control = todc_read_val(todc_info->control_a);
 286
 287         if (todc_info->rtc_type != TODC_TYPE_MC146818) {
 288                 limit = 1;
 289
 290                 switch (todc_info->rtc_type) {
 291                         case TODC_TYPE_DS1557:
 292                         case TODC_TYPE_DS1743:
 293                         case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 294                         case TODC_TYPE_DS1747:
 295                         case TODC_TYPE_DS17285:
 296                                 break;
 297                         default:
 298                                 todc_write_val(todc_info->control_a,
 299                                        (save_control | todc_info->enable_read));
 300                 }
 301         }
 302         else {
 303                 limit = 100000000;
 304         }
 305
 306         for (i=0; i<limit; i++) {
 307                 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 308                         uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
 309                 }
 310
 311                 sec = todc_read_val(todc_info->seconds) & 0x7f;
 312                 min = todc_read_val(todc_info->minutes) & 0x7f;
 313                 hour = todc_read_val(todc_info->hours) & 0x3f;
 314                 day = todc_read_val(todc_info->day_of_month) & 0x3f;
 315                 mon = todc_read_val(todc_info->month) & 0x1f;
 316                 year = todc_read_val(todc_info->year) & 0xff;
 317
 318                 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 319                         uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
 320                         if ((uip & RTC_UIP) == 0) break;
 321                 }
 322         }
 323
 324         if (todc_info->rtc_type != TODC_TYPE_MC146818) {
 325                 switch (todc_info->rtc_type) {
 326                         case TODC_TYPE_DS1557:
 327                         case TODC_TYPE_DS1743:
 328                         case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 329                         case TODC_TYPE_DS1747:
 330                         case TODC_TYPE_DS17285:
 331                                 break;
 332                         default:
 333                                 save_control &= ~(todc_info->enable_read);
 334                                 todc_write_val(todc_info->control_a,
 335                                                        save_control);
 336                 }
 337         }
 338         spin_unlock(&rtc_lock);
 339
 340         if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
 341             ((save_control & RTC_DM_BINARY) == 0) ||
 342             RTC_ALWAYS_BCD) {
 343
 344                 BCD_TO_BIN(sec);
 345                 BCD_TO_BIN(min);
 346                 BCD_TO_BIN(hour);
 347                 BCD_TO_BIN(day);
 348                 BCD_TO_BIN(mon);
 349                 BCD_TO_BIN(year);
 350         }
 351
 352         year = year + 1900;
 353         if (year < 1970) {
 354                 year += 100;
 355         }
 356
 357         return mktime(year, mon, day, hour, min, sec);
 358 }
 359
 360 int
 361 todc_set_rtc_time(unsigned long nowtime)
 362 {
 363         struct rtc_time tm;
 364         u_char          save_control, save_freq_select = 0;
 365
 366         spin_lock(&rtc_lock);
 367         to_tm(nowtime, &tm);
 368
 369         save_control = todc_read_val(todc_info->control_a);
 370
 371         /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
 372         todc_write_val(todc_info->control_a,
 373                                (save_control | todc_info->enable_write));
 374         save_control &= ~(todc_info->enable_write); /* in case it was set */
 375
 376         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 377                 save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
 378                 todc_write_val(todc_info->RTC_FREQ_SELECT,
 379                                        save_freq_select | RTC_DIV_RESET2);
 380         }
 381
 382
 383         tm.tm_year = (tm.tm_year - 1900) % 100;
 384
 385         if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
 386             ((save_control & RTC_DM_BINARY) == 0) ||
 387             RTC_ALWAYS_BCD) {
 388
 389                 BIN_TO_BCD(tm.tm_sec);
 390                 BIN_TO_BCD(tm.tm_min);
 391                 BIN_TO_BCD(tm.tm_hour);
 392                 BIN_TO_BCD(tm.tm_mon);
 393                 BIN_TO_BCD(tm.tm_mday);
 394                 BIN_TO_BCD(tm.tm_year);
 395         }
 396
 397         todc_write_val(todc_info->seconds,      tm.tm_sec);
 398         todc_write_val(todc_info->minutes,      tm.tm_min);
 399         todc_write_val(todc_info->hours,        tm.tm_hour);
 400         todc_write_val(todc_info->month,        tm.tm_mon);
 401         todc_write_val(todc_info->day_of_month, tm.tm_mday);
 402         todc_write_val(todc_info->year,         tm.tm_year);
 403
 404         todc_write_val(todc_info->control_a, save_control);
 405
 406         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 407                 todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
 408         }
 409         spin_unlock(&rtc_lock);
 410
 411         return 0;
 412 }
 413
 414 /*
 415  * Manipulates read bit to reliably read seconds at a high rate.
 416  */
 417 static unsigned char __init todc_read_timereg(int addr)
 418 {
 419         unsigned char save_control = 0, val;
 420
 421         switch (todc_info->rtc_type) {
 422                 case TODC_TYPE_DS1557:
 423                 case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 424                 case TODC_TYPE_DS1747:
 425                 case TODC_TYPE_DS17285:
 426                 case TODC_TYPE_MC146818:
 427                         break;
 428                 default:
 429                         save_control = todc_read_val(todc_info->control_a);
 430                         todc_write_val(todc_info->control_a,
 431                                        (save_control | todc_info->enable_read));
 432         }
 433         val = todc_read_val(addr);
 434
 435         switch (todc_info->rtc_type) {
 436                 case TODC_TYPE_DS1557:
 437                 case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 438                 case TODC_TYPE_DS1747:
 439                 case TODC_TYPE_DS17285:
 440                 case TODC_TYPE_MC146818:
 441                         break;
 442                 default:
 443                         save_control &= ~(todc_info->enable_read);
 444                         todc_write_val(todc_info->control_a, save_control);
 445         }
 446
 447         return val;
 448 }
 449
 450 /*
 451  * This was taken from prep_setup.c
 452  * Use the NVRAM RTC to time a second to calibrate the decrementer.
 453  */
 454 void __init
 455 todc_calibrate_decr(void)
 456 {
 457         ulong   freq;
 458         ulong   tbl, tbu;
 459         long    i, loop_count;
 460         u_char  sec;
 461
 462         todc_time_init();
 463
 464         /*
 465          * Actually this is bad for precision, we should have a loop in
 466          * which we only read the seconds counter. todc_read_val writes
 467          * the address bytes on every call and this takes a lot of time.
 468          * Perhaps an nvram_wait_change method returning a time
 469          * stamp with a loop count as parameter would be the solution.
 470          */
 471         /*
 472          * Need to make sure the tbl doesn't roll over so if tbu increments
 473          * during this test, we need to do it again.
 474          */
 475         loop_count = 0;
 476
 477         sec = todc_read_timereg(todc_info->seconds) & 0x7f;
 478
 479         do {
 480                 tbu = get_tbu();
 481
 482                 for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */
 483                    tbl = get_tbl();
 484
 485                    if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
 486                       break;
 487                    }
 488                 }
 489
 490                 sec = todc_read_timereg(todc_info->seconds) & 0x7f;
 491
 492                 for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */
 493                    freq = get_tbl();
 494
 495                    if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
 496                       break;
 497                    }
 498                 }
 499
 500                 freq -= tbl;
 501         } while ((get_tbu() != tbu) && (++loop_count < 2));
 502
 503         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
 504                freq/1000000, freq%1000000);
 505
 506         tb_ticks_per_jiffy = freq / HZ;
 507         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 508
 509         return;
 510 }