arch/ppc64/kernel/cputable.c

   1 /*
   2  *  arch/ppc64/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/threads.h>
  19 #include <linux/init.h>
  20 #include <asm/cputable.h>
  21
  22 struct cpu_spec* cur_cpu_spec = NULL;
  23
  24 /* NOTE:
  25  * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  26  * the responsibility of the appropriate CPU save/restore functions to
  27  * eventually copy these settings over. Those save/restore aren't yet
  28  * part of the cputable though. That has to be fixed for both ppc32
  29  * and ppc64
  30  */
  31 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  32 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  33 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  34
  35
  36 /* We only set the altivec features if the kernel was compiled with altivec
  37  * support
  38  */
  39 #ifdef CONFIG_ALTIVEC
  40 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
  41 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
  42 #else
  43 #define CPU_FTR_ALTIVEC_COMP    0
  44 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
  45 #endif
  46
  47 struct cpu_spec cpu_specs[] = {
  48     {   /* Power3 */
  49             0xffff0000, 0x00400000, "POWER3 (630)",
  50             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  51                     CPU_FTR_IABR | CPU_FTR_PMC8,
  52             COMMON_USER_PPC64,
  53             128, 128,
  54             __setup_cpu_power3,
  55             COMMON_PPC64_FW
  56     },
  57     {   /* Power3+ */
  58             0xffff0000, 0x00410000, "POWER3 (630+)",
  59             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  60                     CPU_FTR_IABR | CPU_FTR_PMC8,
  61             COMMON_USER_PPC64,
  62             128, 128,
  63             __setup_cpu_power3,
  64             COMMON_PPC64_FW
  65     },
  66     {   /* Northstar */
  67             0xffff0000, 0x00330000, "RS64-II (northstar)",
  68             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  69                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  70             COMMON_USER_PPC64,
  71             128, 128,
  72             __setup_cpu_power3,
  73             COMMON_PPC64_FW
  74     },
  75     {   /* Pulsar */
  76             0xffff0000, 0x00340000, "RS64-III (pulsar)",
  77             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  78                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  79             COMMON_USER_PPC64,
  80             128, 128,
  81             __setup_cpu_power3,
  82             COMMON_PPC64_FW
  83     },
  84     {   /* I-star */
  85             0xffff0000, 0x00360000, "RS64-III (icestar)",
  86             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  87                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  88             COMMON_USER_PPC64,
  89             128, 128,
  90             __setup_cpu_power3,
  91             COMMON_PPC64_FW
  92     },
  93     {   /* S-star */
  94             0xffff0000, 0x00370000, "RS64-IV (sstar)",
  95             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  96                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  97             COMMON_USER_PPC64,
  98             128, 128,
  99             __setup_cpu_power3,
 100             COMMON_PPC64_FW
 101     },
 102     {   /* Power4 */
 103             0xffff0000, 0x00350000, "POWER4 (gp)",
 104             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 105                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 106             COMMON_USER_PPC64,
 107             128, 128,
 108             __setup_cpu_power4,
 109             COMMON_PPC64_FW
 110     },
 111     {   /* Power4+ */
 112             0xffff0000, 0x00380000, "POWER4+ (gq)",
 113             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 114                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 115             COMMON_USER_PPC64,
 116             128, 128,
 117             __setup_cpu_power4,
 118             COMMON_PPC64_FW
 119     },
 120     {   /* PPC970 */
 121             0xffff0000, 0x00390000, "PPC970",
 122             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 123                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 124                     CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 125             COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
 126             128, 128,
 127             __setup_cpu_ppc970,
 128             COMMON_PPC64_FW
 129     },
 130     {   /* PPC970FX */
 131             0xffff0000, 0x003c0000, "PPC970FX",
 132             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 133                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 134                     CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 135             COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
 136             128, 128,
 137             __setup_cpu_ppc970,
 138             COMMON_PPC64_FW
 139     },
 140     {   /* Power5 */
 141             0xffff0000, 0x003a0000, "POWER5 (gr)",
 142             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 143                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 144                     CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE,
 145             COMMON_USER_PPC64,
 146             128, 128,
 147             __setup_cpu_power4,
 148             COMMON_PPC64_FW
 149     },
 150     {   /* Power5 */
 151             0xffff0000, 0x003b0000, "POWER5 (gs)",
 152             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 153                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 154                     CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE,
 155             COMMON_USER_PPC64,
 156             128, 128,
 157             __setup_cpu_power4,
 158             COMMON_PPC64_FW
 159     },
 160     {   /* default match */
 161             0x00000000, 0x00000000, "POWER4 (compatible)",
 162             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 163                     CPU_FTR_PPCAS_ARCH_V2,
 164             COMMON_USER_PPC64,
 165             128, 128,
 166             __setup_cpu_power4,
 167             COMMON_PPC64_FW
 168     }
 169 };
 170
 171 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
 172     {FW_FEATURE_PFT,            "hcall-pft"},
 173     {FW_FEATURE_TCE,            "hcall-tce"},
 174     {FW_FEATURE_SPRG0,          "hcall-sprg0"},
 175     {FW_FEATURE_DABR,           "hcall-dabr"},
 176     {FW_FEATURE_COPY,           "hcall-copy"},
 177     {FW_FEATURE_ASR,            "hcall-asr"},
 178     {FW_FEATURE_DEBUG,          "hcall-debug"},
 179     {FW_FEATURE_PERF,           "hcall-perf"},
 180     {FW_FEATURE_DUMP,           "hcall-dump"},
 181     {FW_FEATURE_INTERRUPT,      "hcall-interrupt"},
 182     {FW_FEATURE_MIGRATE,        "hcall-migrate"},
 183     {FW_FEATURE_PERFMON,        "hcall-perfmon"},
 184     {FW_FEATURE_CRQ,            "hcall-crq"},
 185     {FW_FEATURE_VIO,            "hcall-vio"},
 186     {FW_FEATURE_RDMA,           "hcall-rdma"},
 187     {FW_FEATURE_LLAN,           "hcall-lLAN"},
 188     {FW_FEATURE_BULK,           "hcall-bulk"},
 189     {FW_FEATURE_XDABR,          "hcall-xdabr"},
 190     {FW_FEATURE_MULTITCE,       "hcall-multi-tce"},
 191     {FW_FEATURE_SPLPAR,         "hcall-splpar"},
 192 };