2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #define SECONDARY_PROCESSORS
28 #include <linux/config.h>
29 #include <asm/processor.h>
33 #include <asm/systemcfg.h>
34 #include <asm/ppc_asm.h>
35 #include <asm/offsets.h>
37 #include <asm/cputable.h>
38 #include <asm/setup.h>
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
45 * hcall interface to pSeries LPAR
47 #define HVSC .long 0x44000022
48 #define H_SET_ASR 0x30
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x2fff : pSeries Interrupt prologs
54 * 0x3000 - 0x3fff : Interrupt support
55 * 0x4000 - 0x4fff : NACA
56 * 0x5000 - 0x5fff : SystemCfg
57 * 0x6000 : iSeries and common interrupt prologs
58 * 0x9000 - 0x9fff : Initial segment table
66 * SPRG0 reserved for hypervisor
67 * SPRG1 temp - used to save gpr
68 * SPRG2 temp - used to save gpr
69 * SPRG3 virt addr of paca
73 * Entering into this code we make the following assumptions:
75 * 1. The MMU is off & open firmware is running in real mode.
76 * 2. The kernel is entered at __start
79 * 1. The MMU is on (as it always is for iSeries)
80 * 2. The kernel is entered at SystemReset_Iseries
86 #ifdef CONFIG_PPC_PSERIES
88 /* NOP this out unconditionally */
90 b .__start_initialization_pSeries
93 /* Catch branch to 0 in real mode */
95 #ifdef CONFIG_PPC_ISERIES
97 * At offset 0x20, there is a pointer to iSeries LPAR data.
98 * This is required by the hypervisor
101 .llong hvReleaseData-KERNELBASE
104 * At offset 0x28 and 0x30 are offsets to the msChunks
105 * array (used by the iSeries LPAR debugger to do translation
106 * between physical addresses and absolute addresses) and
107 * to the pidhash table (also used by the debugger)
109 .llong msChunks-KERNELBASE
110 .llong 0 /* pidhash-KERNELBASE SFRXXX */
112 /* Offset 0x38 - Pointer to start of embedded System.map */
113 .globl embedded_sysmap_start
114 embedded_sysmap_start:
116 /* Offset 0x40 - Pointer to end of embedded System.map */
117 .globl embedded_sysmap_end
122 /* Secondary processors spin on this value until it goes to 1. */
123 .globl __secondary_hold_spinloop
124 __secondary_hold_spinloop:
127 /* Secondary processors write this value with their cpu # */
128 /* after they enter the spin loop immediately below. */
129 .globl __secondary_hold_acknowledge
130 __secondary_hold_acknowledge:
135 * The following code is used on pSeries to hold secondary processors
136 * in a spin loop after they have been freed from OpenFirmware, but
137 * before the bulk of the kernel has been relocated. This code
138 * is relocated to physical address 0x60 before prom_init is run.
139 * All of it must fit below the first exception vector at 0x100.
141 _GLOBAL(__secondary_hold)
144 mtmsrd r24 /* RI on */
146 /* Grab our linux cpu number */
149 /* Tell the master cpu we're here */
150 /* Relocation is off & we are located at an address less */
151 /* than 0x100, so only need to grab low order offset. */
152 std r24,__secondary_hold_acknowledge@l(0)
155 /* All secondary cpu's wait here until told to start. */
156 100: ld r4,__secondary_hold_spinloop@l(0)
165 b .pseries_secondary_smp_init
172 /* This value is used to mark exception frames on the stack. */
175 .tc ID_72656773_68657265[TC],0x7265677368657265
179 * The following macros define the code that appears as
180 * the prologue to each of the exception handlers. They
181 * are split into two parts to allow a single kernel binary
182 * to be used for pSeries and iSeries.
183 * LOL. One day... - paulus
187 * We make as much of the exception code common between native
188 * exception handlers (including pSeries LPAR) and iSeries LPAR
189 * implementations as possible.
193 * This is the start of the interrupt handlers for pSeries
194 * This code runs with relocation off.
203 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
207 #define EXCEPTION_PROLOG_PSERIES(area, label) \
208 mfspr r13,SPRG3; /* get paca address into r13 */ \
209 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
210 std r10,area+EX_R10(r13); \
211 std r11,area+EX_R11(r13); \
212 std r12,area+EX_R12(r13); \
214 std r9,area+EX_R13(r13); \
216 clrrdi r12,r13,32; /* get high part of &label */ \
218 mfspr r11,SRR0; /* save SRR0 */ \
219 ori r12,r12,(label)@l; /* virt addr of handler */ \
220 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
222 mfspr r12,SRR1; /* and SRR1 */ \
225 b . /* prevent speculative execution */
228 * This is the start of the interrupt handlers for iSeries
229 * This code runs with relocation on.
231 #define EXCEPTION_PROLOG_ISERIES_1(area) \
232 mfspr r13,SPRG3; /* get paca address into r13 */ \
233 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
234 std r10,area+EX_R10(r13); \
235 std r11,area+EX_R11(r13); \
236 std r12,area+EX_R12(r13); \
238 std r9,area+EX_R13(r13); \
241 #define EXCEPTION_PROLOG_ISERIES_2 \
243 ld r11,PACALPPACA+LPPACASRR0(r13); \
244 ld r12,PACALPPACA+LPPACASRR1(r13); \
245 ori r10,r10,MSR_RI; \
249 * The common exception prolog is used for all except a few exceptions
250 * such as a segment miss on a kernel address. We have to be prepared
251 * to take another exception from the point where we first touch the
252 * kernel stack onwards.
254 * On entry r13 points to the paca, r9-r13 are saved in the paca,
255 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
256 * SRR1, and relocation is on.
258 #define EXCEPTION_PROLOG_COMMON(n, area) \
259 andi. r10,r12,MSR_PR; /* See if coming from user */ \
260 mr r10,r1; /* Save r1 */ \
261 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
263 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
264 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
265 bge- cr1,bad_stack; /* abort if it is */ \
266 std r9,_CCR(r1); /* save CR in stackframe */ \
267 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
268 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
269 std r10,0(r1); /* make stack chain pointer */ \
270 std r0,GPR0(r1); /* save r0 in stackframe */ \
271 std r10,GPR1(r1); /* save r1 in stackframe */ \
272 std r2,GPR2(r1); /* save r2 in stackframe */ \
273 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
274 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
275 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
276 ld r10,area+EX_R10(r13); \
279 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
280 ld r10,area+EX_R12(r13); \
281 ld r11,area+EX_R13(r13); \
285 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
286 mflr r9; /* save LR in stackframe */ \
288 mfctr r10; /* save CTR in stackframe */ \
290 mfspr r11,XER; /* save XER in stackframe */ \
293 std r9,_TRAP(r1); /* set trap number */ \
295 ld r11,exception_marker@toc(r2); \
296 std r10,RESULT(r1); /* clear regs->result */ \
297 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
302 #define STD_EXCEPTION_PSERIES(n, label) \
304 .globl label##_Pseries; \
307 mtspr SPRG1,r13; /* save r13 */ \
308 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
310 #define STD_EXCEPTION_ISERIES(n, label, area) \
311 .globl label##_Iseries; \
314 mtspr SPRG1,r13; /* save r13 */ \
315 EXCEPTION_PROLOG_ISERIES_1(area); \
316 EXCEPTION_PROLOG_ISERIES_2; \
319 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
320 .globl label##_Iseries; \
323 mtspr SPRG1,r13; /* save r13 */ \
324 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
325 lbz r10,PACAPROFENABLED(r13); \
327 bne- label##_Iseries_profile; \
328 label##_Iseries_prof_ret: \
329 lbz r10,PACAPROCENABLED(r13); \
331 beq- label##_Iseries_masked; \
332 EXCEPTION_PROLOG_ISERIES_2; \
334 label##_Iseries_profile: \
335 ld r12,PACALPPACA+LPPACASRR1(r13); \
336 andi. r12,r12,MSR_PR; /* Test if in kernel */ \
337 bne label##_Iseries_prof_ret; \
338 ld r11,PACALPPACA+LPPACASRR0(r13); \
339 ld r12,PACAPROFSTEXT(r13); /* _stext */ \
340 subf r11,r12,r11; /* offset into kernel */ \
341 lwz r12,PACAPROFSHIFT(r13); \
343 lwz r12,PACAPROFLEN(r13); /* profile table length - 1 */ \
344 cmpd r11,r12; /* off end? */ \
346 mr r11,r12; /* force into last entry */ \
347 1: sldi r11,r11,2; /* convert to offset */ \
348 ld r12,PACAPROFBUFFER(r13);/* profile buffer */ \
350 2: lwarx r11,0,r12; /* atomically increment */ \
354 b label##_Iseries_prof_ret
356 #ifdef DO_SOFT_DISABLE
357 #define DISABLE_INTS \
358 lbz r10,PACAPROCENABLED(r13); \
362 stb r11,PACAPROCENABLED(r13); \
363 ori r10,r10,MSR_EE; \
366 #define ENABLE_INTS \
367 lbz r10,PACAPROCENABLED(r13); \
370 ori r11,r11,MSR_EE; \
373 #else /* hard enable/disable interrupts */
376 #define ENABLE_INTS \
379 rlwimi r11,r12,0,MSR_EE; \
384 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
386 .globl label##_common; \
388 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
391 addi r3,r1,STACK_FRAME_OVERHEAD; \
395 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
397 .globl label##_common; \
399 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
401 addi r3,r1,STACK_FRAME_OVERHEAD; \
403 b .ret_from_except_lite
406 * Start of pSeries system interrupt routines
409 .globl __start_interrupts
412 STD_EXCEPTION_PSERIES(0x100, SystemReset)
415 _MachineCheckPseries:
417 mtspr SPRG1,r13 /* save r13 */
418 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
421 .globl DataAccess_Pseries
430 rlwimi r13,r12,16,0x20
433 beq .do_stab_bolted_Pseries
436 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
437 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccess_common)
440 .globl DataAccessSLB_Pseries
441 DataAccessSLB_Pseries:
444 mfspr r13,SPRG3 /* get paca address into r13 */
445 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
446 std r10,PACA_EXSLB+EX_R10(r13)
447 std r11,PACA_EXSLB+EX_R11(r13)
448 std r12,PACA_EXSLB+EX_R12(r13)
449 std r3,PACASLBR3(r13)
451 std r9,PACA_EXSLB+EX_R13(r13)
453 clrrdi r12,r13,32 /* get high part of &label */
455 mfspr r11,SRR0 /* save SRR0 */
456 ori r12,r12,(.do_slb_miss)@l
457 ori r10,r10,MSR_IR|MSR_DR /* DON'T set RI for SLB miss */
459 mfspr r12,SRR1 /* and SRR1 */
463 b . /* prevent speculative execution */
465 STD_EXCEPTION_PSERIES(0x400, InstructionAccess)
468 .globl InstructionAccessSLB_Pseries
469 InstructionAccessSLB_Pseries:
472 mfspr r13,SPRG3 /* get paca address into r13 */
473 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
474 std r10,PACA_EXSLB+EX_R10(r13)
475 std r11,PACA_EXSLB+EX_R11(r13)
476 std r12,PACA_EXSLB+EX_R12(r13)
477 std r3,PACASLBR3(r13)
479 std r9,PACA_EXSLB+EX_R13(r13)
481 clrrdi r12,r13,32 /* get high part of &label */
483 mfspr r11,SRR0 /* save SRR0 */
484 ori r12,r12,(.do_slb_miss)@l
485 ori r10,r10,MSR_IR|MSR_DR /* DON'T set RI for SLB miss */
487 mfspr r12,SRR1 /* and SRR1 */
489 mr r3,r11 /* SRR0 is faulting address */
491 b . /* prevent speculative execution */
493 STD_EXCEPTION_PSERIES(0x500, HardwareInterrupt)
494 STD_EXCEPTION_PSERIES(0x600, Alignment)
495 STD_EXCEPTION_PSERIES(0x700, ProgramCheck)
496 STD_EXCEPTION_PSERIES(0x800, FPUnavailable)
497 STD_EXCEPTION_PSERIES(0x900, Decrementer)
498 STD_EXCEPTION_PSERIES(0xa00, Trap_0a)
499 STD_EXCEPTION_PSERIES(0xb00, Trap_0b)
502 .globl SystemCall_Pseries
510 oris r12,r12,SystemCall_common@h
511 ori r12,r12,SystemCall_common@l
513 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
517 b . /* prevent speculative execution */
519 STD_EXCEPTION_PSERIES(0xd00, SingleStep)
520 STD_EXCEPTION_PSERIES(0xe00, Trap_0e)
522 /* We need to deal with the Altivec unavailable exception
523 * here which is at 0xf20, thus in the middle of the
524 * prolog code of the PerformanceMonitor one. A little
525 * trickery is thus necessary
528 b PerformanceMonitor_Pseries
530 STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable)
532 STD_EXCEPTION_PSERIES(0x1300, InstructionBreakpoint)
533 STD_EXCEPTION_PSERIES(0x1700, AltivecAssist)
535 /* moved from 0xf00 */
536 STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor)
539 _GLOBAL(do_stab_bolted_Pseries)
542 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
545 /* Space for the naca. Architected to be located at real address
546 * NACA_PHYS_ADDR. Various tools rely on this location being fixed.
547 * The first dword of the naca is required by iSeries LPAR to
548 * point to itVpdAreas. On pSeries native, this value is not used.
551 .globl __end_interrupts
555 #ifdef CONFIG_PPC_ISERIES
564 . = SYSTEMCFG_PHYS_ADDR
566 .globl __start_systemcfg
569 . = (SYSTEMCFG_PHYS_ADDR + PAGE_SIZE)
570 .globl __end_systemcfg
573 #ifdef CONFIG_PPC_ISERIES
575 * The iSeries LPAR map is at this fixed address
576 * so that the HvReleaseData structure can address
577 * it with a 32-bit offset.
579 * The VSID values below are dependent on the
580 * VSID generation algorithm. See include/asm/mmu_context.h.
583 .llong 1 /* # ESIDs to be mapped by hypervisor */
584 .llong 1 /* # memory ranges to be mapped by hypervisor */
585 .llong STAB0_PAGE /* Page # of segment table within load area */
586 .llong 0 /* Reserved */
587 .llong 0 /* Reserved */
588 .llong 0 /* Reserved */
589 .llong 0 /* Reserved */
590 .llong 0 /* Reserved */
591 .llong 0x0c00000000 /* ESID to map (Kernel at EA = 0xC000000000000000) */
592 .llong 0x06a99b4b14 /* VSID to map (Kernel at VA = 0x6a99b4b140000000) */
593 .llong 8192 /* # pages to map (32 MB) */
594 .llong 0 /* Offset from start of loadarea to start of map */
595 .llong 0x0006a99b4b140000 /* VPN of first page to map */
599 /*** ISeries-LPAR interrupt handlers ***/
601 STD_EXCEPTION_ISERIES(0x200, MachineCheck, PACA_EXMC)
603 .globl DataAccess_Iseries
611 rlwimi r13,r12,16,0x20
614 beq .do_stab_bolted_Iseries
617 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
618 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
619 EXCEPTION_PROLOG_ISERIES_2
622 .do_stab_bolted_Iseries:
625 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
626 EXCEPTION_PROLOG_ISERIES_2
629 .globl DataAccessSLB_Iseries
630 DataAccessSLB_Iseries:
631 mtspr SPRG1,r13 /* save r13 */
632 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
633 std r3,PACASLBR3(r13)
634 ld r11,PACALPPACA+LPPACASRR0(r13)
635 ld r12,PACALPPACA+LPPACASRR1(r13)
639 STD_EXCEPTION_ISERIES(0x400, InstructionAccess, PACA_EXGEN)
641 .globl InstructionAccessSLB_Iseries
642 InstructionAccessSLB_Iseries:
643 mtspr SPRG1,r13 /* save r13 */
644 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
645 std r3,PACASLBR3(r13)
646 ld r11,PACALPPACA+LPPACASRR0(r13)
647 ld r12,PACALPPACA+LPPACASRR1(r13)
651 MASKABLE_EXCEPTION_ISERIES(0x500, HardwareInterrupt)
652 STD_EXCEPTION_ISERIES(0x600, Alignment, PACA_EXGEN)
653 STD_EXCEPTION_ISERIES(0x700, ProgramCheck, PACA_EXGEN)
654 STD_EXCEPTION_ISERIES(0x800, FPUnavailable, PACA_EXGEN)
655 MASKABLE_EXCEPTION_ISERIES(0x900, Decrementer)
656 STD_EXCEPTION_ISERIES(0xa00, Trap_0a, PACA_EXGEN)
657 STD_EXCEPTION_ISERIES(0xb00, Trap_0b, PACA_EXGEN)
659 .globl SystemCall_Iseries
663 EXCEPTION_PROLOG_ISERIES_2
666 STD_EXCEPTION_ISERIES( 0xd00, SingleStep, PACA_EXGEN)
667 STD_EXCEPTION_ISERIES( 0xe00, Trap_0e, PACA_EXGEN)
668 STD_EXCEPTION_ISERIES( 0xf00, PerformanceMonitor, PACA_EXGEN)
670 .globl SystemReset_Iseries
672 mfspr r13,SPRG3 /* Get paca address */
675 mtmsrd r24 /* RI on */
676 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
677 cmpwi 0,r24,0 /* Are we processor 0? */
678 beq .__start_initialization_iSeries /* Start up the first processor */
680 li r5,RUNLATCH /* Turn off the run light */
687 lbz r23,PACAPROCSTART(r13) /* Test if this processor
690 LOADADDR(r3,current_set)
691 sldi r28,r24,3 /* get current_set[cpu#] */
693 addi r1,r3,THREAD_SIZE
694 subi r1,r1,STACK_FRAME_OVERHEAD
697 beq iseries_secondary_smp_loop /* Loop until told to go */
698 #ifdef SECONDARY_PROCESSORS
699 bne .__secondary_start /* Loop until told to go */
701 iseries_secondary_smp_loop:
702 /* Let the Hypervisor know we are alive */
703 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
705 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
706 #else /* CONFIG_SMP */
707 /* Yield the processor. This is required for non-SMP kernels
708 which are running on multi-threaded machines. */
710 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
711 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
712 li r4,0 /* "yield timed" */
713 li r5,-1 /* "yield forever" */
714 #endif /* CONFIG_SMP */
715 li r0,-1 /* r0=-1 indicates a Hypervisor call */
716 sc /* Invoke the hypervisor via a system call */
717 mfspr r13,SPRG3 /* Put r13 back ???? */
718 b 1b /* If SMP not configured, secondaries
721 .globl Decrementer_Iseries_masked
722 Decrementer_Iseries_masked:
724 stb r11,PACALPPACA+LPPACADECRINT(r13)
725 lwz r12,PACADEFAULTDECR(r13)
729 .globl HardwareInterrupt_Iseries_masked
730 HardwareInterrupt_Iseries_masked:
731 mtcrf 0x80,r9 /* Restore regs */
732 ld r11,PACALPPACA+LPPACASRR0(r13)
733 ld r12,PACALPPACA+LPPACASRR1(r13)
736 ld r9,PACA_EXGEN+EX_R9(r13)
737 ld r10,PACA_EXGEN+EX_R10(r13)
738 ld r11,PACA_EXGEN+EX_R11(r13)
739 ld r12,PACA_EXGEN+EX_R12(r13)
740 ld r13,PACA_EXGEN+EX_R13(r13)
742 b . /* prevent speculative execution */
746 * Data area reserved for FWNMI option.
749 .globl fwnmi_data_area
753 * Vectors for the FWNMI option. Share common code.
756 .globl SystemReset_FWNMI
759 mtspr SPRG1,r13 /* save r13 */
760 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, SystemReset_common)
761 .globl MachineCheck_FWNMI
764 mtspr SPRG1,r13 /* save r13 */
765 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
768 * Space for the initial segment table
769 * For LPAR, the hypervisor must fill in at least one entry
770 * before we get control (with relocate on)
776 . = (STAB0_PHYS_ADDR + PAGE_SIZE)
781 /*** Common interrupt handlers ***/
783 STD_EXCEPTION_COMMON(0x100, SystemReset, .SystemResetException)
786 * Machine check is different because we use a different
787 * save area: PACA_EXMC instead of PACA_EXGEN.
790 .globl MachineCheck_common
792 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
795 addi r3,r1,STACK_FRAME_OVERHEAD
796 bl .MachineCheckException
799 STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt)
800 STD_EXCEPTION_COMMON(0xa00, Trap_0a, .UnknownException)
801 STD_EXCEPTION_COMMON(0xb00, Trap_0b, .UnknownException)
802 STD_EXCEPTION_COMMON(0xd00, SingleStep, .SingleStepException)
803 STD_EXCEPTION_COMMON(0xe00, Trap_0e, .UnknownException)
804 STD_EXCEPTION_COMMON(0xf00, PerformanceMonitor, .PerformanceMonitorException)
805 STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException)
806 #ifdef CONFIG_ALTIVEC
807 STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException)
809 STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException)
813 * Here we have detected that the kernel stack pointer is bad.
814 * R9 contains the saved CR, r13 points to the paca,
815 * r10 contains the (bad) kernel stack pointer,
816 * r11 and r12 contain the saved SRR0 and SRR1.
817 * We switch to using the paca guard page as an emergency stack,
818 * save the registers there, and call kernel_bad_stack(), which panics.
821 ld r1,PACAEMERGSP(r13)
822 subi r1,r1,64+INT_FRAME_SIZE
843 addi r11,r1,INT_FRAME_SIZE
848 1: addi r3,r1,STACK_FRAME_OVERHEAD
853 * Return from an exception with minimal checks.
854 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
855 * If interrupts have been enabled, or anything has been
856 * done that might have changed the scheduling status of
857 * any task or sent any task a signal, you should use
858 * ret_from_except or ret_from_except_lite instead of this.
860 fast_exception_return:
863 andi. r3,r12,MSR_RI /* check if RI is set */
877 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
885 b . /* prevent speculative execution */
889 1: addi r3,r1,STACK_FRAME_OVERHEAD
890 bl .unrecoverable_exception
894 * Here r13 points to the paca, r9 contains the saved CR,
895 * SRR0 and SRR1 are saved in r11 and r12,
896 * r9 - r13 are saved in paca->exgen.
899 .globl DataAccess_common
902 std r10,PACA_EXGEN+EX_DAR(r13)
904 stw r10,PACA_EXGEN+EX_DSISR(r13)
905 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
906 ld r3,PACA_EXGEN+EX_DAR(r13)
907 lwz r4,PACA_EXGEN+EX_DSISR(r13)
909 b .do_hash_page /* Try to handle as hpte fault */
912 .globl InstructionAccess_common
913 InstructionAccess_common:
914 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
918 b .do_hash_page /* Try to handle as hpte fault */
921 .globl HardwareInterrupt_common
922 .globl HardwareInterrupt_entry
923 HardwareInterrupt_common:
924 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
925 HardwareInterrupt_entry:
927 addi r3,r1,STACK_FRAME_OVERHEAD
929 b .ret_from_except_lite
932 .globl Alignment_common
935 std r10,PACA_EXGEN+EX_DAR(r13)
937 stw r10,PACA_EXGEN+EX_DSISR(r13)
938 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
939 ld r3,PACA_EXGEN+EX_DAR(r13)
940 lwz r4,PACA_EXGEN+EX_DSISR(r13)
944 addi r3,r1,STACK_FRAME_OVERHEAD
946 bl .AlignmentException
950 .globl ProgramCheck_common
952 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
954 addi r3,r1,STACK_FRAME_OVERHEAD
956 bl .ProgramCheckException
960 .globl FPUnavailable_common
961 FPUnavailable_common:
962 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
963 bne .load_up_fpu /* if from user, just load it up */
965 addi r3,r1,STACK_FRAME_OVERHEAD
967 bl .KernelFPUnavailableException
971 .globl AltivecUnavailable_common
972 AltivecUnavailable_common:
973 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
974 #ifdef CONFIG_ALTIVEC
975 bne .load_up_altivec /* if from user, just load it up */
978 addi r3,r1,STACK_FRAME_OVERHEAD
980 bl .AltivecUnavailableException
987 _GLOBAL(do_hash_page)
991 andis. r0,r4,0xa450 /* weird error? */
992 bne- .handle_page_fault /* if not, try to insert a HPTE */
994 andis. r0,r4,0x0020 /* Is it a segment table fault? */
995 bne- .do_ste_alloc /* If so handle it */
996 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
999 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1000 * accessing a userspace segment (even from the kernel). We assume
1001 * kernel addresses always have the high bit set.
1003 rlwinm r4,r4,32-23,29,29 /* DSISR_STORE -> _PAGE_RW */
1004 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1005 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1006 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1007 ori r4,r4,1 /* add _PAGE_PRESENT */
1010 * On iSeries, we soft-disable interrupts here, then
1011 * hard-enable interrupts so that the hash_page code can spin on
1012 * the hash_table_lock without problems on a shared processor.
1017 * r3 contains the faulting address
1018 * r4 contains the required access permissions
1019 * r5 contains the trap number
1021 * at return r3 = 0 for success
1023 bl .hash_page /* build HPTE if possible */
1024 cmpdi r3,0 /* see if hash_page succeeded */
1026 #ifdef DO_SOFT_DISABLE
1028 * If we had interrupts soft-enabled at the point where the
1029 * DSI/ISI occurred, and an interrupt came in during hash_page,
1031 * We jump to ret_from_except_lite rather than fast_exception_return
1032 * because ret_from_except_lite will check for and handle pending
1033 * interrupts if necessary.
1035 beq .ret_from_except_lite
1037 * hash_page couldn't handle it, set soft interrupt enable back
1038 * to what it was before the trap. Note that .local_irq_restore
1039 * handles any interrupts pending at this point.
1042 bl .local_irq_restore
1045 beq fast_exception_return /* Return from exception on success */
1049 /* Here we have a page fault that hash_page can't handle. */
1050 _GLOBAL(handle_page_fault)
1054 addi r3,r1,STACK_FRAME_OVERHEAD
1057 beq+ .ret_from_except_lite
1060 addi r3,r1,STACK_FRAME_OVERHEAD
1065 /* here we have a segment miss */
1066 _GLOBAL(do_ste_alloc)
1067 bl .ste_allocate /* try to insert stab entry */
1069 beq+ fast_exception_return
1070 b .handle_page_fault
1073 * r13 points to the PACA, r9 contains the saved CR,
1074 * r11 and r12 contain the saved SRR0 and SRR1.
1075 * r9 - r13 are saved in paca->exslb.
1076 * We assume we aren't going to take any exceptions during this procedure.
1077 * We assume (DAR >> 60) == 0xc.
1080 _GLOBAL(do_stab_bolted)
1081 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1082 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1084 /* Hash to the primary group */
1085 ld r10,PACASTABVIRT(r13)
1088 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1090 /* Calculate VSID */
1091 /* (((ea >> 28) & 0x1fff) << 15) | (ea >> 60) */
1095 /* VSID_RANDOMIZER */
1102 rldic r9,r9,12,16 /* r9 = vsid << 12 */
1104 /* Search the primary group for a free entry */
1105 1: ld r11,0(r10) /* Test valid bit of the current ste */
1112 /* Stick for only searching the primary group for now. */
1113 /* At least for now, we use a very simple random castout scheme */
1114 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1116 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1119 /* r10 currently points to an ste one past the group of interest */
1120 /* make it point to the randomly selected entry */
1122 or r10,r10,r11 /* r10 is the entry to invalidate */
1124 isync /* mark the entry invalid */
1126 rldicl r11,r11,56,1 /* clear the valid bit */
1131 clrrdi r11,r11,28 /* Get the esid part of the ste */
1134 2: std r9,8(r10) /* Store the vsid part of the ste */
1137 mfspr r11,DAR /* Get the new esid */
1138 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1139 ori r11,r11,0x90 /* Turn on valid and kp */
1140 std r11,0(r10) /* Put new entry back into the stab */
1144 /* All done -- return from exception. */
1145 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1146 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1148 andi. r10,r12,MSR_RI
1151 mtcrf 0x80,r9 /* restore CR */
1159 ld r9,PACA_EXSLB+EX_R9(r13)
1160 ld r10,PACA_EXSLB+EX_R10(r13)
1161 ld r11,PACA_EXSLB+EX_R11(r13)
1162 ld r12,PACA_EXSLB+EX_R12(r13)
1163 ld r13,PACA_EXSLB+EX_R13(r13)
1165 b . /* prevent speculative execution */
1168 * r13 points to the PACA, r9 contains the saved CR,
1169 * r11 and r12 contain the saved SRR0 and SRR1.
1170 * r3 has the faulting address
1171 * r9 - r13 are saved in paca->exslb.
1172 * r3 is saved in paca->slb_r3
1173 * We assume we aren't going to take any exceptions during this procedure.
1175 _GLOBAL(do_slb_miss)
1178 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1179 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1180 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1182 bl .slb_allocate /* handle it */
1184 /* All done -- return from exception. */
1186 ld r10,PACA_EXSLB+EX_LR(r13)
1187 ld r3,PACASLBR3(r13)
1188 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1189 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1193 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1199 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1204 ld r9,PACA_EXSLB+EX_R9(r13)
1205 ld r10,PACA_EXSLB+EX_R10(r13)
1206 ld r11,PACA_EXSLB+EX_R11(r13)
1207 ld r12,PACA_EXSLB+EX_R12(r13)
1208 ld r13,PACA_EXSLB+EX_R13(r13)
1210 b . /* prevent speculative execution */
1213 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1216 1: addi r3,r1,STACK_FRAME_OVERHEAD
1217 bl .unrecoverable_exception
1222 * On pSeries, secondary processors spin in the following code.
1223 * At entry, r3 = this processor's number (in Linux terms, not hardware).
1225 _GLOBAL(pseries_secondary_smp_init)
1226 /* turn on 64-bit mode */
1230 /* Set up a paca value for this processor. */
1231 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1232 mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
1233 add r13,r13,r24 /* for this processor. */
1235 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1236 mr r24,r3 /* __secondary_start needs cpu# */
1240 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1244 /* Create a temp kernel stack for use before relocation is on. */
1245 ld r1,PACAEMERGSP(r13)
1246 subi r1,r1,STACK_FRAME_OVERHEAD
1250 #ifdef SECONDARY_PROCESSORS
1251 bne .__secondary_start
1254 b 1b /* Loop until told to go */
1255 #ifdef CONFIG_PPC_ISERIES
1256 _GLOBAL(__start_initialization_iSeries)
1257 /* Clear out the BSS */
1258 LOADADDR(r11,__bss_stop)
1260 LOADADDR(r8,__bss_start)
1262 sub r11,r11,r8 /* bss size */
1263 addi r11,r11,7 /* round up to an even double word */
1264 rldicl. r11,r11,61,3 /* shift right by 3 */
1268 mtctr r11 /* zero this many doublewords */
1272 LOADADDR(r1,init_thread_union)
1273 addi r1,r1,THREAD_SIZE
1275 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1277 LOADADDR(r3,cpu_specs)
1278 LOADADDR(r4,cur_cpu_spec)
1282 LOADADDR(r2,__toc_start)
1286 LOADADDR(r9,systemcfg)
1287 SET_REG_TO_CONST(r4, SYSTEMCFG_VIRT_ADDR)
1288 std r4,0(r9) /* set the systemcfg pointer */
1291 SET_REG_TO_CONST(r4, NACA_VIRT_ADDR)
1292 std r4,0(r9) /* set the naca pointer */
1294 /* Get the pointer to the segment table */
1295 ld r6,PACA(r4) /* Get the base paca pointer */
1296 ld r4,PACASTABVIRT(r6)
1298 bl .iSeries_fixup_klimit
1300 /* relocation is on at this point */
1302 b .start_here_common
1305 #ifdef CONFIG_PPC_PSERIES
1309 andi. r0,r3,MSR_IR|MSR_DR
1316 b . /* prevent speculative execution */
1317 _GLOBAL(__start_initialization_pSeries)
1318 mr r31,r3 /* save parameters */
1326 /* put a relocation offset into r3 */
1329 LOADADDR(r2,__toc_start)
1333 /* Relocate the TOC from a virt addr to a real addr */
1336 /* Save parameters */
1343 /* Do all of the interaction with OF client interface */
1345 mr r23,r3 /* Save phys address we are running at */
1347 /* Setup some critical 970 SPRs before switching MMU off */
1348 bl .__970_cpu_preinit
1350 li r24,0 /* cpu # */
1352 /* Switch off MMU if not already */
1353 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1358 * At this point, r3 contains the physical address we are running at,
1359 * returned by prom_init()
1361 _STATIC(__after_prom_start)
1364 * We need to run with __start at physical address 0.
1365 * This will leave some code in the first 256B of
1366 * real memory, which are reserved for software use.
1367 * The remainder of the first page is loaded with the fixed
1368 * interrupt vectors. The next two pages are filled with
1369 * unknown exception placeholders.
1371 * Note: This process overwrites the OF exception vectors.
1372 * r26 == relocation offset
1377 SET_REG_TO_CONST(r27,KERNELBASE)
1379 li r3,0 /* target addr */
1381 // XXX FIXME: Use phys returned by OF (r23)
1382 sub r4,r27,r26 /* source addr */
1383 /* current address of _start */
1384 /* i.e. where we are running */
1385 /* the source addr */
1387 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1390 li r6,0x100 /* Start offset, the first 0x100 */
1391 /* bytes were copied earlier. */
1393 bl .copy_and_flush /* copy the first n bytes */
1394 /* this includes the code being */
1395 /* executed here. */
1397 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1398 mtctr r0 /* that we just made/relocated */
1401 4: LOADADDR(r5,klimit)
1403 ld r5,0(r5) /* get the value of klimit */
1405 bl .copy_and_flush /* copy the rest */
1406 b .start_here_pSeries
1410 * Copy routine used to copy the kernel to start at physical address 0
1411 * and flush and invalidate the caches as needed.
1412 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1413 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1415 * Note: this routine *only* clobbers r0, r6 and lr
1417 _GLOBAL(copy_and_flush)
1420 4: li r0,16 /* Use the least common */
1421 /* denominator cache line */
1422 /* size. This results in */
1423 /* extra cache line flushes */
1424 /* but operation is correct. */
1425 /* Can't get cache line size */
1426 /* from NACA as it is being */
1429 mtctr r0 /* put # words/line in ctr */
1430 3: addi r6,r6,8 /* copy a cache line */
1434 dcbst r6,r3 /* write it to memory */
1436 icbi r6,r3 /* flush the icache line */
1448 * load_up_fpu(unused, unused, tsk)
1449 * Disable FP for the task which had the FPU previously,
1450 * and save its floating-point registers in its thread_struct.
1451 * Enables the FPU for use in the kernel on return.
1452 * On SMP we know the fpu is free, since we give it up every
1453 * switch (ie, no lazy save of the FP registers).
1454 * On entry: r13 == 'current' && last_task_used_math != 'current'
1456 _STATIC(load_up_fpu)
1457 mfmsr r5 /* grab the current MSR */
1459 mtmsrd r5 /* enable use of fpu now */
1462 * For SMP, we don't do lazy FPU switching because it just gets too
1463 * horrendously complex, especially when a task switches from one CPU
1464 * to another. Instead we call giveup_fpu in switch_to.
1468 ld r3,last_task_used_math@got(r2)
1472 /* Save FP state to last_task_used_math's THREAD struct */
1476 stfd fr0,THREAD_FPSCR(r4)
1477 /* Disable FP for last_task_used_math */
1479 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1480 li r6,MSR_FP|MSR_FE0|MSR_FE1
1482 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1484 #endif /* CONFIG_SMP */
1485 /* enable use of FP after return */
1486 ld r4,PACACURRENT(r13)
1487 addi r5,r4,THREAD /* Get THREAD */
1488 ld r4,THREAD_FPEXC_MODE(r5)
1492 lfd fr0,THREAD_FPSCR(r5)
1496 /* Update last_task_used_math to 'current' */
1497 subi r4,r5,THREAD /* Back to 'current' */
1499 #endif /* CONFIG_SMP */
1500 /* restore registers and return */
1501 b fast_exception_return
1504 * disable_kernel_fp()
1507 _GLOBAL(disable_kernel_fp)
1509 rldicl r0,r3,(63-MSR_FP_LG),1
1510 rldicl r3,r0,(MSR_FP_LG+1),0
1511 mtmsrd r3 /* disable use of fpu now */
1517 * Disable FP for the task given as the argument,
1518 * and save the floating-point registers in its thread_struct.
1519 * Enables the FPU for use in the kernel on return.
1524 mtmsrd r5 /* enable use of fpu now */
1527 beqlr- /* if no previous owner, done */
1528 addi r3,r3,THREAD /* want THREAD of task */
1533 stfd fr0,THREAD_FPSCR(r3)
1535 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1536 li r3,MSR_FP|MSR_FE0|MSR_FE1
1537 andc r4,r4,r3 /* disable FP for previous task */
1538 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1542 ld r4,last_task_used_math@got(r2)
1544 #endif /* CONFIG_SMP */
1548 #ifdef CONFIG_ALTIVEC
1551 * load_up_altivec(unused, unused, tsk)
1552 * Disable VMX for the task which had it previously,
1553 * and save its vector registers in its thread_struct.
1554 * Enables the VMX for use in the kernel on return.
1555 * On SMP we know the VMX is free, since we give it up every
1556 * switch (ie, no lazy save of the vector registers).
1557 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1559 _STATIC(load_up_altivec)
1560 mfmsr r5 /* grab the current MSR */
1561 oris r5,r5,MSR_VEC@h
1562 mtmsrd r5 /* enable use of VMX now */
1566 * For SMP, we don't do lazy VMX switching because it just gets too
1567 * horrendously complex, especially when a task switches from one CPU
1568 * to another. Instead we call giveup_altvec in switch_to.
1569 * VRSAVE isn't dealt with here, that is done in the normal context
1570 * switch code. Note that we could rely on vrsave value to eventually
1571 * avoid saving all of the VREGs here...
1574 ld r3,last_task_used_altivec@got(r2)
1578 /* Save VMX state to last_task_used_altivec's THREAD struct */
1584 /* Disable VMX for last_task_used_altivec */
1586 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1589 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1591 #endif /* CONFIG_SMP */
1592 /* Hack: if we get an altivec unavailable trap with VRSAVE
1593 * set to all zeros, we assume this is a broken application
1594 * that fails to set it properly, and thus we switch it to
1597 mfspr r4,SPRN_VRSAVE
1601 mtspr SPRN_VRSAVE,r4
1603 /* enable use of VMX after return */
1604 ld r4,PACACURRENT(r13)
1605 addi r5,r4,THREAD /* Get THREAD */
1606 oris r12,r12,MSR_VEC@h
1610 stw r4,THREAD_USED_VR(r5)
1614 /* Update last_task_used_math to 'current' */
1615 subi r4,r5,THREAD /* Back to 'current' */
1617 #endif /* CONFIG_SMP */
1618 /* restore registers and return */
1619 b fast_exception_return
1622 * disable_kernel_altivec()
1625 _GLOBAL(disable_kernel_altivec)
1627 rldicl r0,r3,(63-MSR_VEC_LG),1
1628 rldicl r3,r0,(MSR_VEC_LG+1),0
1629 mtmsrd r3 /* disable use of VMX now */
1634 * giveup_altivec(tsk)
1635 * Disable VMX for the task given as the argument,
1636 * and save the vector registers in its thread_struct.
1637 * Enables the VMX for use in the kernel on return.
1639 _GLOBAL(giveup_altivec)
1641 oris r5,r5,MSR_VEC@h
1642 mtmsrd r5 /* enable use of VMX now */
1645 beqlr- /* if no previous owner, done */
1646 addi r3,r3,THREAD /* want THREAD of task */
1654 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1656 andc r4,r4,r3 /* disable FP for previous task */
1657 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1661 ld r4,last_task_used_altivec@got(r2)
1663 #endif /* CONFIG_SMP */
1666 #endif /* CONFIG_ALTIVEC */
1669 #ifdef CONFIG_PPC_PMAC
1671 * On PowerMac, secondary processors starts from the reset vector, which
1672 * is temporarily turned into a call to one of the functions below.
1677 .globl pmac_secondary_start_1
1678 pmac_secondary_start_1:
1680 b .pmac_secondary_start
1682 .globl pmac_secondary_start_2
1683 pmac_secondary_start_2:
1685 b .pmac_secondary_start
1687 .globl pmac_secondary_start_3
1688 pmac_secondary_start_3:
1690 b .pmac_secondary_start
1692 _GLOBAL(pmac_secondary_start)
1693 /* turn on 64-bit mode */
1697 /* Copy some CPU settings from CPU 0 */
1698 bl .__restore_cpu_setup
1700 /* pSeries do that early though I don't think we really need it */
1703 mtmsrd r3 /* RI on */
1705 /* Set up a paca value for this processor. */
1706 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1707 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1708 add r13,r13,r4 /* for this processor. */
1709 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1711 /* Create a temp kernel stack for use before relocation is on. */
1712 ld r1,PACAEMERGSP(r13)
1713 subi r1,r1,STACK_FRAME_OVERHEAD
1715 b .__secondary_start
1717 #endif /* CONFIG_PPC_PMAC */
1720 * This function is called after the master CPU has released the
1721 * secondary processors. The execution environment is relocation off.
1722 * The paca for this processor has the following fields initialized at
1724 * 1. Processor number
1725 * 2. Segment table pointer (virtual address)
1726 * On entry the following are set:
1727 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1728 * r24 = cpu# (in Linux terms)
1729 * r13 = paca virtual address
1730 * SPRG3 = paca virtual address
1732 _GLOBAL(__secondary_start)
1734 HMT_MEDIUM /* Set thread priority to MEDIUM */
1738 stb r6,PACAPROCENABLED(r13)
1740 #ifndef CONFIG_PPC_ISERIES
1741 /* Initialize the page table pointer register. */
1743 ld r6,0(r6) /* get the value of _SDR1 */
1744 mtspr SDR1,r6 /* set the htab location */
1746 /* Initialize the first segment table (or SLB) entry */
1747 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1750 /* Initialize the kernel stack. Just a repeat for iSeries. */
1751 LOADADDR(r3,current_set)
1752 sldi r28,r24,3 /* get current_set[cpu#] */
1754 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1755 std r1,PACAKSAVE(r13)
1757 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1758 ori r4,r3,1 /* turn on valid bit */
1760 #ifdef CONFIG_PPC_ISERIES
1761 li r0,-1 /* hypervisor call */
1763 sldi r3,r3,63 /* 0x8000000000000000 */
1764 ori r3,r3,4 /* 0x8000000000000004 */
1765 sc /* HvCall_setASR */
1768 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1769 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1770 cmpldi r3,PLATFORM_PSERIES_LPAR
1774 cmpwi r3,0x37 /* SStar */
1776 cmpwi r3,0x36 /* IStar */
1778 cmpwi r3,0x34 /* Pulsar */
1780 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1781 HVSC /* Invoking hcall */
1783 98: /* !(rpa hypervisor) || !(star) */
1784 mtasr r4 /* set the stab location */
1790 /* enable MMU and jump to start_secondary */
1791 LOADADDR(r3,.start_secondary_prolog)
1792 SET_REG_TO_CONST(r4, MSR_KERNEL)
1793 #ifdef DO_SOFT_DISABLE
1799 b . /* prevent speculative execution */
1802 * Running with relocation on at this point. All we want to do is
1803 * zero the stack back-chain pointer before going into C code.
1805 _GLOBAL(start_secondary_prolog)
1807 std r3,0(r1) /* Zero the stack frame pointer */
1812 * This subroutine clobbers r11 and r12
1814 _GLOBAL(enable_64b_mode)
1815 mfmsr r11 /* grab the current MSR */
1817 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1820 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1826 #ifdef CONFIG_PPC_PSERIES
1828 * This is where the main kernel code starts.
1830 _STATIC(start_here_pSeries)
1831 /* get a new offset, now that the kernel has moved. */
1837 mtmsrd r6 /* RI on */
1839 /* setup the systemcfg pointer which is needed by *tab_initialize */
1840 LOADADDR(r6,systemcfg)
1841 sub r6,r6,r26 /* addr of the variable systemcfg */
1842 li r27,SYSTEMCFG_PHYS_ADDR
1843 std r27,0(r6) /* set the value of systemcfg */
1845 /* setup the naca pointer which is needed by *tab_initialize */
1847 sub r6,r6,r26 /* addr of the variable naca */
1848 li r27,NACA_PHYS_ADDR
1849 std r27,0(r6) /* set the value of naca */
1852 /* Start up the second thread on cpu 0 */
1855 cmpwi r3,0x34 /* Pulsar */
1857 cmpwi r3,0x36 /* Icestar */
1859 cmpwi r3,0x37 /* SStar */
1861 b 91f /* HMT not supported */
1863 bl .hmt_start_secondary
1868 /* All secondary cpus are now spinning on a common
1869 * spinloop, release them all now so they can start
1870 * to spin on their individual paca spinloops.
1871 * For non SMP kernels, the secondary cpus never
1872 * get out of the common spinloop.
1875 LOADADDR(r5,__secondary_hold_spinloop)
1880 /* The following gets the stack and TOC set up with the regs */
1881 /* pointing to the real addr of the kernel stack. This is */
1882 /* all done to support the C function call below which sets */
1883 /* up the htab. This is done because we have relocated the */
1884 /* kernel but are still running in real mode. */
1886 LOADADDR(r3,init_thread_union)
1889 /* set up a stack pointer (physical address) */
1890 addi r1,r3,THREAD_SIZE
1892 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1894 /* set up the TOC (physical address) */
1895 LOADADDR(r2,__toc_start)
1900 LOADADDR(r3,cpu_specs)
1902 LOADADDR(r4,cur_cpu_spec)
1907 /* Get the pointer to the segment table which is used by */
1908 /* stab_initialize */
1909 LOADADDR(r27, boot_cpuid)
1913 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1914 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1915 add r13,r13,r24 /* for this processor. */
1916 sub r13,r13,r26 /* convert to physical addr */
1918 mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
1919 ld r3,PACASTABREAL(r13)
1920 ori r4,r3,1 /* turn on valid bit */
1923 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1924 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1925 cmpldi r3,PLATFORM_PSERIES_LPAR
1929 cmpwi r3,0x37 /* SStar */
1931 cmpwi r3,0x36 /* IStar */
1933 cmpwi r3,0x34 /* Pulsar */
1935 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1936 HVSC /* Invoking hcall */
1938 98: /* !(rpa hypervisor) || !(star) */
1939 mtasr r4 /* set the stab location */
1942 ld r3,PACASTABREAL(r6) /* restore r3 for stab_initialize */
1944 /* Initialize an initial memory mapping and turn on relocation. */
1948 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1949 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1950 /* Test if bit 0 is set (LPAR bit) */
1953 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1955 ld r6,0(r6) /* get the value of _SDR1 */
1956 mtspr SDR1,r6 /* set the htab location */
1958 LOADADDR(r3,.start_here_common)
1959 SET_REG_TO_CONST(r4, MSR_KERNEL)
1963 b . /* prevent speculative execution */
1964 #endif /* CONFIG_PPC_PSERIES */
1966 /* This is where all platforms converge execution */
1967 _STATIC(start_here_common)
1968 /* relocation is on at this point */
1970 /* The following code sets up the SP and TOC now that we are */
1971 /* running with translation enabled. */
1973 LOADADDR(r3,init_thread_union)
1975 /* set up the stack */
1976 addi r1,r3,THREAD_SIZE
1978 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1980 /* Apply the CPUs-specific fixups (nop out sections not relevant
1984 bl .do_cpu_ftr_fixups
1986 /* setup the systemcfg pointer */
1987 LOADADDR(r9,systemcfg)
1988 SET_REG_TO_CONST(r8, SYSTEMCFG_VIRT_ADDR)
1991 /* setup the naca pointer */
1993 SET_REG_TO_CONST(r8, NACA_VIRT_ADDR)
1994 std r8,0(r9) /* set the value of the naca ptr */
1996 LOADADDR(r26, boot_cpuid)
1999 LOADADDR(r24, paca) /* Get base vaddr of paca array */
2000 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
2001 add r13,r13,r24 /* for this processor. */
2004 /* ptr to current */
2005 LOADADDR(r4,init_task)
2006 std r4,PACACURRENT(r13)
2010 std r1,PACAKSAVE(r13)
2012 /* Restore the parms passed in from the bootloader. */
2021 /* Load up the kernel context */
2023 #ifdef DO_SOFT_DISABLE
2025 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
2027 ori r5,r5,MSR_EE /* Hard Enabled */
2033 _GLOBAL(__setup_cpu_power3)
2038 LOADADDR(r5, hmt_thread_data)
2041 cmpwi r7,0x34 /* Pulsar */
2043 cmpwi r7,0x36 /* Icestar */
2045 cmpwi r7,0x37 /* SStar */
2055 bl .hmt_start_secondary
2058 __hmt_secondary_hold:
2059 LOADADDR(r5, hmt_thread_data)
2069 93: andi. r6,r6,0x3f
2083 b .pseries_secondary_smp_init
2086 _GLOBAL(hmt_start_secondary)
2087 LOADADDR(r4,__hmt_secondary_hold)
2109 * We put a few things here that have to be page-aligned.
2110 * This stuff goes at the beginning of the data segment,
2111 * which is page-aligned.
2117 .globl empty_zero_page
2121 .globl swapper_pg_dir
2129 /* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
2135 * This space gets a copy of optional info passed to us by the bootstrap
2136 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2140 .space COMMAND_LINE_SIZE