2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #define SECONDARY_PROCESSORS
28 #include <linux/config.h>
29 #include <linux/threads.h>
30 #include <asm/processor.h>
34 #include <asm/systemcfg.h>
35 #include <asm/ppc_asm.h>
36 #include <asm/offsets.h>
38 #include <asm/cputable.h>
39 #include <asm/setup.h>
41 #ifdef CONFIG_PPC_ISERIES
42 #define DO_SOFT_DISABLE
46 * hcall interface to pSeries LPAR
48 #define HVSC .long 0x44000022
49 #define H_SET_ASR 0x30
52 * We layout physical memory as follows:
53 * 0x0000 - 0x00ff : Secondary processor spin code
54 * 0x0100 - 0x2fff : pSeries Interrupt prologs
55 * 0x3000 - 0x3fff : Interrupt support
56 * 0x4000 - 0x4fff : NACA
57 * 0x5000 - 0x5fff : SystemCfg
58 * 0x6000 : iSeries and common interrupt prologs
59 * 0x9000 - 0x9fff : Initial segment table
67 * SPRG0 reserved for hypervisor
68 * SPRG1 temp - used to save gpr
69 * SPRG2 temp - used to save gpr
70 * SPRG3 virt addr of paca
74 * Entering into this code we make the following assumptions:
76 * 1. The MMU is off & open firmware is running in real mode.
77 * 2. The kernel is entered at __start
80 * 1. The MMU is on (as it always is for iSeries)
81 * 2. The kernel is entered at system_reset_iSeries
87 #ifdef CONFIG_PPC_MULTIPLATFORM
89 /* NOP this out unconditionally */
91 b .__start_initialization_multiplatform
93 #endif /* CONFIG_PPC_MULTIPLATFORM */
95 /* Catch branch to 0 in real mode */
97 #ifdef CONFIG_PPC_ISERIES
99 * At offset 0x20, there is a pointer to iSeries LPAR data.
100 * This is required by the hypervisor
103 .llong hvReleaseData-KERNELBASE
106 * At offset 0x28 and 0x30 are offsets to the msChunks
107 * array (used by the iSeries LPAR debugger to do translation
108 * between physical addresses and absolute addresses) and
109 * to the pidhash table (also used by the debugger)
111 .llong msChunks-KERNELBASE
112 .llong 0 /* pidhash-KERNELBASE SFRXXX */
114 /* Offset 0x38 - Pointer to start of embedded System.map */
115 .globl embedded_sysmap_start
116 embedded_sysmap_start:
118 /* Offset 0x40 - Pointer to end of embedded System.map */
119 .globl embedded_sysmap_end
123 #else /* CONFIG_PPC_ISERIES */
125 /* Secondary processors spin on this value until it goes to 1. */
126 .globl __secondary_hold_spinloop
127 __secondary_hold_spinloop:
130 /* Secondary processors write this value with their cpu # */
131 /* after they enter the spin loop immediately below. */
132 .globl __secondary_hold_acknowledge
133 __secondary_hold_acknowledge:
138 * The following code is used on pSeries to hold secondary processors
139 * in a spin loop after they have been freed from OpenFirmware, but
140 * before the bulk of the kernel has been relocated. This code
141 * is relocated to physical address 0x60 before prom_init is run.
142 * All of it must fit below the first exception vector at 0x100.
144 _GLOBAL(__secondary_hold)
147 mtmsrd r24 /* RI on */
149 /* Grab our linux cpu number */
152 /* Tell the master cpu we're here */
153 /* Relocation is off & we are located at an address less */
154 /* than 0x100, so only need to grab low order offset. */
155 std r24,__secondary_hold_acknowledge@l(0)
158 /* All secondary cpu's wait here until told to start. */
159 100: ld r4,__secondary_hold_spinloop@l(0)
168 b .pSeries_secondary_smp_init
175 /* This value is used to mark exception frames on the stack. */
178 .tc ID_72656773_68657265[TC],0x7265677368657265
182 * The following macros define the code that appears as
183 * the prologue to each of the exception handlers. They
184 * are split into two parts to allow a single kernel binary
185 * to be used for pSeries and iSeries.
186 * LOL. One day... - paulus
190 * We make as much of the exception code common between native
191 * exception handlers (including pSeries LPAR) and iSeries LPAR
192 * implementations as possible.
196 * This is the start of the interrupt handlers for pSeries
197 * This code runs with relocation off.
205 #define EX_R3 40 /* SLB miss saves R3, but not SRR0 */
207 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
211 #define EXCEPTION_PROLOG_PSERIES(area, label) \
212 mfspr r13,SPRG3; /* get paca address into r13 */ \
213 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
214 std r10,area+EX_R10(r13); \
215 std r11,area+EX_R11(r13); \
216 std r12,area+EX_R12(r13); \
218 std r9,area+EX_R13(r13); \
220 clrrdi r12,r13,32; /* get high part of &label */ \
222 mfspr r11,SRR0; /* save SRR0 */ \
223 ori r12,r12,(label)@l; /* virt addr of handler */ \
224 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
226 mfspr r12,SRR1; /* and SRR1 */ \
229 b . /* prevent speculative execution */
232 * This is the start of the interrupt handlers for iSeries
233 * This code runs with relocation on.
235 #define EXCEPTION_PROLOG_ISERIES_1(area) \
236 mfspr r13,SPRG3; /* get paca address into r13 */ \
237 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
238 std r10,area+EX_R10(r13); \
239 std r11,area+EX_R11(r13); \
240 std r12,area+EX_R12(r13); \
242 std r9,area+EX_R13(r13); \
245 #define EXCEPTION_PROLOG_ISERIES_2 \
247 ld r11,PACALPPACA+LPPACASRR0(r13); \
248 ld r12,PACALPPACA+LPPACASRR1(r13); \
249 ori r10,r10,MSR_RI; \
253 * The common exception prolog is used for all except a few exceptions
254 * such as a segment miss on a kernel address. We have to be prepared
255 * to take another exception from the point where we first touch the
256 * kernel stack onwards.
258 * On entry r13 points to the paca, r9-r13 are saved in the paca,
259 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
260 * SRR1, and relocation is on.
262 #define EXCEPTION_PROLOG_COMMON(n, area) \
263 andi. r10,r12,MSR_PR; /* See if coming from user */ \
264 mr r10,r1; /* Save r1 */ \
265 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
267 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
268 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
269 bge- cr1,bad_stack; /* abort if it is */ \
270 std r9,_CCR(r1); /* save CR in stackframe */ \
271 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
272 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
273 std r10,0(r1); /* make stack chain pointer */ \
274 std r0,GPR0(r1); /* save r0 in stackframe */ \
275 std r10,GPR1(r1); /* save r1 in stackframe */ \
276 std r2,GPR2(r1); /* save r2 in stackframe */ \
277 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
278 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
279 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
280 ld r10,area+EX_R10(r13); \
283 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
284 ld r10,area+EX_R12(r13); \
285 ld r11,area+EX_R13(r13); \
289 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
290 mflr r9; /* save LR in stackframe */ \
292 mfctr r10; /* save CTR in stackframe */ \
294 mfspr r11,XER; /* save XER in stackframe */ \
297 std r9,_TRAP(r1); /* set trap number */ \
299 ld r11,exception_marker@toc(r2); \
300 std r10,RESULT(r1); /* clear regs->result */ \
301 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
306 #define STD_EXCEPTION_PSERIES(n, label) \
308 .globl label##_pSeries; \
311 mtspr SPRG1,r13; /* save r13 */ \
312 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
314 #define STD_EXCEPTION_ISERIES(n, label, area) \
315 .globl label##_iSeries; \
318 mtspr SPRG1,r13; /* save r13 */ \
319 EXCEPTION_PROLOG_ISERIES_1(area); \
320 EXCEPTION_PROLOG_ISERIES_2; \
323 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
324 .globl label##_iSeries; \
327 mtspr SPRG1,r13; /* save r13 */ \
328 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
329 lbz r10,PACAPROCENABLED(r13); \
331 beq- label##_iSeries_masked; \
332 EXCEPTION_PROLOG_ISERIES_2; \
335 #ifdef DO_SOFT_DISABLE
336 #define DISABLE_INTS \
337 lbz r10,PACAPROCENABLED(r13); \
341 stb r11,PACAPROCENABLED(r13); \
342 ori r10,r10,MSR_EE; \
345 #define ENABLE_INTS \
346 lbz r10,PACAPROCENABLED(r13); \
349 ori r11,r11,MSR_EE; \
352 #else /* hard enable/disable interrupts */
355 #define ENABLE_INTS \
358 rlwimi r11,r12,0,MSR_EE; \
363 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
365 .globl label##_common; \
367 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
370 addi r3,r1,STACK_FRAME_OVERHEAD; \
374 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
376 .globl label##_common; \
378 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
380 addi r3,r1,STACK_FRAME_OVERHEAD; \
382 b .ret_from_except_lite
385 * Start of pSeries system interrupt routines
388 .globl __start_interrupts
391 STD_EXCEPTION_PSERIES(0x100, system_reset)
394 _machine_check_pSeries:
396 mtspr SPRG1,r13 /* save r13 */
397 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
400 .globl data_access_pSeries
409 rlwimi r13,r12,16,0x20
412 beq .do_stab_bolted_pSeries
415 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
416 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
419 .globl data_access_slb_pSeries
420 data_access_slb_pSeries:
423 mfspr r13,SPRG3 /* get paca address into r13 */
424 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
425 std r10,PACA_EXSLB+EX_R10(r13)
426 std r11,PACA_EXSLB+EX_R11(r13)
427 std r12,PACA_EXSLB+EX_R12(r13)
428 std r3,PACA_EXSLB+EX_R3(r13)
430 std r9,PACA_EXSLB+EX_R13(r13)
432 mfspr r12,SRR1 /* and SRR1 */
434 b .do_slb_miss /* Rel. branch works in real mode */
436 STD_EXCEPTION_PSERIES(0x400, instruction_access)
439 .globl instruction_access_slb_pSeries
440 instruction_access_slb_pSeries:
443 mfspr r13,SPRG3 /* get paca address into r13 */
444 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
445 std r10,PACA_EXSLB+EX_R10(r13)
446 std r11,PACA_EXSLB+EX_R11(r13)
447 std r12,PACA_EXSLB+EX_R12(r13)
448 std r3,PACA_EXSLB+EX_R3(r13)
450 std r9,PACA_EXSLB+EX_R13(r13)
452 mfspr r12,SRR1 /* and SRR1 */
453 mfspr r3,SRR0 /* SRR0 is faulting address */
454 b .do_slb_miss /* Rel. branch works in real mode */
456 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
457 STD_EXCEPTION_PSERIES(0x600, alignment)
458 STD_EXCEPTION_PSERIES(0x700, program_check)
459 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
460 STD_EXCEPTION_PSERIES(0x900, decrementer)
461 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
462 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
465 .globl system_call_pSeries
473 oris r12,r12,system_call_common@h
474 ori r12,r12,system_call_common@l
476 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
480 b . /* prevent speculative execution */
482 STD_EXCEPTION_PSERIES(0xd00, single_step)
483 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
485 /* We need to deal with the Altivec unavailable exception
486 * here which is at 0xf20, thus in the middle of the
487 * prolog code of the PerformanceMonitor one. A little
488 * trickery is thus necessary
491 b performance_monitor_pSeries
493 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
495 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
496 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
498 /* moved from 0xf00 */
499 STD_EXCEPTION_PSERIES(0x3000, performance_monitor)
502 _GLOBAL(do_stab_bolted_pSeries)
505 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
508 /* Space for the naca. Architected to be located at real address
509 * NACA_PHYS_ADDR. Various tools rely on this location being fixed.
510 * The first dword of the naca is required by iSeries LPAR to
511 * point to itVpdAreas. On pSeries native, this value is not used.
514 .globl __end_interrupts
516 #ifdef CONFIG_PPC_ISERIES
522 . = SYSTEMCFG_PHYS_ADDR
523 .globl __start_systemcfg
525 . = (SYSTEMCFG_PHYS_ADDR + PAGE_SIZE)
526 .globl __end_systemcfg
529 #ifdef CONFIG_PPC_ISERIES
531 * The iSeries LPAR map is at this fixed address
532 * so that the HvReleaseData structure can address
533 * it with a 32-bit offset.
535 * The VSID values below are dependent on the
536 * VSID generation algorithm. See include/asm/mmu_context.h.
539 .llong 2 /* # ESIDs to be mapped by hypervisor */
540 .llong 1 /* # memory ranges to be mapped by hypervisor */
541 .llong STAB0_PAGE /* Page # of segment table within load area */
542 .llong 0 /* Reserved */
543 .llong 0 /* Reserved */
544 .llong 0 /* Reserved */
545 .llong 0 /* Reserved */
546 .llong 0 /* Reserved */
547 .llong (KERNELBASE>>SID_SHIFT)
548 .llong 0x408f92c94 /* KERNELBASE VSID */
549 /* We have to list the bolted VMALLOC segment here, too, so that it
550 * will be restored on shared processor switch */
551 .llong (VMALLOCBASE>>SID_SHIFT)
552 .llong 0xf09b89af5 /* VMALLOCBASE VSID */
553 .llong 8192 /* # pages to map (32 MB) */
554 .llong 0 /* Offset from start of loadarea to start of map */
555 .llong 0x408f92c940000 /* VPN of first page to map */
559 /*** ISeries-LPAR interrupt handlers ***/
561 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
563 .globl data_access_iSeries
571 rlwimi r13,r12,16,0x20
574 beq .do_stab_bolted_iSeries
577 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
578 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
579 EXCEPTION_PROLOG_ISERIES_2
582 .do_stab_bolted_iSeries:
585 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
586 EXCEPTION_PROLOG_ISERIES_2
589 .globl data_access_slb_iSeries
590 data_access_slb_iSeries:
591 mtspr SPRG1,r13 /* save r13 */
592 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
593 std r3,PACA_EXSLB+EX_R3(r13)
594 ld r12,PACALPPACA+LPPACASRR1(r13)
598 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
600 .globl instruction_access_slb_iSeries
601 instruction_access_slb_iSeries:
602 mtspr SPRG1,r13 /* save r13 */
603 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
604 std r3,PACA_EXSLB+EX_R3(r13)
605 ld r12,PACALPPACA+LPPACASRR1(r13)
606 ld r3,PACALPPACA+LPPACASRR0(r13)
609 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
610 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
611 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
612 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
613 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
614 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
615 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
617 .globl system_call_iSeries
621 EXCEPTION_PROLOG_ISERIES_2
624 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
625 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
626 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
628 .globl system_reset_iSeries
629 system_reset_iSeries:
630 mfspr r13,SPRG3 /* Get paca address */
633 mtmsrd r24 /* RI on */
634 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
635 cmpwi 0,r24,0 /* Are we processor 0? */
636 beq .__start_initialization_iSeries /* Start up the first processor */
638 li r5,RUNLATCH /* Turn off the run light */
645 lbz r23,PACAPROCSTART(r13) /* Test if this processor
648 LOADADDR(r3,current_set)
649 sldi r28,r24,3 /* get current_set[cpu#] */
651 addi r1,r3,THREAD_SIZE
652 subi r1,r1,STACK_FRAME_OVERHEAD
655 beq iSeries_secondary_smp_loop /* Loop until told to go */
656 #ifdef SECONDARY_PROCESSORS
657 bne .__secondary_start /* Loop until told to go */
659 iSeries_secondary_smp_loop:
660 /* Let the Hypervisor know we are alive */
661 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
663 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
664 #else /* CONFIG_SMP */
665 /* Yield the processor. This is required for non-SMP kernels
666 which are running on multi-threaded machines. */
668 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
669 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
670 li r4,0 /* "yield timed" */
671 li r5,-1 /* "yield forever" */
672 #endif /* CONFIG_SMP */
673 li r0,-1 /* r0=-1 indicates a Hypervisor call */
674 sc /* Invoke the hypervisor via a system call */
675 mfspr r13,SPRG3 /* Put r13 back ???? */
676 b 1b /* If SMP not configured, secondaries
679 .globl decrementer_iSeries_masked
680 decrementer_iSeries_masked:
682 stb r11,PACALPPACA+LPPACADECRINT(r13)
683 lwz r12,PACADEFAULTDECR(r13)
687 .globl hardware_interrupt_iSeries_masked
688 hardware_interrupt_iSeries_masked:
689 mtcrf 0x80,r9 /* Restore regs */
690 ld r11,PACALPPACA+LPPACASRR0(r13)
691 ld r12,PACALPPACA+LPPACASRR1(r13)
694 ld r9,PACA_EXGEN+EX_R9(r13)
695 ld r10,PACA_EXGEN+EX_R10(r13)
696 ld r11,PACA_EXGEN+EX_R11(r13)
697 ld r12,PACA_EXGEN+EX_R12(r13)
698 ld r13,PACA_EXGEN+EX_R13(r13)
700 b . /* prevent speculative execution */
704 * Data area reserved for FWNMI option.
707 .globl fwnmi_data_area
711 * Vectors for the FWNMI option. Share common code.
714 .globl system_reset_fwnmi
717 mtspr SPRG1,r13 /* save r13 */
718 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
719 .globl machine_check_fwnmi
722 mtspr SPRG1,r13 /* save r13 */
723 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
726 * Space for the initial segment table
727 * For LPAR, the hypervisor must fill in at least one entry
728 * before we get control (with relocate on)
734 . = (STAB0_PHYS_ADDR + PAGE_SIZE)
739 /*** Common interrupt handlers ***/
741 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
744 * Machine check is different because we use a different
745 * save area: PACA_EXMC instead of PACA_EXGEN.
748 .globl machine_check_common
749 machine_check_common:
750 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
753 addi r3,r1,STACK_FRAME_OVERHEAD
754 bl .machine_check_exception
757 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
758 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
759 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
760 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
761 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
762 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
763 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
764 #ifdef CONFIG_ALTIVEC
765 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
767 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
771 * Here we have detected that the kernel stack pointer is bad.
772 * R9 contains the saved CR, r13 points to the paca,
773 * r10 contains the (bad) kernel stack pointer,
774 * r11 and r12 contain the saved SRR0 and SRR1.
775 * We switch to using the paca guard page as an emergency stack,
776 * save the registers there, and call kernel_bad_stack(), which panics.
779 ld r1,PACAEMERGSP(r13)
780 subi r1,r1,64+INT_FRAME_SIZE
801 addi r11,r1,INT_FRAME_SIZE
806 1: addi r3,r1,STACK_FRAME_OVERHEAD
811 * Return from an exception with minimal checks.
812 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
813 * If interrupts have been enabled, or anything has been
814 * done that might have changed the scheduling status of
815 * any task or sent any task a signal, you should use
816 * ret_from_except or ret_from_except_lite instead of this.
818 fast_exception_return:
821 andi. r3,r12,MSR_RI /* check if RI is set */
835 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
843 b . /* prevent speculative execution */
847 1: addi r3,r1,STACK_FRAME_OVERHEAD
848 bl .unrecoverable_exception
852 * Here r13 points to the paca, r9 contains the saved CR,
853 * SRR0 and SRR1 are saved in r11 and r12,
854 * r9 - r13 are saved in paca->exgen.
857 .globl data_access_common
860 std r10,PACA_EXGEN+EX_DAR(r13)
862 stw r10,PACA_EXGEN+EX_DSISR(r13)
863 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
864 ld r3,PACA_EXGEN+EX_DAR(r13)
865 lwz r4,PACA_EXGEN+EX_DSISR(r13)
867 b .do_hash_page /* Try to handle as hpte fault */
870 .globl instruction_access_common
871 instruction_access_common:
872 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
876 b .do_hash_page /* Try to handle as hpte fault */
879 .globl hardware_interrupt_common
880 .globl hardware_interrupt_entry
881 hardware_interrupt_common:
882 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
883 hardware_interrupt_entry:
885 addi r3,r1,STACK_FRAME_OVERHEAD
887 b .ret_from_except_lite
890 .globl alignment_common
893 std r10,PACA_EXGEN+EX_DAR(r13)
895 stw r10,PACA_EXGEN+EX_DSISR(r13)
896 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
897 ld r3,PACA_EXGEN+EX_DAR(r13)
898 lwz r4,PACA_EXGEN+EX_DSISR(r13)
902 addi r3,r1,STACK_FRAME_OVERHEAD
904 bl .alignment_exception
908 .globl program_check_common
909 program_check_common:
910 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
912 addi r3,r1,STACK_FRAME_OVERHEAD
914 bl .program_check_exception
918 .globl fp_unavailable_common
919 fp_unavailable_common:
920 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
921 bne .load_up_fpu /* if from user, just load it up */
923 addi r3,r1,STACK_FRAME_OVERHEAD
925 bl .kernel_fp_unavailable_exception
929 .globl altivec_unavailable_common
930 altivec_unavailable_common:
931 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
932 #ifdef CONFIG_ALTIVEC
933 bne .load_up_altivec /* if from user, just load it up */
936 addi r3,r1,STACK_FRAME_OVERHEAD
938 bl .altivec_unavailable_exception
945 _GLOBAL(do_hash_page)
949 andis. r0,r4,0xa450 /* weird error? */
950 bne- .handle_page_fault /* if not, try to insert a HPTE */
952 andis. r0,r4,0x0020 /* Is it a segment table fault? */
953 bne- .do_ste_alloc /* If so handle it */
954 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
957 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
958 * accessing a userspace segment (even from the kernel). We assume
959 * kernel addresses always have the high bit set.
961 rlwinm r4,r4,32-23,29,29 /* DSISR_STORE -> _PAGE_RW */
962 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
963 orc r0,r12,r0 /* MSR_PR | ~high_bit */
964 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
965 ori r4,r4,1 /* add _PAGE_PRESENT */
968 * On iSeries, we soft-disable interrupts here, then
969 * hard-enable interrupts so that the hash_page code can spin on
970 * the hash_table_lock without problems on a shared processor.
975 * r3 contains the faulting address
976 * r4 contains the required access permissions
977 * r5 contains the trap number
979 * at return r3 = 0 for success
981 bl .hash_page /* build HPTE if possible */
982 cmpdi r3,0 /* see if hash_page succeeded */
984 #ifdef DO_SOFT_DISABLE
986 * If we had interrupts soft-enabled at the point where the
987 * DSI/ISI occurred, and an interrupt came in during hash_page,
989 * We jump to ret_from_except_lite rather than fast_exception_return
990 * because ret_from_except_lite will check for and handle pending
991 * interrupts if necessary.
993 beq .ret_from_except_lite
994 /* For a hash failure, we don't bother re-enabling interrupts */
998 * hash_page couldn't handle it, set soft interrupt enable back
999 * to what it was before the trap. Note that .local_irq_restore
1000 * handles any interrupts pending at this point.
1003 bl .local_irq_restore
1006 beq fast_exception_return /* Return from exception on success */
1007 ble- 12f /* Failure return from hash_page */
1012 /* Here we have a page fault that hash_page can't handle. */
1013 _GLOBAL(handle_page_fault)
1017 addi r3,r1,STACK_FRAME_OVERHEAD
1020 beq+ .ret_from_except_lite
1023 addi r3,r1,STACK_FRAME_OVERHEAD
1028 /* We have a page fault that hash_page could handle but HV refused
1032 addi r3,r1,STACK_FRAME_OVERHEAD
1037 /* here we have a segment miss */
1038 _GLOBAL(do_ste_alloc)
1039 bl .ste_allocate /* try to insert stab entry */
1041 beq+ fast_exception_return
1042 b .handle_page_fault
1045 * r13 points to the PACA, r9 contains the saved CR,
1046 * r11 and r12 contain the saved SRR0 and SRR1.
1047 * r9 - r13 are saved in paca->exslb.
1048 * We assume we aren't going to take any exceptions during this procedure.
1049 * We assume (DAR >> 60) == 0xc.
1052 _GLOBAL(do_stab_bolted)
1053 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1054 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1056 /* Hash to the primary group */
1057 ld r10,PACASTABVIRT(r13)
1060 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1062 /* Calculate VSID */
1063 /* This is a kernel address, so protovsid = ESID */
1064 ASM_VSID_SCRAMBLE(r11, r9)
1065 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1067 /* Search the primary group for a free entry */
1068 1: ld r11,0(r10) /* Test valid bit of the current ste */
1075 /* Stick for only searching the primary group for now. */
1076 /* At least for now, we use a very simple random castout scheme */
1077 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1079 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1082 /* r10 currently points to an ste one past the group of interest */
1083 /* make it point to the randomly selected entry */
1085 or r10,r10,r11 /* r10 is the entry to invalidate */
1087 isync /* mark the entry invalid */
1089 rldicl r11,r11,56,1 /* clear the valid bit */
1094 clrrdi r11,r11,28 /* Get the esid part of the ste */
1097 2: std r9,8(r10) /* Store the vsid part of the ste */
1100 mfspr r11,DAR /* Get the new esid */
1101 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1102 ori r11,r11,0x90 /* Turn on valid and kp */
1103 std r11,0(r10) /* Put new entry back into the stab */
1107 /* All done -- return from exception. */
1108 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1109 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1111 andi. r10,r12,MSR_RI
1114 mtcrf 0x80,r9 /* restore CR */
1122 ld r9,PACA_EXSLB+EX_R9(r13)
1123 ld r10,PACA_EXSLB+EX_R10(r13)
1124 ld r11,PACA_EXSLB+EX_R11(r13)
1125 ld r12,PACA_EXSLB+EX_R12(r13)
1126 ld r13,PACA_EXSLB+EX_R13(r13)
1128 b . /* prevent speculative execution */
1131 * r13 points to the PACA, r9 contains the saved CR,
1132 * r11 and r12 contain the saved SRR0 and SRR1.
1133 * r3 has the faulting address
1134 * r9 - r13 are saved in paca->exslb.
1135 * r3 is saved in paca->slb_r3
1136 * We assume we aren't going to take any exceptions during this procedure.
1138 _GLOBAL(do_slb_miss)
1141 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1142 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1144 bl .slb_allocate /* handle it */
1146 /* All done -- return from exception. */
1148 ld r10,PACA_EXSLB+EX_LR(r13)
1149 ld r3,PACA_EXSLB+EX_R3(r13)
1150 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1151 #ifdef CONFIG_PPC_ISERIES
1152 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
1153 #endif /* CONFIG_PPC_ISERIES */
1157 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1163 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1166 #ifdef CONFIG_PPC_ISERIES
1169 #endif /* CONFIG_PPC_ISERIES */
1170 ld r9,PACA_EXSLB+EX_R9(r13)
1171 ld r10,PACA_EXSLB+EX_R10(r13)
1172 ld r11,PACA_EXSLB+EX_R11(r13)
1173 ld r12,PACA_EXSLB+EX_R12(r13)
1174 ld r13,PACA_EXSLB+EX_R13(r13)
1176 b . /* prevent speculative execution */
1179 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1182 1: addi r3,r1,STACK_FRAME_OVERHEAD
1183 bl .unrecoverable_exception
1188 * On pSeries, secondary processors spin in the following code.
1189 * At entry, r3 = this processor's number (physical cpu id)
1191 _GLOBAL(pSeries_secondary_smp_init)
1194 /* turn on 64-bit mode */
1198 /* Copy some CPU settings from CPU 0 */
1199 bl .__restore_cpu_setup
1201 /* Set up a paca value for this processor. Since we have the
1202 * physical cpu id in r3, we need to search the pacas to find
1203 * which logical id maps to our physical one.
1205 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1206 li r5,0 /* logical cpu id */
1207 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1208 cmpw r6,r24 /* Compare to our id */
1210 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1215 99: HMT_LOW /* Couldn't find our CPU id */
1218 2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1219 /* From now on, r24 is expected to be logica cpuid */
1222 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1226 /* Create a temp kernel stack for use before relocation is on. */
1227 ld r1,PACAEMERGSP(r13)
1228 subi r1,r1,STACK_FRAME_OVERHEAD
1232 #ifdef SECONDARY_PROCESSORS
1233 bne .__secondary_start
1236 b 3b /* Loop until told to go */
1238 #ifdef CONFIG_PPC_ISERIES
1239 _STATIC(__start_initialization_iSeries)
1240 /* Clear out the BSS */
1241 LOADADDR(r11,__bss_stop)
1242 LOADADDR(r8,__bss_start)
1243 sub r11,r11,r8 /* bss size */
1244 addi r11,r11,7 /* round up to an even double word */
1245 rldicl. r11,r11,61,3 /* shift right by 3 */
1249 mtctr r11 /* zero this many doublewords */
1253 LOADADDR(r1,init_thread_union)
1254 addi r1,r1,THREAD_SIZE
1256 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1258 LOADADDR(r3,cpu_specs)
1259 LOADADDR(r4,cur_cpu_spec)
1263 LOADADDR(r2,__toc_start)
1267 LOADADDR(r9,systemcfg)
1268 SET_REG_TO_CONST(r4, SYSTEMCFG_VIRT_ADDR)
1269 std r4,0(r9) /* set the systemcfg pointer */
1271 bl .iSeries_early_setup
1273 /* relocation is on at this point */
1275 b .start_here_common
1276 #endif /* CONFIG_PPC_ISERIES */
1278 #ifdef CONFIG_PPC_MULTIPLATFORM
1282 andi. r0,r3,MSR_IR|MSR_DR
1289 b . /* prevent speculative execution */
1293 * Here is our main kernel entry point. We support currently 2 kind of entries
1294 * depending on the value of r5.
1296 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1299 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1300 * DT block, r4 is a physical pointer to the kernel itself
1303 _GLOBAL(__start_initialization_multiplatform)
1305 * Are we booted from a PROM Of-type client-interface ?
1308 bne .__boot_from_prom /* yes -> prom */
1310 /* Save parameters */
1314 /* Make sure we are running in 64 bits mode */
1317 /* Setup some critical 970 SPRs before switching MMU off */
1318 bl .__970_cpu_preinit
1323 /* Switch off MMU if not already */
1324 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1327 b .__after_prom_start
1329 _STATIC(__boot_from_prom)
1330 /* Save parameters */
1337 /* Make sure we are running in 64 bits mode */
1340 /* put a relocation offset into r3 */
1343 LOADADDR(r2,__toc_start)
1347 /* Relocate the TOC from a virt addr to a real addr */
1350 /* Restore parameters */
1357 /* Do all of the interaction with OF client interface */
1359 /* We never return */
1363 * At this point, r3 contains the physical address we are running at,
1364 * returned by prom_init()
1366 _STATIC(__after_prom_start)
1369 * We need to run with __start at physical address 0.
1370 * This will leave some code in the first 256B of
1371 * real memory, which are reserved for software use.
1372 * The remainder of the first page is loaded with the fixed
1373 * interrupt vectors. The next two pages are filled with
1374 * unknown exception placeholders.
1376 * Note: This process overwrites the OF exception vectors.
1377 * r26 == relocation offset
1382 SET_REG_TO_CONST(r27,KERNELBASE)
1384 li r3,0 /* target addr */
1386 // XXX FIXME: Use phys returned by OF (r30)
1387 sub r4,r27,r26 /* source addr */
1388 /* current address of _start */
1389 /* i.e. where we are running */
1390 /* the source addr */
1392 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1395 li r6,0x100 /* Start offset, the first 0x100 */
1396 /* bytes were copied earlier. */
1398 bl .copy_and_flush /* copy the first n bytes */
1399 /* this includes the code being */
1400 /* executed here. */
1402 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1403 mtctr r0 /* that we just made/relocated */
1406 4: LOADADDR(r5,klimit)
1408 ld r5,0(r5) /* get the value of klimit */
1410 bl .copy_and_flush /* copy the rest */
1411 b .start_here_multiplatform
1413 #endif /* CONFIG_PPC_MULTIPLATFORM */
1416 * Copy routine used to copy the kernel to start at physical address 0
1417 * and flush and invalidate the caches as needed.
1418 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1419 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1421 * Note: this routine *only* clobbers r0, r6 and lr
1423 _GLOBAL(copy_and_flush)
1426 4: li r0,16 /* Use the least common */
1427 /* denominator cache line */
1428 /* size. This results in */
1429 /* extra cache line flushes */
1430 /* but operation is correct. */
1431 /* Can't get cache line size */
1432 /* from NACA as it is being */
1435 mtctr r0 /* put # words/line in ctr */
1436 3: addi r6,r6,8 /* copy a cache line */
1440 dcbst r6,r3 /* write it to memory */
1442 icbi r6,r3 /* flush the icache line */
1454 * load_up_fpu(unused, unused, tsk)
1455 * Disable FP for the task which had the FPU previously,
1456 * and save its floating-point registers in its thread_struct.
1457 * Enables the FPU for use in the kernel on return.
1458 * On SMP we know the fpu is free, since we give it up every
1459 * switch (ie, no lazy save of the FP registers).
1460 * On entry: r13 == 'current' && last_task_used_math != 'current'
1462 _STATIC(load_up_fpu)
1463 mfmsr r5 /* grab the current MSR */
1465 mtmsrd r5 /* enable use of fpu now */
1468 * For SMP, we don't do lazy FPU switching because it just gets too
1469 * horrendously complex, especially when a task switches from one CPU
1470 * to another. Instead we call giveup_fpu in switch_to.
1474 ld r3,last_task_used_math@got(r2)
1478 /* Save FP state to last_task_used_math's THREAD struct */
1482 stfd fr0,THREAD_FPSCR(r4)
1483 /* Disable FP for last_task_used_math */
1485 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1486 li r6,MSR_FP|MSR_FE0|MSR_FE1
1488 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1490 #endif /* CONFIG_SMP */
1491 /* enable use of FP after return */
1492 ld r4,PACACURRENT(r13)
1493 addi r5,r4,THREAD /* Get THREAD */
1494 ld r4,THREAD_FPEXC_MODE(r5)
1498 lfd fr0,THREAD_FPSCR(r5)
1502 /* Update last_task_used_math to 'current' */
1503 subi r4,r5,THREAD /* Back to 'current' */
1505 #endif /* CONFIG_SMP */
1506 /* restore registers and return */
1507 b fast_exception_return
1510 * disable_kernel_fp()
1513 _GLOBAL(disable_kernel_fp)
1515 rldicl r0,r3,(63-MSR_FP_LG),1
1516 rldicl r3,r0,(MSR_FP_LG+1),0
1517 mtmsrd r3 /* disable use of fpu now */
1523 * Disable FP for the task given as the argument,
1524 * and save the floating-point registers in its thread_struct.
1525 * Enables the FPU for use in the kernel on return.
1530 mtmsrd r5 /* enable use of fpu now */
1533 beqlr- /* if no previous owner, done */
1534 addi r3,r3,THREAD /* want THREAD of task */
1539 stfd fr0,THREAD_FPSCR(r3)
1541 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1542 li r3,MSR_FP|MSR_FE0|MSR_FE1
1543 andc r4,r4,r3 /* disable FP for previous task */
1544 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1548 ld r4,last_task_used_math@got(r2)
1550 #endif /* CONFIG_SMP */
1554 #ifdef CONFIG_ALTIVEC
1557 * load_up_altivec(unused, unused, tsk)
1558 * Disable VMX for the task which had it previously,
1559 * and save its vector registers in its thread_struct.
1560 * Enables the VMX for use in the kernel on return.
1561 * On SMP we know the VMX is free, since we give it up every
1562 * switch (ie, no lazy save of the vector registers).
1563 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1565 _STATIC(load_up_altivec)
1566 mfmsr r5 /* grab the current MSR */
1567 oris r5,r5,MSR_VEC@h
1568 mtmsrd r5 /* enable use of VMX now */
1572 * For SMP, we don't do lazy VMX switching because it just gets too
1573 * horrendously complex, especially when a task switches from one CPU
1574 * to another. Instead we call giveup_altvec in switch_to.
1575 * VRSAVE isn't dealt with here, that is done in the normal context
1576 * switch code. Note that we could rely on vrsave value to eventually
1577 * avoid saving all of the VREGs here...
1580 ld r3,last_task_used_altivec@got(r2)
1584 /* Save VMX state to last_task_used_altivec's THREAD struct */
1590 /* Disable VMX for last_task_used_altivec */
1592 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1595 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1597 #endif /* CONFIG_SMP */
1598 /* Hack: if we get an altivec unavailable trap with VRSAVE
1599 * set to all zeros, we assume this is a broken application
1600 * that fails to set it properly, and thus we switch it to
1603 mfspr r4,SPRN_VRSAVE
1607 mtspr SPRN_VRSAVE,r4
1609 /* enable use of VMX after return */
1610 ld r4,PACACURRENT(r13)
1611 addi r5,r4,THREAD /* Get THREAD */
1612 oris r12,r12,MSR_VEC@h
1616 stw r4,THREAD_USED_VR(r5)
1621 /* Update last_task_used_math to 'current' */
1622 subi r4,r5,THREAD /* Back to 'current' */
1624 #endif /* CONFIG_SMP */
1625 /* restore registers and return */
1626 b fast_exception_return
1629 * disable_kernel_altivec()
1632 _GLOBAL(disable_kernel_altivec)
1634 rldicl r0,r3,(63-MSR_VEC_LG),1
1635 rldicl r3,r0,(MSR_VEC_LG+1),0
1636 mtmsrd r3 /* disable use of VMX now */
1641 * giveup_altivec(tsk)
1642 * Disable VMX for the task given as the argument,
1643 * and save the vector registers in its thread_struct.
1644 * Enables the VMX for use in the kernel on return.
1646 _GLOBAL(giveup_altivec)
1648 oris r5,r5,MSR_VEC@h
1649 mtmsrd r5 /* enable use of VMX now */
1652 beqlr- /* if no previous owner, done */
1653 addi r3,r3,THREAD /* want THREAD of task */
1661 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1663 andc r4,r4,r3 /* disable FP for previous task */
1664 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1668 ld r4,last_task_used_altivec@got(r2)
1670 #endif /* CONFIG_SMP */
1673 #endif /* CONFIG_ALTIVEC */
1676 #ifdef CONFIG_PPC_PMAC
1678 * On PowerMac, secondary processors starts from the reset vector, which
1679 * is temporarily turned into a call to one of the functions below.
1684 .globl pmac_secondary_start_1
1685 pmac_secondary_start_1:
1687 b .pmac_secondary_start
1689 .globl pmac_secondary_start_2
1690 pmac_secondary_start_2:
1692 b .pmac_secondary_start
1694 .globl pmac_secondary_start_3
1695 pmac_secondary_start_3:
1697 b .pmac_secondary_start
1699 _GLOBAL(pmac_secondary_start)
1700 /* turn on 64-bit mode */
1704 /* Copy some CPU settings from CPU 0 */
1705 bl .__restore_cpu_setup
1707 /* pSeries do that early though I don't think we really need it */
1710 mtmsrd r3 /* RI on */
1712 /* Set up a paca value for this processor. */
1713 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1714 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1715 add r13,r13,r4 /* for this processor. */
1716 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1718 /* Create a temp kernel stack for use before relocation is on. */
1719 ld r1,PACAEMERGSP(r13)
1720 subi r1,r1,STACK_FRAME_OVERHEAD
1722 b .__secondary_start
1724 #endif /* CONFIG_PPC_PMAC */
1727 * This function is called after the master CPU has released the
1728 * secondary processors. The execution environment is relocation off.
1729 * The paca for this processor has the following fields initialized at
1731 * 1. Processor number
1732 * 2. Segment table pointer (virtual address)
1733 * On entry the following are set:
1734 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1735 * r24 = cpu# (in Linux terms)
1736 * r13 = paca virtual address
1737 * SPRG3 = paca virtual address
1739 _GLOBAL(__secondary_start)
1741 HMT_MEDIUM /* Set thread priority to MEDIUM */
1745 stb r6,PACAPROCENABLED(r13)
1747 #ifndef CONFIG_PPC_ISERIES
1748 /* Initialize the page table pointer register. */
1750 ld r6,0(r6) /* get the value of _SDR1 */
1751 mtspr SDR1,r6 /* set the htab location */
1753 /* Initialize the first segment table (or SLB) entry */
1754 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1757 /* Initialize the kernel stack. Just a repeat for iSeries. */
1758 LOADADDR(r3,current_set)
1759 sldi r28,r24,3 /* get current_set[cpu#] */
1761 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1762 std r1,PACAKSAVE(r13)
1764 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1765 ori r4,r3,1 /* turn on valid bit */
1767 #ifdef CONFIG_PPC_ISERIES
1768 li r0,-1 /* hypervisor call */
1770 sldi r3,r3,63 /* 0x8000000000000000 */
1771 ori r3,r3,4 /* 0x8000000000000004 */
1772 sc /* HvCall_setASR */
1775 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1776 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1777 cmpldi r3,PLATFORM_PSERIES_LPAR
1781 cmpwi r3,0x37 /* SStar */
1783 cmpwi r3,0x36 /* IStar */
1785 cmpwi r3,0x34 /* Pulsar */
1787 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1788 HVSC /* Invoking hcall */
1790 98: /* !(rpa hypervisor) || !(star) */
1791 mtasr r4 /* set the stab location */
1797 /* enable MMU and jump to start_secondary */
1798 LOADADDR(r3,.start_secondary_prolog)
1799 SET_REG_TO_CONST(r4, MSR_KERNEL)
1800 #ifdef DO_SOFT_DISABLE
1806 b . /* prevent speculative execution */
1809 * Running with relocation on at this point. All we want to do is
1810 * zero the stack back-chain pointer before going into C code.
1812 _GLOBAL(start_secondary_prolog)
1814 std r3,0(r1) /* Zero the stack frame pointer */
1819 * This subroutine clobbers r11 and r12
1821 _GLOBAL(enable_64b_mode)
1822 mfmsr r11 /* grab the current MSR */
1824 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1827 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1833 #ifdef CONFIG_PPC_MULTIPLATFORM
1835 * This is where the main kernel code starts.
1837 _STATIC(start_here_multiplatform)
1838 /* get a new offset, now that the kernel has moved. */
1842 /* Clear out the BSS. It may have been done in prom_init,
1843 * already but that's irrelevant since prom_init will soon
1844 * be detached from the kernel completely. Besides, we need
1845 * to clear it now for kexec-style entry.
1847 LOADADDR(r11,__bss_stop)
1848 LOADADDR(r8,__bss_start)
1849 sub r11,r11,r8 /* bss size */
1850 addi r11,r11,7 /* round up to an even double word */
1851 rldicl. r11,r11,61,3 /* shift right by 3 */
1855 mtctr r11 /* zero this many doublewords */
1862 mtmsrd r6 /* RI on */
1864 /* setup the systemcfg pointer which is needed by *tab_initialize */
1865 LOADADDR(r6,systemcfg)
1866 sub r6,r6,r26 /* addr of the variable systemcfg */
1867 li r27,SYSTEMCFG_PHYS_ADDR
1868 std r27,0(r6) /* set the value of systemcfg */
1871 /* Start up the second thread on cpu 0 */
1874 cmpwi r3,0x34 /* Pulsar */
1876 cmpwi r3,0x36 /* Icestar */
1878 cmpwi r3,0x37 /* SStar */
1880 b 91f /* HMT not supported */
1882 bl .hmt_start_secondary
1886 /* The following gets the stack and TOC set up with the regs */
1887 /* pointing to the real addr of the kernel stack. This is */
1888 /* all done to support the C function call below which sets */
1889 /* up the htab. This is done because we have relocated the */
1890 /* kernel but are still running in real mode. */
1892 LOADADDR(r3,init_thread_union)
1895 /* set up a stack pointer (physical address) */
1896 addi r1,r3,THREAD_SIZE
1898 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1900 /* set up the TOC (physical address) */
1901 LOADADDR(r2,__toc_start)
1906 LOADADDR(r3,cpu_specs)
1908 LOADADDR(r4,cur_cpu_spec)
1913 /* Save some low level config HIDs of CPU0 to be copied to
1914 * other CPUs later on, or used for suspend/resume
1916 bl .__save_cpu_setup
1919 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1920 * note that boot_cpuid can always be 0 nowadays since there is
1921 * nowhere it can be initialized differently before we reach this
1924 LOADADDR(r27, boot_cpuid)
1928 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1929 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1930 add r13,r13,r24 /* for this processor. */
1931 sub r13,r13,r26 /* convert to physical addr */
1932 mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
1934 /* Do very early kernel initializations, including initial hash table,
1935 * stab and slb setup before we turn on relocation. */
1937 /* Restore parameters passed from prom_init/kexec */
1942 ld r3,PACASTABREAL(r13)
1943 ori r4,r3,1 /* turn on valid bit */
1944 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1945 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1946 cmpldi r3,PLATFORM_PSERIES_LPAR
1950 cmpwi r3,0x37 /* SStar */
1952 cmpwi r3,0x36 /* IStar */
1954 cmpwi r3,0x34 /* Pulsar */
1956 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1957 HVSC /* Invoking hcall */
1959 98: /* !(rpa hypervisor) || !(star) */
1960 mtasr r4 /* set the stab location */
1962 /* Set SDR1 (hash table pointer) */
1963 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1964 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1965 /* Test if bit 0 is set (LPAR bit) */
1968 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1970 ld r6,0(r6) /* get the value of _SDR1 */
1971 mtspr SDR1,r6 /* set the htab location */
1973 LOADADDR(r3,.start_here_common)
1974 SET_REG_TO_CONST(r4, MSR_KERNEL)
1978 b . /* prevent speculative execution */
1979 #endif /* CONFIG_PPC_MULTIPLATFORM */
1981 /* This is where all platforms converge execution */
1982 _STATIC(start_here_common)
1983 /* relocation is on at this point */
1985 /* The following code sets up the SP and TOC now that we are */
1986 /* running with translation enabled. */
1988 LOADADDR(r3,init_thread_union)
1990 /* set up the stack */
1991 addi r1,r3,THREAD_SIZE
1993 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1995 /* Apply the CPUs-specific fixups (nop out sections not relevant
1999 bl .do_cpu_ftr_fixups
2001 /* setup the systemcfg pointer */
2002 LOADADDR(r9,systemcfg)
2003 SET_REG_TO_CONST(r8, SYSTEMCFG_VIRT_ADDR)
2006 LOADADDR(r26, boot_cpuid)
2009 LOADADDR(r24, paca) /* Get base vaddr of paca array */
2010 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
2011 add r13,r13,r24 /* for this processor. */
2014 /* ptr to current */
2015 LOADADDR(r4,init_task)
2016 std r4,PACACURRENT(r13)
2020 std r1,PACAKSAVE(r13)
2024 /* Load up the kernel context */
2026 #ifdef DO_SOFT_DISABLE
2028 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
2030 ori r5,r5,MSR_EE /* Hard Enabled */
2036 _GLOBAL(__setup_cpu_power3)
2041 LOADADDR(r5, hmt_thread_data)
2044 cmpwi r7,0x34 /* Pulsar */
2046 cmpwi r7,0x36 /* Icestar */
2048 cmpwi r7,0x37 /* SStar */
2058 bl .hmt_start_secondary
2061 __hmt_secondary_hold:
2062 LOADADDR(r5, hmt_thread_data)
2072 93: andi. r6,r6,0x3f
2086 b .pSeries_secondary_smp_init
2089 _GLOBAL(hmt_start_secondary)
2090 LOADADDR(r4,__hmt_secondary_hold)
2111 #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES)
2112 _GLOBAL(smp_release_cpus)
2113 /* All secondary cpus are spinning on a common
2114 * spinloop, release them all now so they can start
2115 * to spin on their individual paca spinloops.
2116 * For non SMP kernels, the secondary cpus never
2117 * get out of the common spinloop.
2120 LOADADDR(r5,__secondary_hold_spinloop)
2124 #endif /* CONFIG_SMP && !CONFIG_PPC_ISERIES */
2128 * We put a few things here that have to be page-aligned.
2129 * This stuff goes at the beginning of the data segment,
2130 * which is page-aligned.
2136 .globl empty_zero_page
2140 .globl swapper_pg_dir
2149 /* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
2156 * This space gets a copy of optional info passed to us by the bootstrap
2157 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2161 .space COMMAND_LINE_SIZE