arch/ppc64/kernel/i8259.c

   1 /*
   2  * c 2001 PPC64 Team, IBM Corp
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9 #include <linux/stddef.h>
  10 #include <linux/init.h>
  11 #include <linux/sched.h>
  12 #include <linux/signal.h>
  13 #include <linux/cache.h>
  14 #include <linux/irq.h>
  15 #include <linux/interrupt.h>
  16 #include <asm/io.h>
  17 #include <asm/ppcdebug.h>
  18 #include "i8259.h"
  19
  20 unsigned char cached_8259[2] = { 0xff, 0xff };
  21 #define cached_A1 (cached_8259[0])
  22 #define cached_21 (cached_8259[1])
  23
  24 static spinlock_t i8259_lock __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
  25
  26 int i8259_pic_irq_offset;
  27
  28 int i8259_irq(int cpu)
  29 {
  30         int irq;
  31
  32         spin_lock/*_irqsave*/(&i8259_lock/*, flags*/);
  33         /*
  34          * Perform an interrupt acknowledge cycle on controller 1
  35          */
  36         outb(0x0C, 0x20);
  37         irq = inb(0x20) & 7;
  38         if (irq == 2)
  39         {
  40                 /*
  41                  * Interrupt is cascaded so perform interrupt
  42                  * acknowledge on controller 2
  43                  */
  44                 outb(0x0C, 0xA0);
  45                 irq = (inb(0xA0) & 7) + 8;
  46         }
  47         else if (irq==7)
  48         {
  49                 /*
  50                  * This may be a spurious interrupt
  51                  *
  52                  * Read the interrupt status register. If the most
  53                  * significant bit is not set then there is no valid
  54                  * interrupt
  55                  */
  56                 outb(0x0b, 0x20);
  57                 if(~inb(0x20)&0x80) {
  58                         spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
  59                         return -1;
  60                 }
  61         }
  62         spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
  63         return irq;
  64 }
  65
  66 static void i8259_mask_and_ack_irq(unsigned int irq_nr)
  67 {
  68         unsigned long flags;
  69
  70         spin_lock_irqsave(&i8259_lock, flags);
  71         if ( irq_nr >= i8259_pic_irq_offset )
  72                 irq_nr -= i8259_pic_irq_offset;
  73
  74         if (irq_nr > 7) {
  75                 cached_A1 |= 1 << (irq_nr-8);
  76                 inb(0xA1);      /* DUMMY */
  77                 outb(cached_A1,0xA1);
  78                 outb(0x20,0xA0);        /* Non-specific EOI */
  79                 outb(0x20,0x20);        /* Non-specific EOI to cascade */
  80         } else {
  81                 cached_21 |= 1 << irq_nr;
  82                 inb(0x21);      /* DUMMY */
  83                 outb(cached_21,0x21);
  84                 outb(0x20,0x20);        /* Non-specific EOI */
  85         }
  86         spin_unlock_irqrestore(&i8259_lock, flags);
  87 }
  88
  89 static void i8259_set_irq_mask(int irq_nr)
  90 {
  91         outb(cached_A1,0xA1);
  92         outb(cached_21,0x21);
  93 }
  94
  95 static void i8259_mask_irq(unsigned int irq_nr)
  96 {
  97         unsigned long flags;
  98
  99         spin_lock_irqsave(&i8259_lock, flags);
 100         if ( irq_nr >= i8259_pic_irq_offset )
 101                 irq_nr -= i8259_pic_irq_offset;
 102         if ( irq_nr < 8 )
 103                 cached_21 |= 1 << irq_nr;
 104         else
 105                 cached_A1 |= 1 << (irq_nr-8);
 106         i8259_set_irq_mask(irq_nr);
 107         spin_unlock_irqrestore(&i8259_lock, flags);
 108 }
 109
 110 static void i8259_unmask_irq(unsigned int irq_nr)
 111 {
 112         unsigned long flags;
 113
 114         spin_lock_irqsave(&i8259_lock, flags);
 115         if ( irq_nr >= i8259_pic_irq_offset )
 116                 irq_nr -= i8259_pic_irq_offset;
 117         if ( irq_nr < 8 )
 118                 cached_21 &= ~(1 << irq_nr);
 119         else
 120                 cached_A1 &= ~(1 << (irq_nr-8));
 121         i8259_set_irq_mask(irq_nr);
 122         spin_unlock_irqrestore(&i8259_lock, flags);
 123 }
 124
 125 static void i8259_end_irq(unsigned int irq)
 126 {
 127         if (!(get_irq_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
 128             get_irq_desc(irq)->action)
 129                 i8259_unmask_irq(irq);
 130 }
 131
 132 struct hw_interrupt_type i8259_pic = {
 133         " i8259    ",
 134         NULL,
 135         NULL,
 136         i8259_unmask_irq,
 137         i8259_mask_irq,
 138         i8259_mask_and_ack_irq,
 139         i8259_end_irq,
 140         NULL
 141 };
 142
 143 void __init i8259_init(void)
 144 {
 145         unsigned long flags;
 146
 147         spin_lock_irqsave(&i8259_lock, flags);
 148         /* init master interrupt controller */
 149         outb(0x11, 0x20); /* Start init sequence */
 150         outb(0x00, 0x21); /* Vector base */
 151         outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
 152         outb(0x01, 0x21); /* Select 8086 mode */
 153         outb(0xFF, 0x21); /* Mask all */
 154         /* init slave interrupt controller */
 155         outb(0x11, 0xA0); /* Start init sequence */
 156         outb(0x08, 0xA1); /* Vector base */
 157         outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
 158         outb(0x01, 0xA1); /* Select 8086 mode */
 159         outb(0xFF, 0xA1); /* Mask all */
 160         outb(cached_A1, 0xA1);
 161         outb(cached_21, 0x21);
 162         spin_unlock_irqrestore(&i8259_lock, flags);
 163         request_irq( i8259_pic_irq_offset + 2, no_action, SA_INTERRUPT,
 164                      "82c59 secondary cascade", NULL );
 165
 166 }