5 * Copyright (C) 2001 Allan Trautman, IBM Corporation
7 * iSeries specific routines for PCI.
9 * Based on code from pci.c and iSeries_pci.c 32bit
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/string.h>
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/ide.h>
31 #include <linux/pci.h>
36 #include <asm/machdep.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/ppcdebug.h>
40 #include <asm/iommu.h>
42 #include <asm/iSeries/HvCallPci.h>
43 #include <asm/iSeries/HvCallSm.h>
44 #include <asm/iSeries/HvCallXm.h>
45 #include <asm/iSeries/LparData.h>
46 #include <asm/iSeries/iSeries_irq.h>
47 #include <asm/iSeries/iSeries_pci.h>
48 #include <asm/iSeries/mf.h>
50 #include "iSeries_IoMmTable.h"
53 extern int panic_timeout;
55 extern unsigned long iSeries_Base_Io_Memory;
57 extern struct iommu_table *tceTables[256];
59 extern void iSeries_MmIoTest(void);
62 * Forward declares of prototypes.
64 static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn);
65 static void iSeries_Scan_PHBs_Slots(struct pci_controller *Phb);
66 static void iSeries_Scan_EADs_Bridge(HvBusNumber Bus, HvSubBusNumber SubBus,
68 static int iSeries_Scan_Bridge_Slot(HvBusNumber Bus,
69 struct HvCallPci_BridgeInfo *Info);
71 LIST_HEAD(iSeries_Global_Device_List);
73 static int DeviceCount;
75 /* Counters and control flags. */
76 static long Pci_Io_Read_Count;
77 static long Pci_Io_Write_Count;
79 static long Pci_Cfg_Read_Count;
80 static long Pci_Cfg_Write_Count;
82 static long Pci_Error_Count;
84 static int Pci_Retry_Max = 3; /* Only retry 3 times */
85 static int Pci_Error_Flag = 1; /* Set Retry Error on. */
87 static struct pci_ops iSeries_pci_ops;
90 * Log Error infor in Flight Recorder to system Console.
91 * Filter out the device not there errors.
92 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
93 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
94 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
96 static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
97 int AgentId, int HvRc)
102 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
103 Error_Text, Bus, SubBus, AgentId, HvRc);
107 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
109 static struct iSeries_Device_Node *build_device_node(HvBusNumber Bus,
110 HvSubBusNumber SubBus, int AgentId, int Function)
112 struct iSeries_Device_Node *node;
114 PPCDBG(PPCDBG_BUSWALK,
115 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
116 Bus, SubBus, AgentId, Function);
118 node = kmalloc(sizeof(struct iSeries_Device_Node), GFP_KERNEL);
122 memset(node, 0, sizeof(struct iSeries_Device_Node));
123 list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
125 node->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
127 node->DsaAddr.DsaAddr = 0;
128 node->DsaAddr.Dsa.busNumber = Bus;
129 node->DsaAddr.Dsa.subBusNumber = SubBus;
130 node->DsaAddr.Dsa.deviceId = 0x10;
131 node->AgentId = AgentId;
132 node->DevFn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
134 iSeries_Get_Location_Code(node);
135 PCIFR("Device 0x%02X.%2X, Node:0x%p ", ISERIES_BUS(node),
136 ISERIES_DEVFUN(node), node);
141 * unsigned long __init find_and_init_phbs(void)
144 * This function checks for all possible system PCI host bridges that connect
145 * PCI buses. The system hypervisor is queried as to the guest partition
146 * ownership status. A pci_controller is built for any bus which is partially
147 * owned or fully owned by this guest partition.
149 unsigned long __init find_and_init_phbs(void)
151 struct pci_controller *phb;
154 PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
156 /* Check all possible buses. */
157 for (bus = 0; bus < 256; bus++) {
158 int ret = HvCallXm_testBus(bus);
160 printk("bus %d appears to exist\n", bus);
161 phb = pci_alloc_pci_controller(phb_type_hypervisor);
163 PCIFR("Allocate pci_controller failed.");
166 phb->pci_mem_offset = phb->local_number = bus;
167 phb->first_busno = bus;
168 phb->last_busno = bus;
169 phb->ops = &iSeries_pci_ops;
171 PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
173 PCIFR("Create iSeries PHB controller: %04X", bus);
175 /* Find and connect the devices. */
176 iSeries_Scan_PHBs_Slots(phb);
179 * Check for Unexpected Return code, a clue that something
182 else if (ret != 0x0301)
183 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
190 * iSeries_pcibios_init
192 * Chance to initialize and structures or variable before PCI Bus walk.
194 void iSeries_pcibios_init(void)
196 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
197 iSeries_IoMmTable_Initialize();
198 find_and_init_phbs();
199 /* pci_assign_all_busses = 0; SFRXXX*/
200 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
204 * iSeries_pci_final_fixup(void)
206 void __init iSeries_pci_final_fixup(void)
208 struct pci_dev *pdev = NULL;
209 struct iSeries_Device_Node *node;
213 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
215 /* Fix up at the device node and pci_dev relationship */
216 mf_displaySrc(0xC9000100);
218 printk("pcibios_final_fixup\n");
219 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))
221 node = find_Device_Node(pdev->bus->number, pdev->devfn);
222 printk("pci dev %p (%x.%x), node %p\n", pdev,
223 pdev->bus->number, pdev->devfn, node);
227 pdev->sysdata = (void *)node;
229 PPCDBG(PPCDBG_BUSWALK,
230 "pdev 0x%p <==> DevNode 0x%p\n",
232 iSeries_allocateDeviceBars(pdev);
233 iSeries_Device_Information(pdev, Buffer,
235 printk("%d. %s\n", DeviceCount, Buffer);
236 iommu_devnode_init(node);
238 printk("PCI: Device Tree not found for 0x%016lX\n",
239 (unsigned long)pdev);
240 pdev->irq = node->Irq;
242 iSeries_IoMmTable_Status();
243 iSeries_activate_IRQs();
244 mf_displaySrc(0xC9000200);
247 void pcibios_fixup_bus(struct pci_bus *PciBus)
249 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
253 void pcibios_fixup_resources(struct pci_dev *pdev)
255 PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
259 * Loop through each node function to find usable EADs bridges.
261 static void iSeries_Scan_PHBs_Slots(struct pci_controller *Phb)
263 struct HvCallPci_DeviceInfo *DevInfo;
264 HvBusNumber bus = Phb->local_number; /* System Bus */
265 const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
268 const int MaxAgents = 8;
270 DevInfo = (struct HvCallPci_DeviceInfo*)
271 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
276 * Probe for EADs Bridges
278 for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
279 HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
280 ISERIES_HV_ADDR(DevInfo),
281 sizeof(struct HvCallPci_DeviceInfo));
283 if (DevInfo->deviceType == HvCallPci_NodeDevice)
284 iSeries_Scan_EADs_Bridge(bus, SubBus, IdSel);
286 printk("PCI: Invalid System Configuration(0x%02X)"
287 " for bus 0x%02x id 0x%02x.\n",
288 DevInfo->deviceType, bus, IdSel);
291 pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
296 static void iSeries_Scan_EADs_Bridge(HvBusNumber bus, HvSubBusNumber SubBus,
299 struct HvCallPci_BridgeInfo *BridgeInfo;
304 BridgeInfo = (struct HvCallPci_BridgeInfo *)
305 kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
306 if (BridgeInfo == NULL)
309 /* Note: hvSubBus and irq is always be 0 at this level! */
310 for (Function = 0; Function < 8; ++Function) {
311 AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
312 HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
314 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
315 bus, IdSel, Function, AgentId);
316 /* Connect EADs: 0x18.00.12 = 0x00 */
317 PPCDBG(PPCDBG_BUSWALK,
318 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
319 bus, SubBus, AgentId);
320 HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
321 ISERIES_HV_ADDR(BridgeInfo),
322 sizeof(struct HvCallPci_BridgeInfo));
324 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
325 BridgeInfo->busUnitInfo.deviceType,
326 BridgeInfo->subBusNumber,
327 BridgeInfo->maxAgents,
328 BridgeInfo->maxSubBusNumber,
329 BridgeInfo->logicalSlotNumber);
330 PPCDBG(PPCDBG_BUSWALK,
331 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
332 BridgeInfo->busUnitInfo.deviceType,
333 BridgeInfo->subBusNumber,
334 BridgeInfo->maxAgents,
335 BridgeInfo->maxSubBusNumber,
336 BridgeInfo->logicalSlotNumber);
338 if (BridgeInfo->busUnitInfo.deviceType ==
339 HvCallPci_BridgeDevice) {
340 /* Scan_Bridge_Slot...: 0x18.00.12 */
341 iSeries_Scan_Bridge_Slot(bus, BridgeInfo);
343 printk("PCI: Invalid Bridge Configuration(0x%02X)",
344 BridgeInfo->busUnitInfo.deviceType);
346 } else if (HvRc != 0x000B)
347 pci_Log_Error("EADs Connect",
348 bus, SubBus, AgentId, HvRc);
354 * This assumes that the node slot is always on the primary bus!
356 static int iSeries_Scan_Bridge_Slot(HvBusNumber Bus,
357 struct HvCallPci_BridgeInfo *BridgeInfo)
359 struct iSeries_Device_Node *node;
360 HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
364 int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
365 int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
366 HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
368 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
369 Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
370 PPCDBG(PPCDBG_BUSWALK,
371 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
372 Bus, 0, EADsIdSel, Irq);
375 * Connect all functions of any device found.
377 for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
378 for (Function = 0; Function < 8; ++Function) {
379 HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
380 HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
383 pci_Log_Error("Connect Bus Unit",
384 Bus, SubBus, AgentId, HvRc);
388 HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
389 PCI_VENDOR_ID, &VendorId);
391 pci_Log_Error("Read Vendor",
392 Bus, SubBus, AgentId, HvRc);
395 printk("read vendor ID: %x\n", VendorId);
397 /* FoundDevice: 0x18.28.10 = 0x12AE */
398 PPCDBG(PPCDBG_BUSWALK,
399 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
400 Bus, SubBus, AgentId, VendorId, Irq);
401 HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
402 PCI_INTERRUPT_LINE, Irq);
404 pci_Log_Error("PciCfgStore Irq Failed!",
405 Bus, SubBus, AgentId, HvRc);
408 node = build_device_node(Bus, SubBus, EADsIdSel, Function);
409 node->Vendor = VendorId;
411 node->LogicalSlot = BridgeInfo->logicalSlotNumber;
413 } /* for (Function = 0; Function < 8; ++Function) */
414 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
419 * I/0 Memory copy MUST use mmio commands on iSeries
420 * To do; For performance, include the hv call directly
422 void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
425 long NumberOfBytes = Count;
427 while (NumberOfBytes > 0) {
428 iSeries_Write_Byte(ByteValue, dest++);
432 EXPORT_SYMBOL(iSeries_memset_io);
434 void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
437 long NumberOfBytes = count;
439 while (NumberOfBytes > 0) {
440 iSeries_Write_Byte(*src++, dest++);
444 EXPORT_SYMBOL(iSeries_memcpy_toio);
446 void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
449 long NumberOfBytes = count;
451 while (NumberOfBytes > 0) {
452 *dst++ = iSeries_Read_Byte(src++);
456 EXPORT_SYMBOL(iSeries_memcpy_fromio);
459 * Look down the chain to find the matching Device Device
461 static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn)
463 struct list_head *pos;
465 list_for_each(pos, &iSeries_Global_Device_List) {
466 struct iSeries_Device_Node *node =
467 list_entry(pos, struct iSeries_Device_Node, Device_List);
469 if ((bus == ISERIES_BUS(node)) && (devfn == node->DevFn))
477 * Returns the device node for the passed pci_dev
478 * Sanity Check Node PciDev to passed pci_dev
479 * If none is found, returns a NULL which the client must handle.
481 static struct iSeries_Device_Node *get_Device_Node(struct pci_dev *pdev)
483 struct iSeries_Device_Node *node;
485 node = pdev->sysdata;
486 if (node == NULL || node->PciDev != pdev)
487 node = find_Device_Node(pdev->bus->number, pdev->devfn);
493 * Config space read and write functions.
494 * For now at least, we look for the device node for the bus and devfn
495 * that we are asked to access. It may be possible to translate the devfn
496 * to a subbus and deviceid more directly.
498 static u64 hv_cfg_read_func[4] = {
499 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
500 HvCallPciConfigLoad32, HvCallPciConfigLoad32
503 static u64 hv_cfg_write_func[4] = {
504 HvCallPciConfigStore8, HvCallPciConfigStore16,
505 HvCallPciConfigStore32, HvCallPciConfigStore32
509 * Read PCI config space
511 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
512 int offset, int size, u32 *val)
514 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
516 struct HvCallPci_LoadReturn ret;
519 return PCIBIOS_DEVICE_NOT_FOUND;
521 fn = hv_cfg_read_func[(size - 1) & 3];
522 HvCall3Ret16(fn, &ret, node->DsaAddr.DsaAddr, offset, 0);
526 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
534 * Write PCI config space
537 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
538 int offset, int size, u32 val)
540 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
545 return PCIBIOS_DEVICE_NOT_FOUND;
547 fn = hv_cfg_write_func[(size - 1) & 3];
548 ret = HvCall4(fn, node->DsaAddr.DsaAddr, offset, val, 0);
551 return PCIBIOS_DEVICE_NOT_FOUND;
556 static struct pci_ops iSeries_pci_ops = {
557 .read = iSeries_pci_read_config,
558 .write = iSeries_pci_write_config
563 * -> On Failure, print and log information.
564 * Increment Retry Count, if exceeds max, panic partition.
565 * -> If in retry, print and log success
567 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
568 * PCI: Device 23.90 ReadL Retry( 1)
569 * PCI: Device 23.90 ReadL Retry Successful(1)
571 static int CheckReturnCode(char *TextHdr, struct iSeries_Device_Node *DevNode,
577 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
578 TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
579 DevNode->IoRetry, (int)ret);
581 * Bump the retry and check for retry count exceeded.
582 * If, Exceeded, panic the system.
584 if ((DevNode->IoRetry > Pci_Retry_Max) &&
585 (Pci_Error_Flag > 0)) {
586 mf_displaySrc(0xB6000103);
588 panic("PCI: Hardware I/O Error, SRC B6000103, "
589 "Automatic Reboot Disabled.\n");
591 return -1; /* Retry Try */
593 /* If retry was in progress, log success and rest retry count */
594 if (DevNode->IoRetry > 0) {
595 PCIFR("%s: Device 0x%04X:%02X Retry Successful(%2d).",
596 TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
598 DevNode->IoRetry = 0;
604 * Translate the I/O Address into a device node, bar, and bar offset.
605 * Note: Make sure the passed variable end up on the stack to avoid
606 * the exposure of being device global.
608 static inline struct iSeries_Device_Node *xlateIoMmAddress(const volatile void __iomem *IoAddress,
609 u64 *dsaptr, u64 *BarOffsetPtr)
611 unsigned long OrigIoAddr;
612 unsigned long BaseIoAddr;
613 unsigned long TableIndex;
614 struct iSeries_Device_Node *DevNode;
616 OrigIoAddr = (unsigned long __force)IoAddress;
617 if ((OrigIoAddr < iSeries_Base_Io_Memory) ||
618 (OrigIoAddr >= iSeries_Max_Io_Memory))
620 BaseIoAddr = OrigIoAddr - iSeries_Base_Io_Memory;
621 TableIndex = BaseIoAddr / iSeries_IoMmTable_Entry_Size;
622 DevNode = iSeries_IoMmTable[TableIndex];
624 if (DevNode != NULL) {
625 int barnum = iSeries_IoBarTable[TableIndex];
626 *dsaptr = DevNode->DsaAddr.DsaAddr | (barnum << 24);
627 *BarOffsetPtr = BaseIoAddr % iSeries_IoMmTable_Entry_Size;
629 panic("PCI: Invalid PCI IoAddress detected!\n");
634 * Read MM I/O Instructions for the iSeries
635 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
636 * else, data is returned in big Endian format.
638 * iSeries_Read_Byte = Read Byte ( 8 bit)
639 * iSeries_Read_Word = Read Word (16 bit)
640 * iSeries_Read_Long = Read Long (32 bit)
642 u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
646 struct HvCallPci_LoadReturn ret;
647 struct iSeries_Device_Node *DevNode =
648 xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
650 if (DevNode == NULL) {
651 static unsigned long last_jiffies;
652 static int num_printed;
654 if ((jiffies - last_jiffies) > 60 * HZ) {
655 last_jiffies = jiffies;
658 if (num_printed++ < 10)
659 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
664 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
665 } while (CheckReturnCode("RDB", DevNode, ret.rc) != 0);
667 return (u8)ret.value;
669 EXPORT_SYMBOL(iSeries_Read_Byte);
671 u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
675 struct HvCallPci_LoadReturn ret;
676 struct iSeries_Device_Node *DevNode =
677 xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
679 if (DevNode == NULL) {
680 static unsigned long last_jiffies;
681 static int num_printed;
683 if ((jiffies - last_jiffies) > 60 * HZ) {
684 last_jiffies = jiffies;
687 if (num_printed++ < 10)
688 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
693 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
695 } while (CheckReturnCode("RDW", DevNode, ret.rc) != 0);
697 return swab16((u16)ret.value);
699 EXPORT_SYMBOL(iSeries_Read_Word);
701 u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
705 struct HvCallPci_LoadReturn ret;
706 struct iSeries_Device_Node *DevNode =
707 xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
709 if (DevNode == NULL) {
710 static unsigned long last_jiffies;
711 static int num_printed;
713 if ((jiffies - last_jiffies) > 60 * HZ) {
714 last_jiffies = jiffies;
717 if (num_printed++ < 10)
718 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
723 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
725 } while (CheckReturnCode("RDL", DevNode, ret.rc) != 0);
727 return swab32((u32)ret.value);
729 EXPORT_SYMBOL(iSeries_Read_Long);
732 * Write MM I/O Instructions for the iSeries
734 * iSeries_Write_Byte = Write Byte (8 bit)
735 * iSeries_Write_Word = Write Word(16 bit)
736 * iSeries_Write_Long = Write Long(32 bit)
738 void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
743 struct iSeries_Device_Node *DevNode =
744 xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
746 if (DevNode == NULL) {
747 static unsigned long last_jiffies;
748 static int num_printed;
750 if ((jiffies - last_jiffies) > 60 * HZ) {
751 last_jiffies = jiffies;
754 if (num_printed++ < 10)
755 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
759 ++Pci_Io_Write_Count;
760 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
761 } while (CheckReturnCode("WWB", DevNode, rc) != 0);
763 EXPORT_SYMBOL(iSeries_Write_Byte);
765 void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
770 struct iSeries_Device_Node *DevNode =
771 xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
773 if (DevNode == NULL) {
774 static unsigned long last_jiffies;
775 static int num_printed;
777 if ((jiffies - last_jiffies) > 60 * HZ) {
778 last_jiffies = jiffies;
781 if (num_printed++ < 10)
782 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
786 ++Pci_Io_Write_Count;
787 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
788 } while (CheckReturnCode("WWW", DevNode, rc) != 0);
790 EXPORT_SYMBOL(iSeries_Write_Word);
792 void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
797 struct iSeries_Device_Node *DevNode =
798 xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
800 if (DevNode == NULL) {
801 static unsigned long last_jiffies;
802 static int num_printed;
804 if ((jiffies - last_jiffies) > 60 * HZ) {
805 last_jiffies = jiffies;
808 if (num_printed++ < 10)
809 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
813 ++Pci_Io_Write_Count;
814 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
815 } while (CheckReturnCode("WWL", DevNode, rc) != 0);
817 EXPORT_SYMBOL(iSeries_Write_Long);