2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
5 * Module name: iSeries_setup.c
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
10 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/threads.h>
24 #include <linux/smp.h>
25 #include <linux/param.h>
26 #include <linux/string.h>
27 #include <linux/bootmem.h>
28 #include <linux/initrd.h>
29 #include <linux/seq_file.h>
30 #include <linux/kdev_t.h>
31 #include <linux/major.h>
32 #include <linux/root_dev.h>
34 #include <asm/processor.h>
35 #include <asm/machdep.h>
38 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
40 #include <asm/cputable.h>
41 #include <asm/sections.h>
44 #include "iSeries_setup.h"
47 #include <asm/cache.h>
48 #include <asm/sections.h>
49 #include <asm/iSeries/LparData.h>
50 #include <asm/iSeries/HvCallHpt.h>
51 #include <asm/iSeries/HvLpConfig.h>
52 #include <asm/iSeries/HvCallEvent.h>
53 #include <asm/iSeries/HvCallSm.h>
54 #include <asm/iSeries/HvCallXm.h>
55 #include <asm/iSeries/ItLpQueue.h>
56 #include <asm/iSeries/IoHriMainStore.h>
57 #include <asm/iSeries/iSeries_proc.h>
58 #include <asm/iSeries/mf.h>
59 #include <asm/iSeries/HvLpEvent.h>
61 extern void hvlog(char *fmt, ...);
64 #define DBG(fmt...) hvlog(fmt)
69 /* Function Prototypes */
70 extern void ppcdbg_initialize(void);
72 static void build_iSeries_Memory_Map(void);
73 static void setup_iSeries_cache_sizes(void);
74 static void iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr);
75 extern void iSeries_setup_arch(void);
76 extern void iSeries_pci_final_fixup(void);
78 /* Global Variables */
79 static unsigned long procFreqHz;
80 static unsigned long procFreqMhz;
81 static unsigned long procFreqMhzHundreths;
83 static unsigned long tbFreqHz;
84 static unsigned long tbFreqMhz;
85 static unsigned long tbFreqMhzHundreths;
87 int piranha_simulator;
89 extern int rd_size; /* Defined in drivers/block/rd.c */
90 extern unsigned long klimit;
91 extern unsigned long embedded_sysmap_start;
92 extern unsigned long embedded_sysmap_end;
94 extern unsigned long iSeries_recal_tb;
95 extern unsigned long iSeries_recal_titan;
97 static int mf_initialized;
100 unsigned long absStart;
101 unsigned long absEnd;
102 unsigned long logicalStart;
103 unsigned long logicalEnd;
107 * Process the main store vpd to determine where the holes in memory are
108 * and return the number of physical blocks and fill in the array of
111 unsigned long iSeries_process_Condor_mainstore_vpd(struct MemoryBlock *mb_array,
112 unsigned long max_entries)
114 unsigned long holeFirstChunk, holeSizeChunks;
115 unsigned long numMemoryBlocks = 1;
116 struct IoHriMainStoreSegment4 *msVpd =
117 (struct IoHriMainStoreSegment4 *)xMsVpd;
118 unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
119 unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
120 unsigned long holeSize = holeEnd - holeStart;
122 printk("Mainstore_VPD: Condor\n");
124 * Determine if absolute memory has any
125 * holes so that we can interpret the
126 * access map we get back from the hypervisor
129 mb_array[0].logicalStart = 0;
130 mb_array[0].logicalEnd = 0x100000000;
131 mb_array[0].absStart = 0;
132 mb_array[0].absEnd = 0x100000000;
136 holeStart = holeStart & 0x000fffffffffffff;
137 holeStart = addr_to_chunk(holeStart);
138 holeFirstChunk = holeStart;
139 holeSize = addr_to_chunk(holeSize);
140 holeSizeChunks = holeSize;
141 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
142 holeFirstChunk, holeSizeChunks );
143 mb_array[0].logicalEnd = holeFirstChunk;
144 mb_array[0].absEnd = holeFirstChunk;
145 mb_array[1].logicalStart = holeFirstChunk;
146 mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks;
147 mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
148 mb_array[1].absEnd = 0x100000000;
150 return numMemoryBlocks;
153 #define MaxSegmentAreas 32
154 #define MaxSegmentAdrRangeBlocks 128
155 #define MaxAreaRangeBlocks 4
157 unsigned long iSeries_process_Regatta_mainstore_vpd(
158 struct MemoryBlock *mb_array, unsigned long max_entries)
160 struct IoHriMainStoreSegment5 *msVpdP =
161 (struct IoHriMainStoreSegment5 *)xMsVpd;
162 unsigned long numSegmentBlocks = 0;
163 u32 existsBits = msVpdP->msAreaExists;
164 unsigned long area_num;
166 printk("Mainstore_VPD: Regatta\n");
168 for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
169 unsigned long numAreaBlocks;
170 struct IoHriMainStoreArea4 *currentArea;
172 if (existsBits & 0x80000000) {
173 unsigned long block_num;
175 currentArea = &msVpdP->msAreaArray[area_num];
176 numAreaBlocks = currentArea->numAdrRangeBlocks;
177 printk("ms_vpd: processing area %2ld blocks=%ld",
178 area_num, numAreaBlocks);
179 for (block_num = 0; block_num < numAreaBlocks;
181 /* Process an address range block */
182 struct MemoryBlock tempBlock;
186 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
188 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
189 tempBlock.logicalStart = 0;
190 tempBlock.logicalEnd = 0;
191 printk("\n block %ld absStart=%016lx absEnd=%016lx",
192 block_num, tempBlock.absStart,
195 for (i = 0; i < numSegmentBlocks; ++i) {
196 if (mb_array[i].absStart ==
200 if (i == numSegmentBlocks) {
201 if (numSegmentBlocks == max_entries)
202 panic("iSeries_process_mainstore_vpd: too many memory blocks");
203 mb_array[numSegmentBlocks] = tempBlock;
206 printk(" (duplicate)");
212 /* Now sort the blocks found into ascending sequence */
213 if (numSegmentBlocks > 1) {
216 for (m = 0; m < numSegmentBlocks - 1; ++m) {
217 for (n = numSegmentBlocks - 1; m < n; --n) {
218 if (mb_array[n].absStart <
219 mb_array[n-1].absStart) {
220 struct MemoryBlock tempBlock;
222 tempBlock = mb_array[n];
223 mb_array[n] = mb_array[n-1];
224 mb_array[n-1] = tempBlock;
230 * Assign "logical" addresses to each block. These
231 * addresses correspond to the hypervisor "bitmap" space.
232 * Convert all addresses into units of 256K chunks.
235 unsigned long i, nextBitmapAddress;
237 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
238 nextBitmapAddress = 0;
239 for (i = 0; i < numSegmentBlocks; ++i) {
240 unsigned long length = mb_array[i].absEnd -
241 mb_array[i].absStart;
243 mb_array[i].logicalStart = nextBitmapAddress;
244 mb_array[i].logicalEnd = nextBitmapAddress + length;
245 nextBitmapAddress += length;
246 printk(" Bitmap range: %016lx - %016lx\n"
247 " Absolute range: %016lx - %016lx\n",
248 mb_array[i].logicalStart,
249 mb_array[i].logicalEnd,
250 mb_array[i].absStart, mb_array[i].absEnd);
251 mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
253 mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
255 mb_array[i].logicalStart =
256 addr_to_chunk(mb_array[i].logicalStart);
257 mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
261 return numSegmentBlocks;
264 unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
265 unsigned long max_entries)
268 unsigned long mem_blocks = 0;
270 if (cur_cpu_spec->cpu_features & CPU_FTR_SLB)
271 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
274 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
277 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
278 for (i = 0; i < mem_blocks; ++i) {
279 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
280 " abs chunks %016lx - %016lx\n",
281 i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
282 mb_array[i].absStart, mb_array[i].absEnd);
287 static void __init iSeries_parse_cmdline(void)
291 /* copy the command line parameter from the primary VSP */
292 HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
293 HvLpDma_Direction_RemoteToLocal);
298 if (!*p || *p == '\n')
305 /*static*/ void __init iSeries_init_early(void)
307 DBG(" -> iSeries_init_early()\n");
311 #if defined(CONFIG_BLK_DEV_INITRD)
313 * If the init RAM disk has been configured and there is
314 * a non-zero starting address for it, set it up
317 initrd_start = (unsigned long)__va(naca.xRamDisk);
318 initrd_end = initrd_start + naca.xRamDiskSize * PAGE_SIZE;
319 initrd_below_start_ok = 1; // ramdisk in kernel space
320 ROOT_DEV = Root_RAM0;
321 if (((rd_size * 1024) / PAGE_SIZE) < naca.xRamDiskSize)
322 rd_size = (naca.xRamDiskSize * PAGE_SIZE) / 1024;
324 #endif /* CONFIG_BLK_DEV_INITRD */
326 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
329 iSeries_recal_tb = get_tb();
330 iSeries_recal_titan = HvCallXm_loadTod();
333 * Cache sizes must be initialized before hpte_init_iSeries is called
334 * as the later need them for flush_icache_range()
336 setup_iSeries_cache_sizes();
339 * Initialize the hash table management pointers
344 * Initialize the DMA/TCE management
346 iommu_init_early_iSeries();
349 * Initialize the table which translate Linux physical addresses to
350 * AS/400 absolute addresses
352 build_iSeries_Memory_Map();
354 /* Initialize machine-dependency vectors */
358 if (itLpNaca.xPirEnvironMode == 0)
359 piranha_simulator = 1;
361 /* Associate Lp Event Queue 0 with processor 0 */
362 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
368 /* If we were passed an initrd, set the ROOT_DEV properly if the values
369 * look sensible. If not, clear initrd reference.
371 #ifdef CONFIG_BLK_DEV_INITRD
372 if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE &&
373 initrd_end > initrd_start)
374 ROOT_DEV = Root_RAM0;
376 initrd_start = initrd_end = 0;
377 #endif /* CONFIG_BLK_DEV_INITRD */
380 iSeries_parse_cmdline();
382 DBG(" <- iSeries_init_early()\n");
386 * The iSeries may have very large memories ( > 128 GB ) and a partition
387 * may get memory in "chunks" that may be anywhere in the 2**52 real
388 * address space. The chunks are 256K in size. To map this to the
389 * memory model Linux expects, the AS/400 specific code builds a
390 * translation table to translate what Linux thinks are "physical"
391 * addresses to the actual real addresses. This allows us to make
392 * it appear to Linux that we have contiguous memory starting at
393 * physical address zero while in fact this could be far from the truth.
394 * To avoid confusion, I'll let the words physical and/or real address
395 * apply to the Linux addresses while I'll use "absolute address" to
396 * refer to the actual hardware real address.
398 * build_iSeries_Memory_Map gets information from the Hypervisor and
399 * looks at the Main Store VPD to determine the absolute addresses
400 * of the memory that has been assigned to our partition and builds
401 * a table used to translate Linux's physical addresses to these
402 * absolute addresses. Absolute addresses are needed when
403 * communicating with the hypervisor (e.g. to build HPT entries)
406 static void __init build_iSeries_Memory_Map(void)
408 u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
410 u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
412 u32 totalChunks,moreChunks;
413 u32 currChunk, thisChunk, absChunk;
417 struct MemoryBlock mb[32];
418 unsigned long numMemoryBlocks, curBlock;
420 /* Chunk size on iSeries is 256K bytes */
421 totalChunks = (u32)HvLpConfig_getMsChunks();
422 klimit = msChunks_alloc(klimit, totalChunks, 1UL << 18);
425 * Get absolute address of our load area
426 * and map it to physical address 0
427 * This guarantees that the loadarea ends up at physical 0
428 * otherwise, it might not be returned by PLIC as the first
432 loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
433 loadAreaSize = itLpNaca.xLoadAreaChunks;
436 * Only add the pages already mapped here.
437 * Otherwise we might add the hpt pages
438 * The rest of the pages of the load area
439 * aren't in the HPT yet and can still
440 * be assigned an arbitrary physical address
442 if ((loadAreaSize * 64) > HvPagesToMap)
443 loadAreaSize = HvPagesToMap / 64;
445 loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
448 * TODO Do we need to do something if the HPT is in the 64MB load area?
449 * This would be required if the itLpNaca.xLoadAreaChunks includes
453 printk("Mapping load area - physical addr = 0000000000000000\n"
454 " absolute addr = %016lx\n",
455 chunk_to_addr(loadAreaFirstChunk));
456 printk("Load area size %dK\n", loadAreaSize * 256);
458 for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
459 msChunks.abs[nextPhysChunk] =
460 loadAreaFirstChunk + nextPhysChunk;
463 * Get absolute address of our HPT and remember it so
464 * we won't map it to any physical address
466 hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
467 hptSizePages = (u32)HvCallHpt_getHptPages();
468 hptSizeChunks = hptSizePages >> (msChunks.chunk_shift - PAGE_SHIFT);
469 hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
471 printk("HPT absolute addr = %016lx, size = %dK\n",
472 chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
474 /* Fill in the hashed page table hash mask */
475 num_ptegs = hptSizePages *
476 (PAGE_SIZE / (sizeof(HPTE) * HPTES_PER_GROUP));
477 htab_hash_mask = num_ptegs - 1;
480 * The actual hashed page table is in the hypervisor,
481 * we have no direct access
486 * Determine if absolute memory has any
487 * holes so that we can interpret the
488 * access map we get back from the hypervisor
491 numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
494 * Process the main store access map from the hypervisor
495 * to build up our physical -> absolute translation table
500 moreChunks = totalChunks;
503 map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
505 thisChunk = currChunk;
507 chunkBit = map >> 63;
511 while (thisChunk >= mb[curBlock].logicalEnd) {
513 if (curBlock >= numMemoryBlocks)
514 panic("out of memory blocks");
516 if (thisChunk < mb[curBlock].logicalStart)
517 panic("memory block error");
519 absChunk = mb[curBlock].absStart +
520 (thisChunk - mb[curBlock].logicalStart);
521 if (((absChunk < hptFirstChunk) ||
522 (absChunk > hptLastChunk)) &&
523 ((absChunk < loadAreaFirstChunk) ||
524 (absChunk > loadAreaLastChunk))) {
525 msChunks.abs[nextPhysChunk] = absChunk;
536 * main store size (in chunks) is
537 * totalChunks - hptSizeChunks
538 * which should be equal to
541 systemcfg->physicalMemorySize = chunk_to_addr(nextPhysChunk);
543 /* Bolt kernel mappings for all of memory */
544 iSeries_bolt_kernel(0, systemcfg->physicalMemorySize);
547 lmb_add(0, systemcfg->physicalMemorySize);
548 lmb_analyze(); /* ?? */
549 lmb_reserve(0, __pa(klimit));
553 * Set up the variables that describe the cache line sizes
556 static void __init setup_iSeries_cache_sizes(void)
559 unsigned int procIx = get_paca()->lppaca.dyn_hv_phys_proc_index;
561 systemcfg->icache_size =
562 ppc64_caches.isize = xIoHriProcessorVpd[procIx].xInstCacheSize * 1024;
563 systemcfg->icache_line_size =
564 ppc64_caches.iline_size =
565 xIoHriProcessorVpd[procIx].xInstCacheOperandSize;
566 systemcfg->dcache_size =
568 xIoHriProcessorVpd[procIx].xDataL1CacheSizeKB * 1024;
569 systemcfg->dcache_line_size =
570 ppc64_caches.dline_size =
571 xIoHriProcessorVpd[procIx].xDataCacheOperandSize;
572 ppc64_caches.ilines_per_page = PAGE_SIZE / ppc64_caches.iline_size;
573 ppc64_caches.dlines_per_page = PAGE_SIZE / ppc64_caches.dline_size;
575 i = ppc64_caches.iline_size;
577 while ((i = (i / 2)))
579 ppc64_caches.log_iline_size = n;
581 i = ppc64_caches.dline_size;
583 while ((i = (i / 2)))
585 ppc64_caches.log_dline_size = n;
587 printk("D-cache line size = %d\n",
588 (unsigned int)ppc64_caches.dline_size);
589 printk("I-cache line size = %d\n",
590 (unsigned int)ppc64_caches.iline_size);
594 * Create a pte. Used during initialization only.
596 static void iSeries_make_pte(unsigned long va, unsigned long pa,
599 HPTE local_hpte, rhpte;
600 unsigned long hash, vpn;
603 vpn = va >> PAGE_SHIFT;
604 hash = hpt_hash(vpn, 0);
606 local_hpte.dw1.dword1 = pa | mode;
607 local_hpte.dw0.dword0 = 0;
608 local_hpte.dw0.dw0.avpn = va >> 23;
609 local_hpte.dw0.dw0.bolted = 1; /* bolted */
610 local_hpte.dw0.dw0.v = 1;
612 slot = HvCallHpt_findValid(&rhpte, vpn);
614 /* Must find space in primary group */
615 panic("hash_page: hpte already exists\n");
617 HvCallHpt_addValidate(slot, 0, (HPTE *)&local_hpte );
621 * Bolt the kernel addr space into the HPT
623 static void __init iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr)
626 unsigned long mode_rw = _PAGE_ACCESSED | _PAGE_COHERENT | PP_RWXX;
629 for (pa = saddr; pa < eaddr ;pa += PAGE_SIZE) {
630 unsigned long ea = (unsigned long)__va(pa);
631 unsigned long vsid = get_kernel_vsid(ea);
632 unsigned long va = (vsid << 28) | (pa & 0xfffffff);
633 unsigned long vpn = va >> PAGE_SHIFT;
634 unsigned long slot = HvCallHpt_findValid(&hpte, vpn);
636 if (hpte.dw0.dw0.v) {
637 /* HPTE exists, so just bolt it */
638 HvCallHpt_setSwBits(slot, 0x10, 0);
639 /* And make sure the pp bits are correct */
640 HvCallHpt_setPp(slot, PP_RWXX);
642 /* No HPTE exists, so create a new bolted one */
643 iSeries_make_pte(va, phys_to_abs(pa), mode_rw);
647 extern unsigned long ppc_proc_freq;
648 extern unsigned long ppc_tb_freq;
653 void __init iSeries_setup_arch(void)
656 unsigned procIx = get_paca()->lppaca.dyn_hv_phys_proc_index;
658 /* Add an eye catcher and the systemcfg layout version number */
659 strcpy(systemcfg->eye_catcher, "SYSTEMCFG:PPC64");
660 systemcfg->version.major = SYSTEMCFG_MAJOR;
661 systemcfg->version.minor = SYSTEMCFG_MINOR;
663 /* Setup the Lp Event Queue */
665 /* Allocate a page for the Event Stack
666 * The hypervisor wants the absolute real address, so
667 * we subtract out the KERNELBASE and add in the
668 * absolute real address of the kernel load area
670 eventStack = alloc_bootmem_pages(LpEventStackSize);
671 memset(eventStack, 0, LpEventStackSize);
673 /* Invoke the hypervisor to initialize the event stack */
674 HvCallEvent_setLpEventStack(0, eventStack, LpEventStackSize);
676 /* Initialize fields in our Lp Event Queue */
677 xItLpQueue.xSlicEventStackPtr = (char *)eventStack;
678 xItLpQueue.xSlicCurEventPtr = (char *)eventStack;
679 xItLpQueue.xSlicLastValidEventPtr = (char *)eventStack +
680 (LpEventStackSize - LpEventMaxSize);
681 xItLpQueue.xIndex = 0;
683 /* Compute processor frequency */
684 procFreqHz = ((1UL << 34) * 1000000) /
685 xIoHriProcessorVpd[procIx].xProcFreq;
686 procFreqMhz = procFreqHz / 1000000;
687 procFreqMhzHundreths = (procFreqHz / 10000) - (procFreqMhz * 100);
688 ppc_proc_freq = procFreqHz;
690 /* Compute time base frequency */
691 tbFreqHz = ((1UL << 32) * 1000000) /
692 xIoHriProcessorVpd[procIx].xTimeBaseFreq;
693 tbFreqMhz = tbFreqHz / 1000000;
694 tbFreqMhzHundreths = (tbFreqHz / 10000) - (tbFreqMhz * 100);
695 ppc_tb_freq = tbFreqHz;
697 printk("Max logical processors = %d\n",
698 itVpdAreas.xSlicMaxLogicalProcs);
699 printk("Max physical processors = %d\n",
700 itVpdAreas.xSlicMaxPhysicalProcs);
701 printk("Processor frequency = %lu.%02lu\n", procFreqMhz,
702 procFreqMhzHundreths);
703 printk("Time base frequency = %lu.%02lu\n", tbFreqMhz,
705 systemcfg->processor = xIoHriProcessorVpd[procIx].xPVR;
706 printk("Processor version = %x\n", systemcfg->processor);
709 void iSeries_get_cpuinfo(struct seq_file *m)
711 seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
718 int iSeries_get_irq(struct pt_regs *regs)
720 /* -2 means ignore this interrupt */
727 void iSeries_restart(char *cmd)
735 void iSeries_power_off(void)
743 void iSeries_halt(void)
749 unsigned long jdh_time = 0;
751 extern void setup_default_decr(void);
754 * void __init iSeries_calibrate_decr()
757 * This routine retrieves the internal processor frequency from the VPD,
758 * and sets up the kernel timer decrementer based on that value.
761 void __init iSeries_calibrate_decr(void)
763 unsigned long cyclesPerUsec;
764 struct div_result divres;
766 /* Compute decrementer (and TB) frequency in cycles/sec */
767 cyclesPerUsec = ppc_tb_freq / 1000000;
770 * Set the amount to refresh the decrementer by. This
771 * is the number of decrementer ticks it takes for
774 tb_ticks_per_jiffy = ppc_tb_freq / HZ;
777 /* TEST CODE FOR ADJTIME */
778 tb_ticks_per_jiffy += tb_ticks_per_jiffy / 5000;
779 /* END OF TEST CODE */
783 * tb_ticks_per_sec = freq; would give better accuracy
784 * but tb_ticks_per_sec = tb_ticks_per_jiffy*HZ; assures
785 * that jiffies (and xtime) will match the time returned
786 * by do_gettimeofday.
788 tb_ticks_per_sec = tb_ticks_per_jiffy * HZ;
789 tb_ticks_per_usec = cyclesPerUsec;
790 tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
791 div128_by_32(1024 * 1024, 0, tb_ticks_per_sec, &divres);
792 tb_to_xs = divres.result_low;
793 setup_default_decr();
796 void __init iSeries_progress(char * st, unsigned short code)
798 printk("Progress: [%04x] - %s\n", (unsigned)code, st);
799 if (!piranha_simulator && mf_initialized) {
801 mf_display_progress(code);
807 static void __init iSeries_fixup_klimit(void)
810 * Change klimit to take into account any ram disk
811 * that may be included
814 klimit = KERNELBASE + (u64)naca.xRamDisk +
815 (naca.xRamDiskSize * PAGE_SIZE);
818 * No ram disk was included - check and see if there
819 * was an embedded system map. Change klimit to take
820 * into account any embedded system map
822 if (embedded_sysmap_end)
823 klimit = KERNELBASE + ((embedded_sysmap_end + 4095) &
828 int __init iSeries_src_init(void)
830 /* clear the progress line */
831 ppc_md.progress(" ", 0xffff);
835 late_initcall(iSeries_src_init);
837 void __init iSeries_early_setup(void)
839 iSeries_fixup_klimit();
841 ppc_md.setup_arch = iSeries_setup_arch;
842 ppc_md.get_cpuinfo = iSeries_get_cpuinfo;
843 ppc_md.init_IRQ = iSeries_init_IRQ;
844 ppc_md.get_irq = iSeries_get_irq;
845 ppc_md.init_early = iSeries_init_early,
847 ppc_md.pcibios_fixup = iSeries_pci_final_fixup;
849 ppc_md.restart = iSeries_restart;
850 ppc_md.power_off = iSeries_power_off;
851 ppc_md.halt = iSeries_halt;
853 ppc_md.get_boot_time = iSeries_get_boot_time;
854 ppc_md.set_rtc_time = iSeries_set_rtc_time;
855 ppc_md.get_rtc_time = iSeries_get_rtc_time;
856 ppc_md.calibrate_decr = iSeries_calibrate_decr;
857 ppc_md.progress = iSeries_progress;