arch/ppc64/kernel/open_pic_defs.h

   1 /*
   2  *  linux/openpic.h -- OpenPIC definitions
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is based on the following documentation:
   7  *
   8  *      The Open Programmable Interrupt Controller (PIC)
   9  *      Register Interface Specification Revision 1.2
  10  *
  11  *      Issue Date: October 1995
  12  *
  13  *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
  14  *
  15  *      AMD is a registered trademark of Advanced Micro Devices, Inc.
  16  *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
  17  *      All Rights Reserved.
  18  *
  19  *  To receive a copy of this documentation, send an email to openpic@amd.com.
  20  *
  21  *  This file is subject to the terms and conditions of the GNU General Public
  22  *  License.  See the file COPYING in the main directory of this archive
  23  *  for more details.
  24  */
  25
  26 #ifndef _LINUX_OPENPIC_H
  27 #define _LINUX_OPENPIC_H
  28
  29 #ifdef __KERNEL__
  30
  31 #include <linux/config.h>
  32
  33 /*
  34  *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
  35  */
  36
  37 #define OPENPIC_MAX_SOURCES     2048
  38 #define OPENPIC_MAX_PROCESSORS  32
  39 #define OPENPIC_MAX_ISU         32
  40
  41 #define OPENPIC_NUM_TIMERS      4
  42 #define OPENPIC_NUM_IPI         4
  43 #define OPENPIC_NUM_PRI         16
  44 #define OPENPIC_NUM_VECTORS     OPENPIC_MAX_SOURCES
  45
  46 /*
  47  *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
  48  */
  49
  50 typedef struct _OpenPIC_Reg {
  51         u_int Reg;                                      /* Little endian! */
  52         char Pad[0xc];
  53 } OpenPIC_Reg;
  54
  55
  56 /*
  57  *  Per Processor Registers
  58  */
  59
  60 typedef struct _OpenPIC_Processor {
  61         /*
  62          *  Private Shadow Registers (for SLiC backwards compatibility)
  63          */
  64         u_int IPI0_Dispatch_Shadow;                     /* Write Only */
  65         char Pad1[0x4];
  66         u_int IPI0_Vector_Priority_Shadow;              /* Read/Write */
  67         char Pad2[0x34];
  68         /*
  69          *  Interprocessor Interrupt Command Ports
  70          */
  71         OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI];     /* Write Only */
  72         /*
  73          *  Current Task Priority Register
  74          */
  75         OpenPIC_Reg _Current_Task_Priority;             /* Read/Write */
  76         char Pad3[0x10];
  77         /*
  78          *  Interrupt Acknowledge Register
  79          */
  80         OpenPIC_Reg _Interrupt_Acknowledge;             /* Read Only */
  81         /*
  82          *  End of Interrupt (EOI) Register
  83          */
  84         OpenPIC_Reg _EOI;                               /* Read/Write */
  85         char Pad5[0xf40];
  86 } OpenPIC_Processor;
  87
  88
  89     /*
  90      *  Timer Registers
  91      */
  92
  93 typedef struct _OpenPIC_Timer {
  94         OpenPIC_Reg _Current_Count;                     /* Read Only */
  95         OpenPIC_Reg _Base_Count;                        /* Read/Write */
  96         OpenPIC_Reg _Vector_Priority;                   /* Read/Write */
  97         OpenPIC_Reg _Destination;                       /* Read/Write */
  98 } OpenPIC_Timer;
  99
 100
 101     /*
 102      *  Global Registers
 103      */
 104
 105 typedef struct _OpenPIC_Global {
 106         /*
 107          *  Feature Reporting Registers
 108          */
 109         OpenPIC_Reg _Feature_Reporting0;                /* Read Only */
 110         OpenPIC_Reg _Feature_Reporting1;                /* Future Expansion */
 111         /*
 112          *  Global Configuration Registers
 113          */
 114         OpenPIC_Reg _Global_Configuration0;             /* Read/Write */
 115         OpenPIC_Reg _Global_Configuration1;             /* Future Expansion */
 116         /*
 117          *  Vendor Specific Registers
 118          */
 119         OpenPIC_Reg _Vendor_Specific[4];
 120         /*
 121          *  Vendor Identification Register
 122          */
 123         OpenPIC_Reg _Vendor_Identification;             /* Read Only */
 124         /*
 125          *  Processor Initialization Register
 126          */
 127         OpenPIC_Reg _Processor_Initialization;          /* Read/Write */
 128         /*
 129          *  IPI Vector/Priority Registers
 130          */
 131         OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */
 132         /*
 133          *  Spurious Vector Register
 134          */
 135         OpenPIC_Reg _Spurious_Vector;                   /* Read/Write */
 136         /*
 137          *  Global Timer Registers
 138          */
 139         OpenPIC_Reg _Timer_Frequency;                   /* Read/Write */
 140         OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
 141         char Pad1[0xee00];
 142 } OpenPIC_Global;
 143
 144
 145     /*
 146      *  Interrupt Source Registers
 147      */
 148
 149 typedef struct _OpenPIC_Source {
 150         OpenPIC_Reg _Vector_Priority;                   /* Read/Write */
 151         OpenPIC_Reg _Destination;                       /* Read/Write */
 152 } OpenPIC_Source, *OpenPIC_SourcePtr;
 153
 154
 155     /*
 156      *  OpenPIC Register Map
 157      */
 158
 159 struct OpenPIC {
 160         char Pad1[0x1000];
 161         /*
 162          *  Global Registers
 163          */
 164         OpenPIC_Global Global;
 165         /*
 166          *  Interrupt Source Configuration Registers
 167          */
 168         OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
 169         /*
 170          *  Per Processor Registers
 171          */
 172         OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
 173 };
 174
 175 extern volatile struct OpenPIC *OpenPIC;
 176
 177
 178 /*
 179  *  Current Task Priority Register
 180  */
 181
 182 #define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
 183
 184 /*
 185  *  Who Am I Register
 186  */
 187
 188 #define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
 189
 190 /*
 191  *  Feature Reporting Register 0
 192  */
 193
 194 #define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
 195 #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
 196 #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
 197 #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
 198 #define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
 199
 200 /*
 201  *  Global Configuration Register 0
 202  */
 203
 204 #define OPENPIC_CONFIG_RESET                    0x80000000
 205 #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
 206 #define OPENPIC_CONFIG_BASE_MASK                0x000fffff
 207
 208 /*
 209  *  Vendor Identification Register
 210  */
 211
 212 #define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
 213 #define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
 214 #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
 215 #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
 216 #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
 217
 218 /*
 219  *  Vector/Priority Registers
 220  */
 221
 222 #define OPENPIC_MASK                            0x80000000
 223 #define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
 224 #define OPENPIC_PRIORITY_MASK                   0x000f0000
 225 #define OPENPIC_PRIORITY_SHIFT                  16
 226 #define OPENPIC_VECTOR_MASK                     0x000007ff
 227
 228
 229 /*
 230  *  Interrupt Source Registers
 231  */
 232
 233 #define OPENPIC_POLARITY_POSITIVE               0x00800000
 234 #define OPENPIC_POLARITY_NEGATIVE               0x00000000
 235 #define OPENPIC_POLARITY_MASK                   0x00800000
 236 #define OPENPIC_SENSE_LEVEL                     0x00400000
 237 #define OPENPIC_SENSE_EDGE                      0x00000000
 238 #define OPENPIC_SENSE_MASK                      0x00400000
 239
 240
 241 /*
 242  *  Timer Registers
 243  */
 244
 245 #define OPENPIC_COUNT_MASK                      0x7fffffff
 246 #define OPENPIC_TIMER_TOGGLE                    0x80000000
 247 #define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
 248
 249
 250 /*
 251  *  Aliases to make life simpler
 252  */
 253
 254 /* Per Processor Registers */
 255 #define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
 256 #define Current_Task_Priority           _Current_Task_Priority.Reg
 257 #define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
 258 #define EOI                             _EOI.Reg
 259
 260 /* Global Registers */
 261 #define Feature_Reporting0              _Feature_Reporting0.Reg
 262 #define Feature_Reporting1              _Feature_Reporting1.Reg
 263 #define Global_Configuration0           _Global_Configuration0.Reg
 264 #define Global_Configuration1           _Global_Configuration1.Reg
 265 #define Vendor_Specific(i)              _Vendor_Specific[i].Reg
 266 #define Vendor_Identification           _Vendor_Identification.Reg
 267 #define Processor_Initialization        _Processor_Initialization.Reg
 268 #define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
 269 #define Spurious_Vector                 _Spurious_Vector.Reg
 270 #define Timer_Frequency                 _Timer_Frequency.Reg
 271
 272 /* Timer Registers */
 273 #define Current_Count                   _Current_Count.Reg
 274 #define Base_Count                      _Base_Count.Reg
 275 #define Vector_Priority                 _Vector_Priority.Reg
 276 #define Destination                     _Destination.Reg
 277
 278 /* Interrupt Source Registers */
 279 #define Vector_Priority                 _Vector_Priority.Reg
 280 #define Destination                     _Destination.Reg
 281
 282
 283 #endif /* __KERNEL__ */
 284
 285 #endif /* _LINUX_OPENPIC_H */