2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/capability.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/bootmem.h>
24 #include <linux/module.h>
26 #include <linux/list.h>
28 #include <asm/processor.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/byteorder.h>
34 #include <asm/uaccess.h>
35 #include <asm/ppcdebug.h>
37 #include <asm/iommu.h>
38 #include <asm/machdep.h>
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
45 /* legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
46 devices we don't have access to. */
47 unsigned long io_page_mask;
49 EXPORT_SYMBOL(io_page_mask);
52 unsigned int pcibios_assign_all_busses(void)
54 return pci_assign_all_buses;
57 /* pci_io_base -- the base address from which io bars are offsets.
58 * This is the lowest I/O base address (so bar values are always positive),
59 * and it *must* be the start of ISA space if an ISA bus exists because
60 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
61 * page is mapped and isa_io_limit prevents access to it.
63 unsigned long isa_io_base; /* NULL if no ISA bus */
64 unsigned long pci_io_base;
66 void iSeries_pcibios_init(void);
70 struct pci_dma_ops pci_dma_ops;
71 EXPORT_SYMBOL(pci_dma_ops);
73 int global_phb_number; /* Global phb counter */
75 /* Cached ISA bridge dev. */
76 struct pci_dev *ppc64_isabridge_dev = NULL;
78 static void fixup_broken_pcnet32(struct pci_dev* dev)
80 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
81 dev->vendor = PCI_VENDOR_ID_AMD;
82 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
88 static void fixup_windbond_82c105(struct pci_dev* dev)
90 /* Assume the windbond 82c105 is the IDE controller on a
91 * p610. We should probably be more careful in case
92 * someone tries to plug in a similar adapter.
97 printk("Using INTC for W82c105 IDE controller.\n");
98 pci_read_config_dword(dev, 0x40, ®);
99 /* Enable LEGIRQ to use INTC instead of ISA interrupts */
100 pci_write_config_dword(dev, 0x40, reg | (1<<11));
102 for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
103 /* zap the 2nd function of the winbond chip */
104 if (dev->resource[i].flags & IORESOURCE_IO
105 && dev->bus->number == 0 && dev->devfn == 0x81)
106 dev->resource[i].flags &= ~IORESOURCE_IO;
109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, fixup_windbond_82c105);
112 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
113 struct resource *res)
115 unsigned long offset = 0;
116 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
121 if (res->flags & IORESOURCE_IO)
122 offset = (unsigned long)hose->io_base_virt - pci_io_base;
124 if (res->flags & IORESOURCE_MEM)
125 offset = hose->pci_mem_offset;
127 region->start = res->start - offset;
128 region->end = res->end - offset;
131 #ifdef CONFIG_HOTPLUG
132 EXPORT_SYMBOL(pcibios_resource_to_bus);
136 * We need to avoid collisions with `mirrored' VGA ports
137 * and other strange ISA hardware, so we always want the
138 * addresses to be allocated in the 0x000-0x0ff region
141 * Why? Because some silly external IO cards only decode
142 * the low 10 bits of the IO address. The 0x00-0xff region
143 * is reserved for motherboard devices that decode all 16
144 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
145 * but we want to try to avoid allocating at 0x2900-0x2bff
146 * which might have be mirrored at 0x0100-0x03ff..
148 void pcibios_align_resource(void *data, struct resource *res,
149 unsigned long size, unsigned long align)
151 struct pci_dev *dev = data;
152 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
153 unsigned long start = res->start;
154 unsigned long alignto;
156 if (res->flags & IORESOURCE_IO) {
157 unsigned long offset = (unsigned long)hose->io_base_virt -
159 /* Make sure we start at our min on all hoses */
160 if (start - offset < PCIBIOS_MIN_IO)
161 start = PCIBIOS_MIN_IO + offset;
164 * Put everything into 0x00-0xff region modulo 0x400
167 start = (start + 0x3ff) & ~0x3ff;
169 } else if (res->flags & IORESOURCE_MEM) {
170 /* Make sure we start at our min on all hoses */
171 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
172 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
174 /* Align to multiple of size of minimum base. */
175 alignto = max(0x1000UL, align);
176 start = ALIGN(start, alignto);
183 * Allocate pci_controller(phb) initialized common variables.
185 struct pci_controller * __init
186 pci_alloc_pci_controller(enum phb_types controller_type)
188 struct pci_controller *hose;
191 #ifdef CONFIG_PPC_ISERIES
192 hose = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
194 hose = (struct pci_controller *)alloc_bootmem(sizeof(struct pci_controller));
197 printk(KERN_ERR "PCI: Allocate pci_controller failed.\n");
200 memset(hose, 0, sizeof(struct pci_controller));
202 switch(controller_type) {
203 #ifdef CONFIG_PPC_ISERIES
204 case phb_type_hypervisor:
208 case phb_type_python:
211 case phb_type_speedwagon:
214 case phb_type_winnipeg:
225 if(strlen(model) < 8)
226 strcpy(hose->what,model);
228 memcpy(hose->what,model,7);
229 hose->type = controller_type;
230 hose->global_number = global_phb_number++;
232 list_add_tail(&hose->list_node, &hose_list);
237 static void __init pcibios_claim_one_bus(struct pci_bus *b)
239 struct list_head *ld;
240 struct pci_bus *child_bus;
242 for (ld = b->devices.next; ld != &b->devices; ld = ld->next) {
243 struct pci_dev *dev = pci_dev_b(ld);
246 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
247 struct resource *r = &dev->resource[i];
249 if (r->parent || !r->start || !r->flags)
251 pci_claim_resource(dev, i);
255 list_for_each_entry(child_bus, &b->children, node)
256 pcibios_claim_one_bus(child_bus);
259 #ifndef CONFIG_PPC_ISERIES
260 static void __init pcibios_claim_of_setup(void)
262 struct list_head *lb;
264 for (lb = pci_root_buses.next; lb != &pci_root_buses; lb = lb->next) {
265 struct pci_bus *b = pci_bus_b(lb);
266 pcibios_claim_one_bus(b);
271 static int __init pcibios_init(void)
273 struct pci_controller *hose, *tmp;
276 #ifdef CONFIG_PPC_ISERIES
277 iSeries_pcibios_init();
280 printk("PCI: Probing PCI hardware\n");
282 /* Scan all of the recorded PCI controllers. */
283 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
284 hose->last_busno = 0xff;
285 bus = pci_scan_bus(hose->first_busno, hose->ops,
288 hose->last_busno = bus->subordinate;
291 #ifndef CONFIG_PPC_ISERIES
293 pcibios_claim_of_setup();
295 /* FIXME: `else' will be removed when
296 pci_assign_unassigned_resources() is able to work
297 correctly with [partially] allocated PCI tree. */
298 pci_assign_unassigned_resources();
299 #endif /* !CONFIG_PPC_ISERIES */
301 /* Call machine dependent final fixup */
302 if (ppc_md.pcibios_fixup)
303 ppc_md.pcibios_fixup();
305 /* Cache the location of the ISA bridge (if we have one) */
306 ppc64_isabridge_dev = pci_find_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
307 if (ppc64_isabridge_dev != NULL)
308 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
310 printk("PCI: Probing PCI hardware done\n");
315 subsys_initcall(pcibios_init);
317 char __init *pcibios_setup(char *str)
322 int pcibios_enable_device(struct pci_dev *dev, int mask)
327 pci_read_config_word(dev, PCI_COMMAND, &cmd);
330 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
331 struct resource *res = &dev->resource[i];
333 /* Only set up the requested stuff */
334 if (!(mask & (1<<i)))
337 if (res->flags & IORESOURCE_IO)
338 cmd |= PCI_COMMAND_IO;
339 if (res->flags & IORESOURCE_MEM)
340 cmd |= PCI_COMMAND_MEMORY;
344 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
346 /* Enable the appropriate bits in the PCI command register. */
347 pci_write_config_word(dev, PCI_COMMAND, cmd);
353 * Return the domain number for this bus.
355 int pci_domain_nr(struct pci_bus *bus)
357 #ifdef CONFIG_PPC_ISERIES
360 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
362 return hose->global_number;
366 EXPORT_SYMBOL(pci_domain_nr);
368 /* Set the name of the bus as it appears in /proc/bus/pci */
369 int pci_name_bus(char *name, struct pci_bus *bus)
371 #ifndef CONFIG_PPC_ISERIES
372 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
375 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
378 sprintf(name, "%02x", bus->number);
384 * Platform support for /proc/bus/pci/X/Y mmap()s,
385 * modelled on the sparc64 implementation by Dave Miller.
390 * Adjust vm_pgoff of VMA such that it is the physical page offset
391 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
393 * Basically, the user finds the base address for his device which he wishes
394 * to mmap. They read the 32-bit value from the config space base register,
395 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
396 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
398 * Returns negative error code on failure, zero on success.
400 static __inline__ int
401 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
402 enum pci_mmap_state mmap_state)
404 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
405 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
406 unsigned long io_offset = 0;
410 return -EINVAL; /* should never happen */
412 /* If memory, add on the PCI bridge address offset */
413 if (mmap_state == pci_mmap_mem) {
414 offset += hose->pci_mem_offset;
415 res_bit = IORESOURCE_MEM;
417 io_offset = (unsigned long)hose->io_base_virt;
419 res_bit = IORESOURCE_IO;
423 * Check that the offset requested corresponds to one of the
424 * resources of the device.
426 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
427 struct resource *rp = &dev->resource[i];
428 int flags = rp->flags;
430 /* treat ROM as memory (should be already) */
431 if (i == PCI_ROM_RESOURCE)
432 flags |= IORESOURCE_MEM;
434 /* Active and same type? */
435 if ((flags & res_bit) == 0)
438 /* In the range of this resource? */
439 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
442 /* found it! construct the final physical address */
443 if (mmap_state == pci_mmap_io)
444 offset += hose->io_base_phys - io_offset;
446 vma->vm_pgoff = offset >> PAGE_SHIFT;
454 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
457 static __inline__ void
458 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
459 enum pci_mmap_state mmap_state)
461 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
465 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
468 static __inline__ void
469 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
470 enum pci_mmap_state mmap_state, int write_combine)
472 long prot = pgprot_val(vma->vm_page_prot);
474 /* XXX would be nice to have a way to ask for write-through */
475 prot |= _PAGE_NO_CACHE;
477 prot |= _PAGE_GUARDED;
478 vma->vm_page_prot = __pgprot(prot);
482 * Perform the actual remap of the pages for a PCI device mapping, as
483 * appropriate for this architecture. The region in the process to map
484 * is described by vm_start and vm_end members of VMA, the base physical
485 * address is found in vm_pgoff.
486 * The pci device structure is provided so that architectures may make mapping
487 * decisions on a per-device or per-bus basis.
489 * Returns a negative error code on failure, zero on success.
491 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
492 enum pci_mmap_state mmap_state,
497 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
501 __pci_mmap_set_flags(dev, vma, mmap_state);
502 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
504 ret = remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
505 vma->vm_end - vma->vm_start, vma->vm_page_prot);
510 #ifdef CONFIG_PPC_MULTIPLATFORM
511 static ssize_t pci_show_devspec(struct device *dev, char *buf)
513 struct pci_dev *pdev;
514 struct device_node *np;
516 pdev = to_pci_dev (dev);
517 np = pci_device_to_OF_node(pdev);
518 if (np == NULL || np->full_name == NULL)
520 return sprintf(buf, "%s", np->full_name);
522 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
523 #endif /* CONFIG_PPC_MULTIPLATFORM */
525 void pcibios_add_platform_entries(struct pci_dev *pdev)
527 #ifdef CONFIG_PPC_MULTIPLATFORM
528 device_create_file(&pdev->dev, &dev_attr_devspec);
529 #endif /* CONFIG_PPC_MULTIPLATFORM */
532 #ifdef CONFIG_PPC_MULTIPLATFORM
534 #define ISA_SPACE_MASK 0x1
535 #define ISA_SPACE_IO 0x1
537 static void pci_process_ISA_OF_ranges(struct device_node *isa_node,
538 unsigned long phb_io_base_phys,
539 void * phb_io_base_virt)
541 struct isa_range *range;
542 unsigned long pci_addr;
543 unsigned int isa_addr;
547 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
548 if (rlen < sizeof(struct isa_range)) {
549 printk(KERN_ERR "unexpected isa range size: %s\n",
554 /* From "ISA Binding to 1275"
555 * The ranges property is laid out as an array of elements,
556 * each of which comprises:
557 * cells 0 - 1: an ISA address
558 * cells 2 - 4: a PCI address
559 * (size depending on dev->n_addr_cells)
560 * cell 5: the size of the range
562 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
563 isa_addr = range->isa_addr.a_lo;
564 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
565 range->pci_addr.a_lo;
567 /* Assume these are both zero */
568 if ((pci_addr != 0) || (isa_addr != 0)) {
569 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
574 size = PAGE_ALIGN(range->size);
576 __ioremap_explicit(phb_io_base_phys,
577 (unsigned long) phb_io_base_virt,
578 size, _PAGE_NO_CACHE);
582 void __init pci_process_bridge_OF_ranges(struct pci_controller *hose,
583 struct device_node *dev, int primary)
585 unsigned int *ranges;
589 struct resource *res;
590 int np, na = prom_n_addr_cells(dev);
591 unsigned long pci_addr, cpu_phys_addr;
592 struct device_node *isa_dn;
596 /* From "PCI Binding to 1275"
597 * The ranges property is laid out as an array of elements,
598 * each of which comprises:
599 * cells 0 - 2: a PCI address
600 * cells 3 or 3+4: a CPU physical address
601 * (size depending on dev->n_addr_cells)
602 * cells 4+5 or 5+6: the size of the range
605 hose->io_base_phys = 0;
606 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
607 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
609 pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
611 cpu_phys_addr = ranges[3];
613 cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
615 size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
617 switch (ranges[0] >> 24) {
618 case 1: /* I/O space */
619 hose->io_base_phys = cpu_phys_addr;
620 hose->io_base_virt = reserve_phb_iospace(size);
621 PPCDBG(PPCDBG_PHBINIT,
622 "phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
623 hose->global_number, hose->io_base_phys,
624 (unsigned long) hose->io_base_virt);
627 pci_io_base = (unsigned long)hose->io_base_virt;
628 isa_dn = of_find_node_by_type(NULL, "isa");
630 isa_io_base = pci_io_base;
631 pci_process_ISA_OF_ranges(isa_dn,
640 res = &hose->io_resource;
641 res->flags = IORESOURCE_IO;
642 res->start = pci_addr;
643 res->start += (unsigned long)hose->io_base_virt -
646 case 2: /* memory space */
648 while (memno < 3 && hose->mem_resources[memno].flags)
652 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
654 res = &hose->mem_resources[memno];
655 res->flags = IORESOURCE_MEM;
656 res->start = cpu_phys_addr;
661 res->name = dev->full_name;
662 res->end = res->start + size - 1;
671 /***********************************************************************
672 * pci_find_hose_for_OF_device
674 * This function finds the PHB that matching device_node in the
675 * OpenFirmware by scanning all the pci_controllers.
677 ***********************************************************************/
678 struct pci_controller* pci_find_hose_for_OF_device(struct device_node *node)
681 struct pci_controller *hose, *tmp;
682 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
683 if (hose->arch_data == node)
691 * ppc64 can have multifunction devices that do not respond to function 0.
692 * In this case we must scan all functions.
694 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
696 struct device_node *busdn, *dn;
699 busdn = pci_device_to_OF_node(bus->self);
701 busdn = bus->sysdata; /* must be a phb */
704 * Check to see if there is any of the 8 functions are in the
705 * device tree. If they are then we need to scan all the
706 * functions of this slot.
708 for (dn = busdn->child; dn; dn = dn->sibling)
709 if ((dn->devfn >> 3) == (devfn >> 3))
716 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
719 /* Update device resources. */
720 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
723 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
724 if (dev->resource[i].flags & IORESOURCE_IO) {
725 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
726 unsigned long start, end, mask;
728 start = dev->resource[i].start += offset;
729 end = dev->resource[i].end += offset;
731 /* Need to allow IO access to pages that are in the
733 if (start < MAX_ISA_PORT) {
734 if (end > MAX_ISA_PORT)
737 start >>= PAGE_SHIFT;
740 /* get the range of pages for the map */
741 mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
742 io_page_mask |= mask;
745 else if (dev->resource[i].flags & IORESOURCE_MEM) {
746 dev->resource[i].start += hose->pci_mem_offset;
747 dev->resource[i].end += hose->pci_mem_offset;
751 EXPORT_SYMBOL(pcibios_fixup_device_resources);
753 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
755 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
756 struct list_head *ln;
758 /* XXX or bus->parent? */
759 struct pci_dev *dev = bus->self;
760 struct resource *res;
767 bus->resource[0] = res = &hose->io_resource;
769 BUG(); /* No I/O resource for this PHB? */
771 if (request_resource(&ioport_resource, res))
772 printk(KERN_ERR "Failed to request IO on "
773 "PCI domain %d\n", pci_domain_nr(bus));
776 for (i = 0; i < 3; ++i) {
777 res = &hose->mem_resources[i];
778 if (!res->flags && i == 0)
779 BUG(); /* No memory resource for this PHB? */
780 bus->resource[i+1] = res;
781 if (res->flags && request_resource(&iomem_resource, res))
782 printk(KERN_ERR "Failed to request MEM on "
786 } else if (pci_probe_only &&
787 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
788 /* This is a subordinate bridge */
790 pci_read_bridge_bases(bus);
791 pcibios_fixup_device_resources(dev, bus);
794 /* XXX Need to check why Alpha doesnt do this - Anton */
798 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
799 struct pci_dev *dev = pci_dev_b(ln);
800 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
801 pcibios_fixup_device_resources(dev, bus);
804 EXPORT_SYMBOL(pcibios_fixup_bus);
806 /******************************************************************
809 * Reads the Interrupt Pin to determine if interrupt is use by card.
810 * If the interrupt is used, then gets the interrupt line from the
811 * openfirmware and sets it in the pci_dev and pci_config line.
813 ******************************************************************/
814 int pci_read_irq_line(struct pci_dev *pci_dev)
817 struct device_node *node;
819 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
822 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s No Interrupt used by device.\n",
827 node = pci_device_to_OF_node(pci_dev);
829 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s Device Node not found.\n",
833 if (node->n_intrs == 0) {
834 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s No Device OF interrupts defined.\n",
838 pci_dev->irq = node->intrs[0].line;
840 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
842 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s pci_dev->irq = 0x%02X\n",
843 pci_name(pci_dev), pci_dev->irq);
846 EXPORT_SYMBOL(pci_read_irq_line);
848 #endif /* CONFIG_PPC_MULTIPLATFORM */