2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
23 #include <linux/config.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
35 #include <asm/ppcdebug.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/abs_addr.h>
48 #include <asm/tlbflush.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/abs_addr.h>
57 #define DBG(fmt...) udbg_printf(fmt)
63 * Note: pte --> Linux PTE
64 * HPTE --> PowerPC Hashed Page Table Entry
67 * htab_initialize is called with the MMU off (of course), but
68 * the kernel has been copied down to zero so it can directly
69 * reference global data. At this point it is very difficult
70 * to print debug info.
75 extern unsigned long dart_tablebase;
76 #endif /* CONFIG_U3_DART */
78 HTAB htab_data = {NULL, 0, 0, 0, 0};
80 extern unsigned long _SDR1;
85 static inline void loop_forever(void)
87 volatile unsigned long x = 1;
92 #ifdef CONFIG_PPC_MULTIPLATFORM
93 static inline void create_pte_mapping(unsigned long start, unsigned long end,
94 unsigned long mode, int large)
104 for (addr = start; addr < end; addr += step) {
105 unsigned long vpn, hash, hpteg;
106 unsigned long vsid = get_kernel_vsid(addr);
107 unsigned long va = (vsid << 28) | (addr & 0xfffffff);
111 vpn = va >> HPAGE_SHIFT;
113 vpn = va >> PAGE_SHIFT;
115 hash = hpt_hash(vpn, large);
117 hpteg = ((hash & htab_data.htab_hash_mask)*HPTES_PER_GROUP);
119 #ifdef CONFIG_PPC_PSERIES
120 if (systemcfg->platform & PLATFORM_LPAR)
121 ret = pSeries_lpar_hpte_insert(hpteg, va,
122 virt_to_abs(addr) >> PAGE_SHIFT,
125 #endif /* CONFIG_PPC_PSERIES */
126 ret = native_hpte_insert(hpteg, va,
127 virt_to_abs(addr) >> PAGE_SHIFT,
131 ppc64_terminate_msg(0x20, "create_pte_mapping");
137 void __init htab_initialize(void)
139 unsigned long table, htab_size_bytes;
140 unsigned long pteg_count;
141 unsigned long mode_rw;
142 int i, use_largepages = 0;
144 DBG(" -> htab_initialize()\n");
147 * Calculate the required size of the htab. We want the number of
148 * PTEGs to equal one half the number of real pages.
150 htab_size_bytes = 1UL << naca->pftSize;
151 pteg_count = htab_size_bytes >> 7;
153 /* For debug, make the HTAB 1/8 as big as it normally would be. */
154 ifppcdebug(PPCDBG_HTABSIZE) {
156 htab_size_bytes = pteg_count << 7;
159 htab_data.htab_num_ptegs = pteg_count;
160 htab_data.htab_hash_mask = pteg_count - 1;
162 if (systemcfg->platform & PLATFORM_LPAR) {
163 /* Using a hypervisor which owns the htab */
164 htab_data.htab = NULL;
167 /* Find storage for the HPT. Must be contiguous in
168 * the absolute address space.
170 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
172 DBG("Hash table allocated at %lx, size: %lx\n", table,
176 ppc64_terminate_msg(0x20, "hpt space");
179 htab_data.htab = abs_to_virt(table);
181 /* htab absolute addr + encoded htabsize */
182 _SDR1 = table + __ilog2(pteg_count) - 11;
184 /* Initialize the HPT with no entries */
185 memset((void *)table, 0, htab_size_bytes);
188 mode_rw = _PAGE_ACCESSED | _PAGE_COHERENT | PP_RWXX;
190 /* On U3 based machines, we need to reserve the DART area and
191 * _NOT_ map it to avoid cache paradoxes as it's remapped non
194 if (cur_cpu_spec->cpu_features & CPU_FTR_16M_PAGE)
197 /* create bolted the linear mapping in the hash table */
198 for (i=0; i < lmb.memory.cnt; i++) {
199 unsigned long base, size;
201 base = lmb.memory.region[i].physbase + KERNELBASE;
202 size = lmb.memory.region[i].size;
204 DBG("creating mapping for region: %lx : %lx\n", base, size);
206 #ifdef CONFIG_U3_DART
207 /* Do not map the DART space. Fortunately, it will be aligned
208 * in such a way that it will not cross two lmb regions and will
209 * fit within a single 16Mb page.
210 * The DART space is assumed to be a full 16Mb region even if we
211 * only use 2Mb of that space. We will use more of it later for
212 * AGP GART. We have to use a full 16Mb large page.
214 DBG("DART base: %lx\n", dart_tablebase);
216 if (dart_tablebase != 0 && dart_tablebase >= base
217 && dart_tablebase < (base + size)) {
218 if (base != dart_tablebase)
219 create_pte_mapping(base, dart_tablebase, mode_rw,
221 if ((base + size) > (dart_tablebase + 16*MB))
222 create_pte_mapping(dart_tablebase + 16*MB, base + size,
223 mode_rw, use_largepages);
226 #endif /* CONFIG_U3_DART */
227 create_pte_mapping(base, base + size, mode_rw, use_largepages);
229 DBG(" <- htab_initialize()\n");
233 #endif /* CONFIG_PPC_MULTIPLATFORM */
236 * Called by asm hashtable.S for doing lazy icache flush
238 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
242 #define PPC64_HWNOEXEC (1 << 2)
244 if (!pfn_valid(pte_pfn(pte)))
247 page = pte_page(pte);
250 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
252 __flush_dcache_icache(page_address(page));
253 set_bit(PG_arch_1, &page->flags);
255 pp |= PPC64_HWNOEXEC;
262 * 1 - normal page fault
263 * -1 - critical hash insertion error
265 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
269 struct mm_struct *mm;
276 switch (REGION_ID(ea)) {
280 if ((ea > USER_END) || (! mm))
283 vsid = get_vsid(mm->context.id, ea);
286 if (ea > IMALLOC_END)
289 vsid = get_kernel_vsid(ea);
291 case VMALLOC_REGION_ID:
292 if (ea > VMALLOC_END)
295 vsid = get_kernel_vsid(ea);
300 * Should only be hit if there is an access to MMIO space
301 * which is protected by EEH.
302 * Send the problem up to do_page_fault
304 case KERNEL_REGION_ID:
306 * Should never get here - entire 0xC0... region is bolted.
307 * Send the problem up to do_page_fault
312 * Send the problem up to do_page_fault
323 tmp = cpumask_of_cpu(smp_processor_id());
324 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
327 /* Is this a huge page ? */
328 if (unlikely(in_hugepage_area(mm->context, ea)))
329 ret = hash_huge_page(mm, access, ea, vsid, local);
331 ptep = find_linux_pte(pgdir, ea);
334 ret = __hash_page(ea, access, vsid, ptep, trap, local);
340 void flush_hash_page(unsigned long context, unsigned long ea, pte_t pte,
343 unsigned long vsid, vpn, va, hash, secondary, slot;
345 /* XXX fix for large ptes */
346 unsigned long large = 0;
348 if ((ea >= USER_START) && (ea <= USER_END))
349 vsid = get_vsid(context, ea);
351 vsid = get_kernel_vsid(ea);
353 va = (vsid << 28) | (ea & 0x0fffffff);
355 vpn = va >> HPAGE_SHIFT;
357 vpn = va >> PAGE_SHIFT;
358 hash = hpt_hash(vpn, large);
359 secondary = (pte_val(pte) & _PAGE_SECONDARY) >> 15;
362 slot = (hash & htab_data.htab_hash_mask) * HPTES_PER_GROUP;
363 slot += (pte_val(pte) & _PAGE_GROUP_IX) >> 12;
365 ppc_md.hpte_invalidate(slot, va, large, local);
368 void flush_hash_range(unsigned long context, unsigned long number, int local)
370 if (ppc_md.flush_hash_range) {
371 ppc_md.flush_hash_range(context, number, local);
374 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
376 for (i = 0; i < number; i++)
377 flush_hash_page(context, batch->addr[i], batch->pte[i],
382 static inline void make_bl(unsigned int *insn_addr, void *func)
384 unsigned long funcp = *((unsigned long *)func);
385 int offset = funcp - (unsigned long)insn_addr;
387 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
388 flush_icache_range((unsigned long)insn_addr, 4+
389 (unsigned long)insn_addr);
393 * low_hash_fault is called when we the low level hash code failed
394 * to instert a PTE due to an hypervisor error
396 void low_hash_fault(struct pt_regs *regs, unsigned long address)
398 if (user_mode(regs)) {
401 info.si_signo = SIGBUS;
403 info.si_code = BUS_ADRERR;
404 info.si_addr = (void *)address;
405 force_sig_info(SIGBUS, &info, current);
408 bad_page_fault(regs, address, SIGBUS);
411 void __init htab_finish_init(void)
413 extern unsigned int *htab_call_hpte_insert1;
414 extern unsigned int *htab_call_hpte_insert2;
415 extern unsigned int *htab_call_hpte_remove;
416 extern unsigned int *htab_call_hpte_updatepp;
418 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
419 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
420 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
421 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);