2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * Based on alpha version.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
15 #define OP_MAX_COUNTER 8
17 #define MSR_PMM (1UL << (63 - 61))
19 /* freeze counters. set to 1 on a perfmon exception */
20 #define MMCR0_FC (1UL << (31 - 0))
22 /* freeze counters while MSR mark = 1 */
23 #define MMCR0_FCM1 (1UL << (31 - 3))
25 /* performance monitor exception enable */
26 #define MMCR0_PMXE (1UL << (31 - 5))
28 /* freeze counters on enabled condition or event */
29 #define MMCR0_FCECE (1UL << (31 - 6))
31 /* performance monitor alert has occurred, set to 0 after handling exception */
32 #define MMCR0_PMAO (1UL << (31 - 24))
34 /* PMC1 count enable*/
35 #define MMCR0_PMC1INTCONTROL (1UL << (31 - 16))
37 /* PMCn count enable*/
38 #define MMCR0_PMCNINTCONTROL (1UL << (31 - 17))
40 /* state of MSR HV when SIAR set */
41 #define MMCRA_SIHV (1UL << (63 - 35))
43 /* state of MSR PR when SIAR set */
44 #define MMCRA_SIPR (1UL << (63 - 36))
47 #define MMCRA_SAMPLE_ENABLE (1UL << (63 - 63))
49 /* Per-counter configuration as set via oprofilefs. */
50 struct op_counter_config {
52 unsigned long enabled;
56 /* We dont support per counter user/kernel selection */
58 unsigned long unit_mask;
61 /* System-wide configuration as set via oprofilefs. */
62 struct op_system_config {
63 unsigned long enable_kernel;
64 unsigned long enable_user;
67 /* Per-arch configuration */
68 struct op_ppc64_model {
69 void (*reg_setup) (struct op_counter_config *,
70 struct op_system_config *,
72 void (*cpu_setup) (void *);
73 void (*start) (struct op_counter_config *);
75 void (*handle_interrupt) (struct pt_regs *,
76 struct op_counter_config *);
80 static inline unsigned int ctr_read(unsigned int i)
84 return mfspr(SPRN_PMC1);
86 return mfspr(SPRN_PMC2);
88 return mfspr(SPRN_PMC3);
90 return mfspr(SPRN_PMC4);
92 return mfspr(SPRN_PMC5);
94 return mfspr(SPRN_PMC6);
96 return mfspr(SPRN_PMC7);
98 return mfspr(SPRN_PMC8);
104 static inline void ctr_write(unsigned int i, unsigned int val)
108 mtspr(SPRN_PMC1, val);
111 mtspr(SPRN_PMC2, val);
114 mtspr(SPRN_PMC3, val);
117 mtspr(SPRN_PMC4, val);
120 mtspr(SPRN_PMC5, val);
123 mtspr(SPRN_PMC6, val);
126 mtspr(SPRN_PMC7, val);
129 mtspr(SPRN_PMC8, val);