2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * Based on alpha version.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
15 #define OP_MAX_COUNTER 8
17 #define MSR_PMM (1UL << (63 - 61))
19 /* freeze counters. set to 1 on a perfmon exception */
20 #define MMCR0_FC (1UL << (31 - 0))
22 /* freeze in supervisor state */
23 #define MMCR0_KERNEL_DISABLE (1UL << (31 - 1))
25 /* freeze in problem state */
26 #define MMCR0_PROBLEM_DISABLE (1UL << (31 - 2))
28 /* freeze counters while MSR mark = 1 */
29 #define MMCR0_FCM1 (1UL << (31 - 3))
31 /* performance monitor exception enable */
32 #define MMCR0_PMXE (1UL << (31 - 5))
34 /* freeze counters on enabled condition or event */
35 #define MMCR0_FCECE (1UL << (31 - 6))
37 /* PMC1 count enable*/
38 #define MMCR0_PMC1INTCONTROL (1UL << (31 - 16))
40 /* PMCn count enable*/
41 #define MMCR0_PMCNINTCONTROL (1UL << (31 - 17))
43 /* performance monitor alert has occurred, set to 0 after handling exception */
44 #define MMCR0_PMAO (1UL << (31 - 24))
46 /* state of MSR HV when SIAR set */
47 #define MMCRA_SIHV (1UL << (63 - 35))
49 /* state of MSR PR when SIAR set */
50 #define MMCRA_SIPR (1UL << (63 - 36))
53 #define MMCRA_SAMPLE_ENABLE (1UL << (63 - 63))
55 /* Per-counter configuration as set via oprofilefs. */
56 struct op_counter_config {
58 unsigned long enabled;
62 /* We dont support per counter user/kernel selection */
64 unsigned long unit_mask;
67 /* System-wide configuration as set via oprofilefs. */
68 struct op_system_config {
72 unsigned long enable_kernel;
73 unsigned long enable_user;
76 /* Per-arch configuration */
77 struct op_ppc64_model {
78 void (*reg_setup) (struct op_counter_config *,
79 struct op_system_config *,
81 void (*cpu_setup) (void *);
82 void (*start) (struct op_counter_config *);
84 void (*handle_interrupt) (struct pt_regs *,
85 struct op_counter_config *);
89 static inline unsigned int ctr_read(unsigned int i)
93 return mfspr(SPRN_PMC1);
95 return mfspr(SPRN_PMC2);
97 return mfspr(SPRN_PMC3);
99 return mfspr(SPRN_PMC4);
101 return mfspr(SPRN_PMC5);
103 return mfspr(SPRN_PMC6);
105 return mfspr(SPRN_PMC7);
107 return mfspr(SPRN_PMC8);
113 static inline void ctr_write(unsigned int i, unsigned int val)
117 mtspr(SPRN_PMC1, val);
120 mtspr(SPRN_PMC2, val);
123 mtspr(SPRN_PMC3, val);
126 mtspr(SPRN_PMC4, val);
129 mtspr(SPRN_PMC5, val);
132 mtspr(SPRN_PMC6, val);
135 mtspr(SPRN_PMC7, val);
138 mtspr(SPRN_PMC8, val);