2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/oprofile.h>
11 #include <linux/init.h>
12 #include <linux/smp.h>
13 #include <asm/ptrace.h>
14 #include <asm/system.h>
15 #include <asm/processor.h>
16 #include <asm/cputable.h>
17 #include <asm/systemcfg.h>
20 #define dbg(args...) printk(args)
24 static unsigned long reset_value[OP_MAX_COUNTER];
26 static int num_counters;
28 static void power4_reg_setup(struct op_counter_config *ctr,
29 struct op_system_config *sys,
34 num_counters = num_ctrs;
36 for (i = 0; i < num_counters; ++i)
37 reset_value[i] = 0x80000000UL - ctr[i].count;
39 /* XXX setup user and kernel profiling */
42 extern void ppc64_enable_pmcs(void);
44 static void power4_cpu_setup(void *unused)
46 unsigned int mmcr0 = mfspr(SPRN_MMCR0);
47 unsigned long mmcra = mfspr(SPRN_MMCRA);
51 /* set the freeze bit */
53 mtspr(SPRN_MMCR0, mmcr0);
55 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
56 mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL;
57 mtspr(SPRN_MMCR0, mmcr0);
59 mmcra |= MMCRA_SAMPLE_ENABLE;
60 mtspr(SPRN_MMCRA, mmcra);
62 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
64 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
66 dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
70 static void power4_start(struct op_counter_config *ctr)
75 /* set the PMM bit (see comment below) */
76 mtmsrd(mfmsr() | MSR_PMM);
78 for (i = 0; i < num_counters; ++i) {
80 ctr_write(i, reset_value[i]);
86 mmcr0 = mfspr(SPRN_MMCR0);
89 * We must clear the PMAO bit on some (GQ) chips. Just do it
95 * now clear the freeze bit, counting will not start until we
96 * rfid from this excetion, because only at that point will
97 * the PMM bit be cleared
100 mtspr(SPRN_MMCR0, mmcr0);
102 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
105 static void power4_stop(void)
109 /* freeze counters */
110 mmcr0 = mfspr(SPRN_MMCR0);
112 mtspr(SPRN_MMCR0, mmcr0);
114 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
119 /* Fake functions used by canonicalize_pc */
120 static void __attribute_used__ hypervisor_bucket(void)
124 static void __attribute_used__ rtas_bucket(void)
128 static void __attribute_used__ kernel_unknown_bucket(void)
132 /* XXX Not currently working */
133 static int mmcra_has_sihv = 0;
136 * On GQ and newer the MMCRA stores the HV and PR bits at the time
137 * the SIAR was sampled. We use that to work out if the SIAR was sampled in
138 * the hypervisor, our exception vectors or RTAS.
140 static unsigned long get_pc(void)
142 unsigned long pc = mfspr(SPRN_SIAR);
145 /* Cant do much about it */
149 mmcra = mfspr(SPRN_MMCRA);
151 /* Were we in the hypervisor? */
152 if ((systemcfg->platform == PLATFORM_PSERIES_LPAR) &&
153 (mmcra & MMCRA_SIHV))
154 /* function descriptor madness */
155 return *((unsigned long *)hypervisor_bucket);
157 /* We were in userspace, nothing to do */
158 if (mmcra & MMCRA_SIPR)
161 /* Were we in our exception vectors? */
163 return (unsigned long)__va(pc);
165 #ifdef CONFIG_PPC_PSERIES
166 /* Were we in RTAS? */
167 if (pc >= rtas.base && pc < (rtas.base + rtas.size))
168 /* function descriptor madness */
169 return *((unsigned long *)rtas_bucket);
172 /* Not sure where we were */
174 /* function descriptor madness */
175 return *((unsigned long *)kernel_unknown_bucket);
180 static int get_kernel(unsigned long pc)
184 if (!mmcra_has_sihv) {
185 is_kernel = (pc >= KERNELBASE);
187 unsigned long mmcra = mfspr(SPRN_MMCRA);
188 is_kernel = ((mmcra & MMCRA_SIPR) == 0);
194 static void power4_handle_interrupt(struct pt_regs *regs,
195 struct op_counter_config *ctr)
201 unsigned int cpu = smp_processor_id();
205 is_kernel = get_kernel(pc);
207 /* set the PMM bit (see comment below) */
208 mtmsrd(mfmsr() | MSR_PMM);
210 for (i = 0; i < num_counters; ++i) {
213 if (ctr[i].enabled) {
214 oprofile_add_sample(pc, is_kernel, i, cpu);
215 ctr_write(i, reset_value[i]);
222 mmcr0 = mfspr(SPRN_MMCR0);
224 /* reset the perfmon trigger */
228 * We must clear the PMAO bit on some (GQ) chips. Just do it
231 mmcr0 &= ~MMCR0_PMAO;
234 * now clear the freeze bit, counting will not start until we
235 * rfid from this exception, because only at that point will
236 * the PMM bit be cleared
239 mtspr(SPRN_MMCR0, mmcr0);
242 struct op_ppc64_model op_model_power4 = {
243 .reg_setup = power4_reg_setup,
244 .cpu_setup = power4_cpu_setup,
245 .start = power4_start,
247 .handle_interrupt = power4_handle_interrupt,