2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/oprofile.h>
11 #include <linux/init.h>
12 #include <linux/smp.h>
13 #include <asm/ptrace.h>
14 #include <asm/system.h>
15 #include <asm/processor.h>
16 #include <asm/cputable.h>
17 #include <asm/systemcfg.h>
20 #define dbg(args...) printk(args)
24 static unsigned long reset_value[OP_MAX_COUNTER];
26 static int num_counters;
27 static int oprofile_running;
28 static int mmcra_has_sihv;
30 static void power4_reg_setup(struct op_counter_config *ctr,
31 struct op_system_config *sys,
36 num_counters = num_ctrs;
39 * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
40 * However we disable it on all POWER4 until we verify it works
41 * (I was seeing some strange behaviour last time I tried).
43 * It has been verified to work on POWER5 so we enable it there.
45 if (cur_cpu_spec->cpu_features & CPU_FTR_MMCRA_SIHV)
48 for (i = 0; i < num_counters; ++i)
49 reset_value[i] = 0x80000000UL - ctr[i].count;
51 /* XXX setup user and kernel profiling */
54 extern void ppc64_enable_pmcs(void);
56 static void power4_cpu_setup(void *unused)
58 unsigned int mmcr0 = mfspr(SPRN_MMCR0);
59 unsigned long mmcra = mfspr(SPRN_MMCRA);
63 /* set the freeze bit */
65 mtspr(SPRN_MMCR0, mmcr0);
67 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
68 mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL;
69 mtspr(SPRN_MMCR0, mmcr0);
71 mmcra |= MMCRA_SAMPLE_ENABLE;
72 mtspr(SPRN_MMCRA, mmcra);
74 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
76 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
78 dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
82 static void power4_start(struct op_counter_config *ctr)
87 /* set the PMM bit (see comment below) */
88 mtmsrd(mfmsr() | MSR_PMM);
90 for (i = 0; i < num_counters; ++i) {
92 ctr_write(i, reset_value[i]);
98 mmcr0 = mfspr(SPRN_MMCR0);
101 * We must clear the PMAO bit on some (GQ) chips. Just do it
104 mmcr0 &= ~MMCR0_PMAO;
107 * now clear the freeze bit, counting will not start until we
108 * rfid from this excetion, because only at that point will
109 * the PMM bit be cleared
112 mtspr(SPRN_MMCR0, mmcr0);
114 oprofile_running = 1;
116 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
119 static void power4_stop(void)
123 /* freeze counters */
124 mmcr0 = mfspr(SPRN_MMCR0);
126 mtspr(SPRN_MMCR0, mmcr0);
128 oprofile_running = 0;
130 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
135 /* Fake functions used by canonicalize_pc */
136 static void __attribute_used__ hypervisor_bucket(void)
140 static void __attribute_used__ rtas_bucket(void)
144 static void __attribute_used__ kernel_unknown_bucket(void)
149 * On GQ and newer the MMCRA stores the HV and PR bits at the time
150 * the SIAR was sampled. We use that to work out if the SIAR was sampled in
151 * the hypervisor, our exception vectors or RTAS.
153 static unsigned long get_pc(void)
155 unsigned long pc = mfspr(SPRN_SIAR);
158 /* Cant do much about it */
162 mmcra = mfspr(SPRN_MMCRA);
164 /* Were we in the hypervisor? */
165 if ((systemcfg->platform == PLATFORM_PSERIES_LPAR) &&
166 (mmcra & MMCRA_SIHV))
167 /* function descriptor madness */
168 return *((unsigned long *)hypervisor_bucket);
170 /* We were in userspace, nothing to do */
171 if (mmcra & MMCRA_SIPR)
174 /* Were we in our exception vectors? */
176 return (unsigned long)__va(pc);
178 #ifdef CONFIG_PPC_PSERIES
179 /* Were we in RTAS? */
180 if (pc >= rtas.base && pc < (rtas.base + rtas.size))
181 /* function descriptor madness */
182 return *((unsigned long *)rtas_bucket);
185 /* Not sure where we were */
187 /* function descriptor madness */
188 return *((unsigned long *)kernel_unknown_bucket);
193 static int get_kernel(unsigned long pc)
197 if (!mmcra_has_sihv) {
198 is_kernel = (pc >= KERNELBASE);
200 unsigned long mmcra = mfspr(SPRN_MMCRA);
201 is_kernel = ((mmcra & MMCRA_SIPR) == 0);
207 static void power4_handle_interrupt(struct pt_regs *regs,
208 struct op_counter_config *ctr)
214 unsigned int cpu = smp_processor_id();
218 is_kernel = get_kernel(pc);
220 /* set the PMM bit (see comment below) */
221 mtmsrd(mfmsr() | MSR_PMM);
223 for (i = 0; i < num_counters; ++i) {
226 if (oprofile_running && ctr[i].enabled) {
227 oprofile_add_sample(pc, is_kernel, i, cpu);
228 ctr_write(i, reset_value[i]);
235 mmcr0 = mfspr(SPRN_MMCR0);
237 /* reset the perfmon trigger */
241 * We must clear the PMAO bit on some (GQ) chips. Just do it
244 mmcr0 &= ~MMCR0_PMAO;
247 * now clear the freeze bit, counting will not start until we
248 * rfid from this exception, because only at that point will
249 * the PMM bit be cleared
252 mtspr(SPRN_MMCR0, mmcr0);
255 struct op_ppc64_model op_model_power4 = {
256 .reg_setup = power4_reg_setup,
257 .cpu_setup = power4_cpu_setup,
258 .start = power4_start,
260 .handle_interrupt = power4_handle_interrupt,