2 * arch/s390/kernel/entry.S
3 * S390 low-level entry points.
6 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Hartmut Penner (hp@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/config.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/offsets.h>
21 #include <asm/unistd.h>
24 * Stack layout for the system_call stack entry.
25 * The first few entries are identical to the user_regs_struct.
27 SP_PTREGS = STACK_FRAME_OVERHEAD
28 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
29 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
30 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
31 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 4
32 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
33 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 12
34 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
35 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 20
36 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
37 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 28
38 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
39 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 36
40 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
41 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 44
42 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
43 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 52
44 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
45 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 60
46 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
47 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
48 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
49 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
51 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
52 _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
53 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
55 #define BASED(name) name-system_call(%r13)
58 * Register usage in interrupt handlers:
59 * R9 - pointer to current task structure
60 * R13 - pointer to literal pool
61 * R14 - return register for function calls
62 * R15 - kernel stack pointer
65 .macro SAVE_ALL_BASE psworg,savearea,sync
66 stm %r12,%r15,\savearea
67 l %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
70 .macro CLEANUP_SAVE_ALL_BASE psworg,savearea,sync
74 mvc \savearea(16),SP_R12(%r15)
75 0: st %r13,SP_R13(%r15)
78 .macro SAVE_ALL psworg,savearea,sync
80 tm \psworg+1,0x01 # test problem state bit
81 bz BASED(1f) # skip stack setup save
82 l %r15,__LC_KERNEL_STACK # problem state -> load ksp
84 tm \psworg+1,0x01 # test problem state bit
85 bnz BASED(0f) # from user -> load async stack
86 l %r14,__LC_ASYNC_STACK # are we already on the async stack ?
90 0: l %r15,__LC_ASYNC_STACK
92 1: s %r15,BASED(.Lc_spsize) # make room for registers & psw
93 l %r14,BASED(.L\psworg)
95 icm %r14,12,__LC_SVC_ILC
96 stm %r0,%r11,SP_R0(%r15) # store gprs 0-12 to kernel stack
97 st %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
98 mvc SP_R12(16,%r15),\savearea # move R13-R15 to stack
99 mvc SP_PSW(8,%r15),\psworg # move user PSW to stack
101 st %r12,0(%r15) # clear back chain
104 .macro CLEANUP_SAVE_ALL psworg,savearea,sync
109 l %r1,__LC_KERNEL_STACK
113 l %r0,__LC_ASYNC_STACK
117 0: l %r1,__LC_ASYNC_STACK
119 1: s %r1,BASED(.Lc_spsize)
121 l %r0,BASED(.L\psworg)
122 xc SP_R12(4,%r15),SP_R12(%r15)
123 icm %r0,12,__LC_SVC_ILC
125 mvc SP_R0(48,%r1),SP_R0(%r15)
126 mvc SP_ORIG_R2(4,%r1),SP_R2(%r15)
127 mvc SP_R12(16,%r1),\savearea
128 mvc SP_PSW(8,%r1),\psworg
133 .macro RESTORE_ALL # system exit macro
134 mvc __LC_RETURN_PSW(8),SP_PSW(%r15) # move user PSW to lowcore
135 ni __LC_RETURN_PSW+1,0xfd # clear wait state bit
136 lm %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
137 lpsw __LC_RETURN_PSW # back to caller
140 .macro CLEANUP_RESTORE_ALL
144 mvc SP_PSW(8,%r15),__LC_RETURN_PSW
146 0: l %r1,SP_R15(%r15)
147 mvc SP_PSW(8,%r15),SP_PSW(%r1)
148 mvc SP_R0(64,%r15),SP_R0(%r1)
152 .macro GET_THREAD_INFO
153 l %r9,__LC_THREAD_INFO
156 .macro CHECK_CRITICAL
157 tm SP_PSW+1(%r15),0x01 # test problem state bit
158 bnz BASED(0f) # from user -> not critical
159 clc SP_PSW+4(4,%r15),BASED(.Lcritical_end)
161 clc SP_PSW+4(4,%r15),BASED(.Lcritical_start)
163 l %r1,BASED(.Lcleanup_critical)
169 * Scheduler resume function, called by switch_to
170 * gpr2 = (task_struct *) prev
171 * gpr3 = (task_struct *) next
179 tm __THREAD_per(%r3),0xe8 # new process is using per ?
180 bz __switch_to_noper-__switch_to_base(%r1) # if not we're fine
181 stctl %c9,%c11,24(%r15) # We are using per stuff
182 clc __THREAD_per(12,%r3),24(%r15)
183 be __switch_to_noper-__switch_to_base(%r1) # we got away w/o bashing TLB's
184 lctl %c9,%c11,__THREAD_per(%r3) # Nope we didn't
186 stm %r6,%r15,24(%r15) # store __switch_to registers of prev task
187 st %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
188 l %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
189 lm %r6,%r15,24(%r15) # load __switch_to registers of next task
190 st %r3,__LC_CURRENT # __LC_CURRENT = current task struct
191 l %r3,__THREAD_info(%r3) # load thread_info from task struct
192 st %r3,__LC_THREAD_INFO
194 st %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
198 * do_softirq calling function. We want to run the softirq functions on the
199 * asynchronous interrupt stack.
201 .global do_call_softirq
204 stm %r12,%r15,28(%r15)
208 l %r0,__LC_ASYNC_STACK
211 be 0f-do_call_base(%r13)
212 l %r15,__LC_ASYNC_STACK
213 0: sl %r15,.Lc_overhead-do_call_base(%r13)
214 st %r12,0(%r15) # store backchain
215 l %r1,.Ldo_softirq-do_call_base(%r13)
217 lm %r12,%r15,28(%r12)
223 * SVC interrupt handler routine. System calls are synchronous events and
224 * are executed with interrupts enabled.
229 SAVE_ALL_BASE __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
230 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
231 lh %r7,0x8a # get svc number from lowcore
233 GET_THREAD_INFO # load pointer to task_struct to R9
235 sla %r7,2 # *4 and test for svc 0
236 bnz BASED(sysc_nr_ok) # svc number > 0
237 # svc 0: system call number in %r1
238 cl %r1,BASED(.Lnr_syscalls)
239 bnl BASED(sysc_nr_ok)
240 lr %r7,%r1 # copy svc number to %r7
243 mvc SP_ARGS(4,%r15),SP_R7(%r15)
245 tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
246 l %r8,sys_call_table-system_call(%r7,%r13) # get system call addr.
247 bnz BASED(sysc_tracesys)
248 basr %r14,%r8 # call sys_xxxx
249 st %r2,SP_R2(%r15) # store return value (change R2 on stack)
250 # ATTENTION: check sys_execve_glue before
251 # changing anything here !!
254 tm SP_PSW+1(%r15),0x01 # returning to user ?
255 bno BASED(sysc_leave)
256 tm __TI_flags+3(%r9),_TIF_WORK_SVC
257 bnz BASED(sysc_work) # there is work to do (signals etc.)
262 # recheck if there is more work to do
265 GET_THREAD_INFO # load pointer to task_struct to R9
266 tm __TI_flags+3(%r9),_TIF_WORK_SVC
267 bz BASED(sysc_leave) # there is no work to do
269 # One of the work bits is on. Find out which one.
272 tm __TI_flags+3(%r9),_TIF_NEED_RESCHED
273 bo BASED(sysc_reschedule)
274 tm __TI_flags+3(%r9),_TIF_SIGPENDING
275 bo BASED(sysc_sigpending)
276 tm __TI_flags+3(%r9),_TIF_RESTART_SVC
277 bo BASED(sysc_restart)
278 tm __TI_flags+3(%r9),_TIF_SINGLE_STEP
279 bo BASED(sysc_singlestep)
283 # _TIF_NEED_RESCHED is set, call schedule
286 l %r1,BASED(.Lschedule)
287 la %r14,BASED(sysc_work_loop)
288 br %r1 # call scheduler
291 # _TIF_SIGPENDING is set, call do_signal
294 la %r2,SP_PTREGS(%r15) # load pt_regs
295 sr %r3,%r3 # clear *oldset
296 l %r1,BASED(.Ldo_signal)
297 basr %r14,%r1 # call do_signal
298 tm __TI_flags+3(%r9),_TIF_RESTART_SVC
299 bo BASED(sysc_restart)
300 b BASED(sysc_leave) # out of here, do NOT recheck
303 # _TIF_RESTART_SVC is set, set up registers and restart svc
306 ni __TI_flags+3(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
307 l %r7,SP_R2(%r15) # load new svc number
309 mvc SP_R2(4,%r15),SP_ORIG_R2(%r15) # restore first argument
310 lm %r2,%r6,SP_R2(%r15) # load svc arguments
311 b BASED(sysc_do_restart) # restart svc
314 # _TIF_SINGLE_STEP is set, call do_debugger_trap
317 ni __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
318 mvi SP_TRAP+1(%r15),0x28 # set trap indication to pgm check
319 la %r2,SP_PTREGS(%r15) # address of register-save area
320 l %r1,BASED(.Lhandle_per) # load adr. of per handler
321 la %r14,BASED(sysc_return) # load adr. of system return
322 br %r1 # branch to do_debugger_trap
327 # call trace before and after sys_call
331 la %r2,SP_PTREGS(%r15) # load pt_regs
336 clc SP_R2(4,%r15),BASED(.Lnr_syscalls)
337 bnl BASED(sysc_tracenogo)
338 l %r7,SP_R2(%r15) # strace might have changed the
339 sll %r7,2 # system call
340 l %r8,sys_call_table-system_call(%r7,%r13)
342 lm %r3,%r6,SP_R3(%r15)
343 l %r2,SP_ORIG_R2(%r15)
344 basr %r14,%r8 # call sys_xxx
345 st %r2,SP_R2(%r15) # store return value
347 tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
348 bz BASED(sysc_return)
350 la %r2,SP_PTREGS(%r15) # load pt_regs
352 la %r14,BASED(sysc_return)
356 # a new process exits the kernel with ret_from_fork
360 l %r13,__LC_SVC_NEW_PSW+4
361 GET_THREAD_INFO # load pointer to task_struct to R9
362 l %r1,BASED(.Lschedtail)
364 stosm 24(%r15),0x03 # reenable interrupts
368 # clone, fork, vfork, exec and sigreturn need glue,
369 # because they all expect pt_regs as parameter,
370 # but are called with different parameter.
371 # return-address is set up above
374 la %r2,SP_PTREGS(%r15) # load pt_regs
376 br %r1 # branch to sys_clone
379 la %r2,SP_PTREGS(%r15) # load pt_regs
381 br %r1 # branch to sys_fork
384 la %r2,SP_PTREGS(%r15) # load pt_regs
386 br %r1 # branch to sys_vfork
389 la %r2,SP_PTREGS(%r15) # load pt_regs
390 l %r1,BASED(.Lexecve)
391 lr %r12,%r14 # save return address
392 basr %r14,%r1 # call sys_execve
393 ltr %r2,%r2 # check if execve failed
394 bnz 0(%r12) # it did fail -> store result in gpr2
395 b 4(%r12) # SKIP ST 2,SP_R2(15) after BASR 14,8
396 # in system_call/sysc_tracesys
399 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
400 l %r1,BASED(.Lsigreturn)
401 br %r1 # branch to sys_sigreturn
403 sys_rt_sigreturn_glue:
404 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
405 l %r1,BASED(.Lrt_sigreturn)
406 br %r1 # branch to sys_sigreturn
409 # sigsuspend and rt_sigsuspend need pt_regs as an additional
410 # parameter and they have to skip the store of %r2 into the
411 # user register %r2 because the return value was set in
412 # sigsuspend and rt_sigsuspend already and must not be overwritten!
416 lr %r5,%r4 # move mask back
417 lr %r4,%r3 # move history1 parameter
418 lr %r3,%r2 # move history0 parameter
419 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
420 l %r1,BASED(.Lsigsuspend)
421 la %r14,4(%r14) # skip store of return value
422 br %r1 # branch to sys_sigsuspend
424 sys_rt_sigsuspend_glue:
425 lr %r4,%r3 # move sigsetsize parameter
426 lr %r3,%r2 # move unewset parameter
427 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
428 l %r1,BASED(.Lrt_sigsuspend)
429 la %r14,4(%r14) # skip store of return value
430 br %r1 # branch to sys_rt_sigsuspend
432 sys_sigaltstack_glue:
433 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
434 l %r1,BASED(.Lsigaltstack)
435 br %r1 # branch to sys_sigreturn
439 * Program check handler routine
442 .globl pgm_check_handler
445 * First we need to check for a special case:
446 * Single stepping an instruction that disables the PER event mask will
447 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
448 * For a single stepped SVC the program check handler gets control after
449 * the SVC new PSW has been loaded. But we want to execute the SVC first and
450 * then handle the PER event. Therefore we update the SVC old PSW to point
451 * to the pgm_check_handler and branch to the SVC handler after we checked
452 * if we have to load the kernel stack register.
453 * For every other possible cause for PER event without the PER mask set
454 * we just ignore the PER event (FIXME: is there anything we have to do
457 SAVE_ALL_BASE __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
458 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
459 bnz BASED(pgm_per) # got per exception -> special case
460 SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
461 l %r3,__LC_PGM_ILC # load program interruption code
463 l %r7,BASED(.Ljump_table)
467 l %r7,0(%r8,%r7) # load address of handler routine
468 la %r2,SP_PTREGS(%r15) # address of register-save area
469 la %r14,BASED(sysc_return)
470 br %r7 # branch to interrupt-handler
473 # handle per exception
476 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
477 bnz BASED(pgm_per_std) # ok, normal per event from user space
478 # ok its one of the special cases, now we need to find out which one
479 clc __LC_PGM_OLD_PSW(8),__LC_SVC_NEW_PSW
481 # no interesting special case, ignore PER event
482 lm %r13,%r15,__LC_SAVE_AREA
486 # Normal per exception
489 SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
492 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
493 mvc __THREAD_per+__PER_address(4,%r1),__LC_PER_ADDRESS
494 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
496 l %r3,__LC_PGM_ILC # load program interruption code
497 nr %r4,%r3 # clear per-event-bit and ilc
498 be BASED(pgm_per_only) # only per or per+check ?
499 l %r1,BASED(.Ljump_table)
501 l %r1,0(%r4,%r1) # load address of handler routine
502 la %r2,SP_PTREGS(%r15) # address of register-save area
503 basr %r14,%r1 # branch to interrupt-handler
505 la %r2,SP_PTREGS(15) # address of register-save area
506 l %r1,BASED(.Lhandle_per) # load adr. of per handler
507 la %r14,BASED(sysc_return) # load adr. of system return
508 br %r1 # branch to do_debugger_trap
511 # it was a single stepped SVC that is causing all the trouble
514 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
515 lh %r7,0x8a # get svc number from lowcore
516 GET_THREAD_INFO # load pointer to task_struct to R9
518 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
519 mvc __THREAD_per+__PER_address(4,%r1),__LC_PER_ADDRESS
520 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
521 oi __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
522 stosm 24(%r15),0x03 # reenable interrupts
526 * IO interrupt handler routine
529 .globl io_int_handler
531 SAVE_ALL_BASE __LC_IO_OLD_PSW,__LC_SAVE_AREA+16,0
532 SAVE_ALL __LC_IO_OLD_PSW,__LC_SAVE_AREA+16,0
535 GET_THREAD_INFO # load pointer to task_struct to R9
536 l %r1,BASED(.Ldo_IRQ) # load address of do_IRQ
537 la %r2,SP_PTREGS(%r15) # address of register-save area
538 basr %r14,%r1 # branch to standard irq handler
541 tm SP_PSW+1(%r15),0x01 # returning to user ?
542 #ifdef CONFIG_PREEMPT
543 bno BASED(io_preempt) # no -> check for preemptive scheduling
545 bno BASED(io_leave) # no-> skip resched & signal
547 tm __TI_flags+3(%r9),_TIF_WORK_INT
548 bnz BASED(io_work) # there is work to do (signals etc.)
552 #ifdef CONFIG_PREEMPT
554 icm %r0,15,__TI_precount(%r9)
557 s %r1,BASED(.Lc_spsize)
558 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
559 xc 0(4,%r1),0(%r1) # clear back chain
562 tm __TI_flags+3(%r9),_TIF_NEED_RESCHED
564 mvc __TI_precount(4,%r9),BASED(.Lc_pactive)
565 stosm 24(%r15),0x03 # reenable interrupts
566 l %r1,BASED(.Lschedule)
567 basr %r14,%r1 # call schedule
568 stnsm 24(%r15),0xfc # disable I/O and ext. interrupts
569 GET_THREAD_INFO # load pointer to task_struct to R9
570 xc __TI_precount(4,%r9),__TI_precount(%r9)
571 b BASED(io_resume_loop)
575 # switch to kernel stack, then check the TIF bits
578 l %r1,__LC_KERNEL_STACK
579 s %r1,BASED(.Lc_spsize)
580 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
581 xc 0(4,%r1),0(%r1) # clear back chain
584 # One of the work bits is on. Find out which one.
585 # Checked are: _TIF_SIGPENDING and _TIF_NEED_RESCHED
588 tm __TI_flags+3(%r9),_TIF_NEED_RESCHED
589 bo BASED(io_reschedule)
590 tm __TI_flags+3(%r9),_TIF_SIGPENDING
591 bo BASED(io_sigpending)
595 # _TIF_NEED_RESCHED is set, call schedule
598 l %r1,BASED(.Lschedule)
599 stosm 24(%r15),0x03 # reenable interrupts
600 basr %r14,%r1 # call scheduler
601 stnsm 24(%r15),0xfc # disable I/O and ext. interrupts
602 GET_THREAD_INFO # load pointer to task_struct to R9
603 tm __TI_flags+3(%r9),_TIF_WORK_INT
604 bz BASED(io_leave) # there is no work to do
605 b BASED(io_work_loop)
608 # _TIF_SIGPENDING is set, call do_signal
611 stosm 24(%r15),0x03 # reenable interrupts
612 la %r2,SP_PTREGS(%r15) # load pt_regs
613 sr %r3,%r3 # clear *oldset
614 l %r1,BASED(.Ldo_signal)
615 basr %r14,%r1 # call do_signal
616 stnsm 24(%r15),0xfc # disable I/O and ext. interrupts
617 b BASED(io_leave) # out of here, do NOT recheck
620 * External interrupt handler routine
623 .globl ext_int_handler
625 SAVE_ALL_BASE __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16,0
626 SAVE_ALL __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16,0
629 GET_THREAD_INFO # load pointer to task_struct to R9
630 la %r2,SP_PTREGS(%r15) # address of register-save area
631 lh %r3,__LC_EXT_INT_CODE # get interruption code
632 l %r1,BASED(.Ldo_extint)
637 * Machine check handler routines
640 .globl mcck_int_handler
642 SAVE_ALL_BASE __LC_MCK_OLD_PSW,__LC_SAVE_AREA+32,0
643 SAVE_ALL __LC_MCK_OLD_PSW,__LC_SAVE_AREA+32,0
644 l %r1,BASED(.Ls390_mcck)
645 basr %r14,%r1 # call machine check handler
651 * Restart interruption handler, kick starter for additional CPUs
653 .globl restart_int_handler
655 l %r15,__LC_SAVE_AREA+60 # load ksp
656 lctl %c0,%c15,__LC_CREGS_SAVE_AREA # get new ctl regs
657 lam %a0,%a15,__LC_AREGS_SAVE_AREA
658 stosm 0(%r15),0x04 # now we can turn dat on
659 lm %r6,%r15,24(%r15) # load registers from clone
661 l %r14,restart_addr-.(%r14)
662 br %r14 # branch to start_secondary
664 .long start_secondary
667 * If we do not run with SMP enabled, let the new CPU crash ...
669 .globl restart_int_handler
673 lpsw restart_crash-restart_base(%r1)
676 .long 0x000a0000,0x00000000
681 .long system_call, sysc_enter, cleanup_sysc_enter
682 .long sysc_return, sysc_leave, cleanup_sysc_return
683 .long sysc_leave, sysc_work_loop, cleanup_sysc_leave
684 .long sysc_work_loop, sysc_reschedule, cleanup_sysc_return
685 cleanup_table_entries=(.-cleanup_table) / 12
688 lhi %r0,cleanup_table_entries
689 la %r1,BASED(cleanup_table)
694 bl BASED(cleanup_cont)
696 bl BASED(cleanup_found)
699 bct %r0,BASED(cleanup_loop)
706 CLEANUP_SAVE_ALL_BASE __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
707 CLEANUP_SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
710 la %r1,BASED(sysc_enter)
712 st %r1,SP_PSW+4(%r15)
716 la %r1,BASED(sysc_return)
718 st %r1,SP_PSW+4(%r15)
729 .Lc_spsize: .long SP_SIZE
730 .Lc_overhead: .long STACK_FRAME_OVERHEAD
731 .Lc_pactive: .long PREEMPT_ACTIVE
732 .Lnr_syscalls: .long NR_syscalls
738 .Lamode: .long 0x80000000
743 .Ls390_mcck: .long s390_do_machine_check
744 .Ldo_IRQ: .long do_IRQ
745 .Ldo_extint: .long do_extint
746 .Ldo_signal: .long do_signal
747 .Ldo_softirq: .long do_softirq
748 .Lhandle_per: .long do_debugger_trap
749 .Ljump_table: .long pgm_check_table
750 .Lschedule: .long schedule
751 .Lclone: .long sys_clone
752 .Lexecve: .long sys_execve
753 .Lfork: .long sys_fork
754 .Lrt_sigreturn:.long sys_rt_sigreturn
756 .long sys_rt_sigsuspend
757 .Lsigreturn: .long sys_sigreturn
758 .Lsigsuspend: .long sys_sigsuspend
759 .Lsigaltstack: .long sys_sigaltstack
760 .Ltrace: .long syscall_trace
761 .Lvfork: .long sys_vfork
762 .Lschedtail: .long schedule_tail
765 .long __critical_start + 0x80000000
767 .long __critical_end + 0x80000000
769 .long cleanup_critical
771 #define SYSCALL(esa,esame,emu) .long esa
772 .globl sys_call_table
774 #include "syscalls.S"