2 * arch/s390/kernel/entry.S
3 * S390 low-level entry points.
6 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Hartmut Penner (hp@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/config.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/offsets.h>
21 #include <asm/unistd.h>
24 * Stack layout for the system_call stack entry.
25 * The first few entries are identical to the user_regs_struct.
27 SP_PTREGS = STACK_FRAME_OVERHEAD
28 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
29 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
30 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
31 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
32 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
33 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
34 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
35 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
36 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
37 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
38 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
39 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
40 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
41 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
42 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
43 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
44 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
45 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
46 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
47 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
48 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
49 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
51 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
52 _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
53 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
55 #define BASED(name) name-system_call(%r13)
58 * Register usage in interrupt handlers:
59 * R9 - pointer to current task structure
60 * R13 - pointer to literal pool
61 * R14 - return register for function calls
62 * R15 - kernel stack pointer
65 .macro SAVE_ALL_BASE savearea
66 stmg %r12,%r15,\savearea
70 .macro SAVE_ALL psworg,savearea,sync
73 tm \psworg+1,0x01 # test problem state bit
74 jz 2f # skip stack setup save
75 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
77 tm \psworg+1,0x01 # test problem state bit
78 jnz 1f # from user -> load kernel stack
79 clc \psworg+8(8),BASED(.Lcritical_end)
81 clc \psworg+8(8),BASED(.Lcritical_start)
83 brasl %r14,cleanup_critical
84 tm 0(%r12),0x01 # retest problem state after cleanup
86 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
90 1: lg %r15,__LC_ASYNC_STACK # load async stack
92 2: aghi %r15,-SP_SIZE # make room for registers & psw
93 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
95 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
96 icm %r12,12,__LC_SVC_ILC
97 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
99 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
104 .macro RESTORE_ALL sync
105 mvc __LC_RETURN_PSW(16),SP_PSW(%r15) # move user PSW to lowcore
107 ni __LC_RETURN_PSW+1,0xfd # clear wait state bit
109 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
110 lpswe __LC_RETURN_PSW # back to caller
114 * Scheduler resume function, called by switch_to
115 * gpr2 = (task_struct *) prev
116 * gpr3 = (task_struct *) next
122 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
123 jz __switch_to_noper # if not we're fine
124 stctg %c9,%c11,48(%r15) # We are using per stuff
125 clc __THREAD_per(24,%r3),48(%r15)
126 je __switch_to_noper # we got away without bashing TLB's
127 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
129 stmg %r6,%r15,48(%r15) # store __switch_to registers of prev task
130 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
131 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
132 lmg %r6,%r15,48(%r15) # load __switch_to registers of next task
133 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
134 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
135 stg %r3,__LC_THREAD_INFO
137 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
141 * do_softirq calling function. We want to run the softirq functions on the
142 * asynchronous interrupt stack.
144 .global do_call_softirq
147 stmg %r12,%r15,56(%r15)
149 lg %r0,__LC_ASYNC_STACK
153 lg %r15,__LC_ASYNC_STACK
154 0: aghi %r15,-STACK_FRAME_OVERHEAD
155 stg %r12,0(%r15) # store back chain
156 brasl %r14,do_softirq
157 lmg %r12,%r15,56(%r12)
163 * SVC interrupt handler routine. System calls are synchronous events and
164 * are executed with interrupts enabled.
169 SAVE_ALL_BASE __LC_SAVE_AREA
170 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
171 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
173 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
174 slag %r7,%r7,2 # *4 and test for svc 0
176 # svc 0: system call number in %r1
177 cl %r1,BASED(.Lnr_syscalls)
179 lgfr %r7,%r1 # clear high word in r1
180 slag %r7,%r7,2 # svc 0: system call number in %r1
182 mvc SP_ARGS(8,%r15),SP_R7(%r15)
184 larl %r10,sys_call_table
185 #ifdef CONFIG_S390_SUPPORT
186 tm SP_PSW+3(%r15),0x01 # are we running in 31 bit mode ?
188 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
191 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
192 lgf %r8,0(%r7,%r10) # load address of system call routine
194 basr %r14,%r8 # call sys_xxxx
195 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
196 # ATTENTION: check sys_execve_glue before
197 # changing anything here !!
200 tm SP_PSW+1(%r15),0x01 # returning to user ?
202 tm __TI_flags+7(%r9),_TIF_WORK_SVC
203 jnz sysc_work # there is work to do (signals etc.)
208 # recheck if there is more work to do
211 tm __TI_flags+7(%r9),_TIF_WORK_SVC
212 jz sysc_leave # there is no work to do
214 # One of the work bits is on. Find out which one.
217 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
219 tm __TI_flags+7(%r9),_TIF_SIGPENDING
221 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
223 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
228 # _TIF_NEED_RESCHED is set, call schedule
231 larl %r14,sysc_work_loop
232 jg schedule # return point is sysc_return
235 # _TIF_SIGPENDING is set, call do_signal
238 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
239 la %r2,SP_PTREGS(%r15) # load pt_regs
240 sgr %r3,%r3 # clear *oldset
241 brasl %r14,do_signal # call do_signal
242 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
244 j sysc_leave # out of here, do NOT recheck
247 # _TIF_RESTART_SVC is set, set up registers and restart svc
250 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
251 lg %r7,SP_R2(%r15) # load new svc number
253 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
254 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
255 j sysc_do_restart # restart svc
258 # _TIF_SINGLE_STEP is set, call do_single_step
261 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
262 lhi %r0,__LC_PGM_OLD_PSW
263 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
264 la %r2,SP_PTREGS(%r15) # address of register-save area
265 larl %r14,sysc_return # load adr. of system return
266 jg do_single_step # branch to do_sigtrap
272 # call syscall_trace before and after system call
273 # special linkage: %r12 contains the return address for trace_svc
276 la %r2,SP_PTREGS(%r15) # load pt_regs
280 brasl %r14,syscall_trace
284 lg %r7,SP_R2(%r15) # strace might have changed the
285 sll %r7,2 # system call
288 lmg %r3,%r6,SP_R3(%r15)
289 lg %r2,SP_ORIG_R2(%r15)
290 basr %r14,%r8 # call sys_xxx
291 stg %r2,SP_R2(%r15) # store return value
293 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
295 la %r2,SP_PTREGS(%r15) # load pt_regs
297 larl %r14,sysc_return # return point is sysc_return
301 # a new process exits the kernel with ret_from_fork
305 lg %r13,__LC_SVC_NEW_PSW+8
306 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
307 brasl %r14,schedule_tail
308 stosm 24(%r15),0x03 # reenable interrupts
312 # clone, fork, vfork, exec and sigreturn need glue,
313 # because they all expect pt_regs as parameter,
314 # but are called with different parameter.
315 # return-address is set up above
318 la %r2,SP_PTREGS(%r15) # load pt_regs
319 jg sys_clone # branch to sys_clone
321 #ifdef CONFIG_S390_SUPPORT
323 la %r2,SP_PTREGS(%r15) # load pt_regs
324 jg sys32_clone # branch to sys32_clone
328 la %r2,SP_PTREGS(%r15) # load pt_regs
329 jg sys_fork # branch to sys_fork
332 la %r2,SP_PTREGS(%r15) # load pt_regs
333 jg sys_vfork # branch to sys_vfork
336 la %r2,SP_PTREGS(%r15) # load pt_regs
337 lgr %r12,%r14 # save return address
338 brasl %r14,sys_execve # call sys_execve
339 ltgr %r2,%r2 # check if execve failed
340 bnz 0(%r12) # it did fail -> store result in gpr2
341 b 6(%r12) # SKIP STG 2,SP_R2(15) in
342 # system_call/sysc_tracesys
343 #ifdef CONFIG_S390_SUPPORT
345 la %r2,SP_PTREGS(%r15) # load pt_regs
346 lgr %r12,%r14 # save return address
347 brasl %r14,sys32_execve # call sys32_execve
348 ltgr %r2,%r2 # check if execve failed
349 bnz 0(%r12) # it did fail -> store result in gpr2
350 b 6(%r12) # SKIP STG 2,SP_R2(15) in
351 # system_call/sysc_tracesys
355 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
356 jg sys_sigreturn # branch to sys_sigreturn
358 #ifdef CONFIG_S390_SUPPORT
359 sys32_sigreturn_glue:
360 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
361 jg sys32_sigreturn # branch to sys32_sigreturn
364 sys_rt_sigreturn_glue:
365 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
366 jg sys_rt_sigreturn # branch to sys_sigreturn
368 #ifdef CONFIG_S390_SUPPORT
369 sys32_rt_sigreturn_glue:
370 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
371 jg sys32_rt_sigreturn # branch to sys32_sigreturn
375 # sigsuspend and rt_sigsuspend need pt_regs as an additional
376 # parameter and they have to skip the store of %r2 into the
377 # user register %r2 because the return value was set in
378 # sigsuspend and rt_sigsuspend already and must not be overwritten!
382 lgr %r5,%r4 # move mask back
383 lgr %r4,%r3 # move history1 parameter
384 lgr %r3,%r2 # move history0 parameter
385 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
386 la %r14,6(%r14) # skip store of return value
387 jg sys_sigsuspend # branch to sys_sigsuspend
389 #ifdef CONFIG_S390_SUPPORT
390 sys32_sigsuspend_glue:
391 llgfr %r4,%r4 # unsigned long
392 lgr %r5,%r4 # move mask back
394 lgr %r4,%r3 # move history1 parameter
396 lgr %r3,%r2 # move history0 parameter
397 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
398 la %r14,6(%r14) # skip store of return value
399 jg sys32_sigsuspend # branch to sys32_sigsuspend
402 sys_rt_sigsuspend_glue:
403 lgr %r4,%r3 # move sigsetsize parameter
404 lgr %r3,%r2 # move unewset parameter
405 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
406 la %r14,6(%r14) # skip store of return value
407 jg sys_rt_sigsuspend # branch to sys_rt_sigsuspend
409 #ifdef CONFIG_S390_SUPPORT
410 sys32_rt_sigsuspend_glue:
411 llgfr %r3,%r3 # size_t
412 lgr %r4,%r3 # move sigsetsize parameter
413 llgtr %r2,%r2 # sigset_emu31_t *
414 lgr %r3,%r2 # move unewset parameter
415 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
416 la %r14,6(%r14) # skip store of return value
417 jg sys32_rt_sigsuspend # branch to sys32_rt_sigsuspend
420 sys_sigaltstack_glue:
421 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
422 jg sys_sigaltstack # branch to sys_sigreturn
424 #ifdef CONFIG_S390_SUPPORT
425 sys32_sigaltstack_glue:
426 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
427 jg sys32_sigaltstack_wrapper # branch to sys_sigreturn
431 * Program check handler routine
434 .globl pgm_check_handler
437 * First we need to check for a special case:
438 * Single stepping an instruction that disables the PER event mask will
439 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
440 * For a single stepped SVC the program check handler gets control after
441 * the SVC new PSW has been loaded. But we want to execute the SVC first and
442 * then handle the PER event. Therefore we update the SVC old PSW to point
443 * to the pgm_check_handler and branch to the SVC handler after we checked
444 * if we have to load the kernel stack register.
445 * For every other possible cause for PER event without the PER mask set
446 * we just ignore the PER event (FIXME: is there anything we have to do
449 SAVE_ALL_BASE __LC_SAVE_AREA
450 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
451 jnz pgm_per # got per exception -> special case
452 SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
453 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
454 lgf %r3,__LC_PGM_ILC # load program interruption code
459 larl %r1,pgm_check_table
460 lg %r1,0(%r8,%r1) # load address of handler routine
461 la %r2,SP_PTREGS(%r15) # address of register-save area
462 larl %r14,sysc_return
463 br %r1 # branch to interrupt-handler
466 # handle per exception
469 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
470 jnz pgm_per_std # ok, normal per event from user space
471 # ok its one of the special cases, now we need to find out which one
472 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
474 # no interesting special case, ignore PER event
475 lmg %r12,%r15,__LC_SAVE_AREA
476 lpswe __LC_PGM_OLD_PSW
479 # Normal per exception
482 SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
483 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
484 lg %r1,__TI_task(%r9)
485 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
486 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
487 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
488 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
489 lgf %r3,__LC_PGM_ILC # load program interruption code
491 ngr %r8,%r3 # clear per-event-bit and ilc
496 # it was a single stepped SVC that is causing all the trouble
499 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
500 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
501 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
502 lg %r1,__TI_task(%r9)
503 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
504 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
505 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
506 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
507 stosm 48(%r15),0x03 # reenable interrupts
511 * IO interrupt handler routine
513 .globl io_int_handler
516 SAVE_ALL_BASE __LC_SAVE_AREA+32
517 SAVE_ALL __LC_IO_OLD_PSW,__LC_SAVE_AREA+32,0
518 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
519 la %r2,SP_PTREGS(%r15) # address of register-save area
520 brasl %r14,do_IRQ # call standard irq handler
523 tm SP_PSW+1(%r15),0x01 # returning to user ?
524 #ifdef CONFIG_PREEMPT
525 jno io_preempt # no -> check for preemptive scheduling
527 jno io_leave # no-> skip resched & signal
529 tm __TI_flags+7(%r9),_TIF_WORK_INT
530 jnz io_work # there is work to do (signals etc.)
534 #ifdef CONFIG_PREEMPT
536 icm %r0,15,__TI_precount(%r9)
538 # switch to kernel stack
541 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
542 xc 0(8,%r1),0(%r1) # clear back chain
545 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
548 mvc __TI_precount(4,%r9),0(%r1)
549 stosm 48(%r15),0x03 # reenable interrupts
550 brasl %r14,schedule # call schedule
551 stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
552 xc __TI_precount(4,%r9),__TI_precount(%r9)
557 # switch to kernel stack, then check TIF bits
560 lg %r1,__LC_KERNEL_STACK
562 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
563 xc 0(8,%r1),0(%r1) # clear back chain
566 # One of the work bits is on. Find out which one.
567 # Checked are: _TIF_SIGPENDING and _TIF_NEED_RESCHED
570 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
572 tm __TI_flags+7(%r9),_TIF_SIGPENDING
577 # _TIF_NEED_RESCHED is set, call schedule
580 stosm 48(%r15),0x03 # reenable interrupts
581 brasl %r14,schedule # call scheduler
582 stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
583 tm __TI_flags+7(%r9),_TIF_WORK_INT
584 jz io_leave # there is no work to do
588 # _TIF_SIGPENDING is set, call do_signal
591 stosm 48(%r15),0x03 # reenable interrupts
592 la %r2,SP_PTREGS(%r15) # load pt_regs
593 slgr %r3,%r3 # clear *oldset
594 brasl %r14,do_signal # call do_signal
595 stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
596 j sysc_leave # out of here, do NOT recheck
599 * External interrupt handler routine
601 .globl ext_int_handler
604 SAVE_ALL_BASE __LC_SAVE_AREA+32
605 SAVE_ALL __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32,0
606 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
607 la %r2,SP_PTREGS(%r15) # address of register-save area
608 llgh %r3,__LC_EXT_INT_CODE # get interruption code
613 * Machine check handler routines
615 .globl mcck_int_handler
617 SAVE_ALL_BASE __LC_SAVE_AREA+64
618 SAVE_ALL __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64,0
619 brasl %r14,s390_do_machine_check
625 * Restart interruption handler, kick starter for additional CPUs
627 .globl restart_int_handler
629 lg %r15,__LC_SAVE_AREA+120 # load ksp
630 lghi %r10,__LC_CREGS_SAVE_AREA
631 lctlg %c0,%c15,0(%r10) # get new ctl regs
632 lghi %r10,__LC_AREGS_SAVE_AREA
634 stosm 0(%r15),0x04 # now we can turn dat on
635 lmg %r6,%r15,48(%r15) # load registers from clone
639 * If we do not run with SMP enabled, let the new CPU crash ...
641 .globl restart_int_handler
645 lpswe restart_crash-restart_base(%r1)
648 .long 0x000a0000,0x00000000,0x00000000,0x00000000
652 cleanup_table_system_call:
653 .quad system_call, sysc_do_svc
654 cleanup_table_sysc_return:
655 .quad sysc_return, sysc_leave
656 cleanup_table_sysc_leave:
657 .quad sysc_leave, sysc_work_loop
658 cleanup_table_sysc_work_loop:
659 .quad sysc_work_loop, sysc_reschedule
662 clc 8(8,%r12),BASED(cleanup_table_system_call)
664 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
665 jl cleanup_system_call
667 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
669 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
670 jl cleanup_sysc_return
672 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
674 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
675 jl cleanup_sysc_leave
677 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
679 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
680 jl cleanup_sysc_leave
685 mvc __LC_RETURN_PSW(8),0(%r12)
686 clc 8(8,%r12),BASED(cleanup_table_system_call)
688 mvc __LC_SAVE_AREA(32),__LC_SAVE_AREA+32
689 0: stg %r13,__LC_SAVE_AREA+40
690 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
691 stg %r15,__LC_SAVE_AREA+56
692 llgh %r7,__LC_SVC_INT_CODE
693 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
694 la %r12,__LC_RETURN_PSW
698 mvc __LC_RETURN_PSW(8),0(%r12)
699 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
700 la %r12,__LC_RETURN_PSW
704 clc 8(8,%r12),BASED(cleanup_sysc_leave_lpsw)
706 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
707 mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
708 lmg %r0,%r11,SP_R0(%r15)
710 0: la %r12,__LC_RETURN_PSW
712 cleanup_sysc_leave_lpsw:
713 .quad sysc_leave + 12
720 .Lc_pactive: .long PREEMPT_ACTIVE
721 .Lnr_syscalls: .long NR_syscalls
722 .L0x0130: .short 0x130
723 .L0x0140: .short 0x140
724 .L0x0150: .short 0x150
725 .L0x0160: .short 0x160
726 .L0x0170: .short 0x170
728 .quad __critical_start
732 #define SYSCALL(esa,esame,emu) .long esame
733 .globl sys_call_table
735 #include "syscalls.S"
738 #ifdef CONFIG_S390_SUPPORT
740 #define SYSCALL(esa,esame,emu) .long emu
741 .globl sys_call_table_emu
743 #include "syscalls.S"