arch/s390/kernel/reipl64.S

   1 /*
   2  *  arch/s390/kernel/reipl.S
   3  *
   4  *  S390 version
   5  *    Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
   7                  Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
   8  */
   9
  10 #include <asm/lowcore.h>
  11                 .globl  do_reipl
  12 do_reipl:       basr    %r13,0
  13 .Lpg0:          lpswe   .Lnewpsw-.Lpg0(%r13)
  14 .Lpg1:          lctlg   %c6,%c6,.Lall-.Lpg0(%r13)
  15                 stctg   %c0,%c0,.Lctlsave-.Lpg0(%r13)
  16                 ni      .Lctlsave+4-.Lpg0(%r13),0xef
  17                 lctlg   %c0,%c0,.Lctlsave-.Lpg0(%r13)
  18                 lgr     %r1,%r2
  19                 mvc     __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
  20                 stsch   .Lschib-.Lpg0(%r13)
  21                 oi      .Lschib+5-.Lpg0(%r13),0x84
  22 .Lecs:          xi      .Lschib+27-.Lpg0(%r13),0x01
  23                 msch    .Lschib-.Lpg0(%r13)
  24                 lghi    %r0,5
  25 .Lssch:         ssch    .Liplorb-.Lpg0(%r13)
  26                 jz      .L001
  27                 brct    %r0,.Lssch
  28                 bas     %r14,.Ldisab-.Lpg0(%r13)
  29 .L001:          mvc     __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
  30 .Ltpi:          lpswe   .Lwaitpsw-.Lpg0(%r13)
  31 .Lcont:         c       %r1,__LC_SUBCHANNEL_ID
  32                 jnz     .Ltpi
  33                 clc     __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
  34                 jnz     .Ltpi
  35                 tsch    .Liplirb-.Lpg0(%r13)
  36                 tm      .Liplirb+9-.Lpg0(%r13),0xbf
  37                 jz      .L002
  38                 bas     %r14,.Ldisab-.Lpg0(%r13)
  39 .L002:          tm      .Liplirb+8-.Lpg0(%r13),0xf3
  40                 jz      .L003
  41                 bas     %r14,.Ldisab-.Lpg0(%r13)
  42 .L003:          spx     .Lnull-.Lpg0(%r13)
  43                 st      %r1,__LC_SUBCHANNEL_ID
  44                 lhi     %r1,0            # mode 0 = esa
  45                 slr     %r0,%r0          # set cpuid to zero
  46                 sigp    %r1,%r0,0x12     # switch to esa mode
  47                 lpsw    0
  48 .Ldisab:        sll    %r14,1
  49                 srl    %r14,1            # need to kill hi bit to avoid specification exceptions.
  50                 st     %r14,.Ldispsw+12-.Lpg0(%r13)
  51                 lpswe   .Ldispsw-.Lpg0(%r13)
  52                 .align  8
  53 .Lall:          .quad   0x00000000ff000000
  54 .Lctlsave:      .quad   0x0000000000000000
  55 .Lnull:         .long   0x0000000000000000
  56                 .align  16
  57 /*
  58  * These addresses have to be 31 bit otherwise
  59  * the sigp will throw a specifcation exception
  60  * when switching to ESA mode as bit 31 be set
  61  * in the ESA psw.
  62  * Bit 31 of the addresses has to be 0 for the
  63  * 31bit lpswe instruction a fact they appear to have
  64  * ommited from the pop.
  65  */
  66 .Lnewpsw:       .quad   0x0000000080000000
  67                 .quad   .Lpg1
  68 .Lpcnew:        .quad   0x0000000080000000
  69                 .quad   .Lecs
  70 .Lionew:        .quad   0x0000000080000000
  71                 .quad   .Lcont
  72 .Lwaitpsw:      .quad   0x0202000080000000
  73                 .quad   .Ltpi
  74 .Ldispsw:       .quad   0x0002000080000000
  75                 .quad   0x0000000000000000
  76 .Liplccws:      .long   0x02000000,0x60000018
  77                 .long   0x08000008,0x20000001
  78 .Liplorb:       .long   0x0049504c,0x0040ff80
  79                 .long   0x00000000+.Liplccws
  80 .Lschib:        .long   0x00000000,0x00000000
  81                 .long   0x00000000,0x00000000
  82                 .long   0x00000000,0x00000000
  83                 .long   0x00000000,0x00000000
  84                 .long   0x00000000,0x00000000
  85                 .long   0x00000000,0x00000000
  86 .Liplirb:       .long   0x00000000,0x00000000
  87                 .long   0x00000000,0x00000000
  88                 .long   0x00000000,0x00000000
  89                 .long   0x00000000,0x00000000
  90                 .long   0x00000000,0x00000000
  91                 .long   0x00000000,0x00000000
  92                 .long   0x00000000,0x00000000
  93                 .long   0x00000000,0x00000000
  94
  95
  96