arch/sh/drivers/pci/pci-auto.c

   1 /*
   2  * PCI autoconfiguration library
   3  *
   4  * Author: Matt Porter <mporter@mvista.com>
   5  *
   6  * Copyright 2000, 2001 MontaVista Software Inc.
   7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8  * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /*
  17  * Modified for MIPS by Jun Sun, jsun@mvista.com
  18  *
  19  * . Simplify the interface between pci_auto and the rest: a single function.
  20  * . Assign resources from low address to upper address.
  21  * . change most int to u32.
  22  *
  23  * Further modified to include it as mips generic code, ppopov@mvista.com.
  24  *
  25  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  26  * - Add a top_bus argument to the "early config" functions so that
  27  *   they can set a fake parent bus pointer to convince the underlying
  28  *   pci ops to use type 1 configuration for sub busses.
  29  * - Set bridge base and limit registers correctly.
  30  * - Align io and memory base properly before and after bridge setup.
  31  * - Don't fall through to pci_setup_bars for bridge.
  32  * - Reformat the debug output to look more like lspci's output.
  33  *
  34  * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
  35  *
  36  * 2003-08-05  Paul Mundt <lethal@linux-sh.org>
  37  * - Don't update the BAR values on systems that already have valid addresses
  38  *   and don't want these updated for whatever reason, by way of a new config
  39  *   option check. However, we still read in the old BAR values so that they
  40  *   can still be reported through the debug output.
  41  */
  42
  43 #include <linux/kernel.h>
  44 #include <linux/init.h>
  45 #include <linux/types.h>
  46 #include <linux/pci.h>
  47
  48 #define DEBUG
  49 #ifdef  DEBUG
  50 #define DBG(x...)       printk(x)
  51 #else
  52 #define DBG(x...)
  53 #endif
  54
  55 /*
  56  * These functions are used early on before PCI scanning is done
  57  * and all of the pci_dev and pci_bus structures have been created.
  58  */
  59 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  60         int top_bus, int busnr, int devfn)
  61 {
  62         static struct pci_dev dev;
  63         static struct pci_bus bus;
  64
  65         dev.bus = &bus;
  66         dev.sysdata = hose;
  67         dev.devfn = devfn;
  68         bus.number = busnr;
  69         bus.ops = hose->pci_ops;
  70
  71         if(busnr != top_bus)
  72                 /* Fake a parent bus structure. */
  73                 bus.parent = &bus;
  74         else
  75                 bus.parent = NULL;
  76
  77         return &dev;
  78 }
  79
  80 #define EARLY_PCI_OP(rw, size, type)                                    \
  81 int early_##rw##_config_##size(struct pci_channel *hose,                \
  82         int top_bus, int bus, int devfn, int offset, type value)        \
  83 {                                                                       \
  84         return pci_##rw##_config_##size(                                \
  85                 fake_pci_dev(hose, top_bus, bus, devfn),                \
  86                 offset, value);                                         \
  87 }
  88
  89 EARLY_PCI_OP(read, byte, u8 *)
  90 EARLY_PCI_OP(read, word, u16 *)
  91 EARLY_PCI_OP(read, dword, u32 *)
  92 EARLY_PCI_OP(write, byte, u8)
  93 EARLY_PCI_OP(write, word, u16)
  94 EARLY_PCI_OP(write, dword, u32)
  95
  96 static struct resource *io_resource_inuse;
  97 static struct resource *mem_resource_inuse;
  98
  99 static u32 pciauto_lower_iospc;
 100 static u32 pciauto_upper_iospc;
 101
 102 static u32 pciauto_lower_memspc;
 103 static u32 pciauto_upper_memspc;
 104
 105 static void __init
 106 pciauto_setup_bars(struct pci_channel *hose,
 107                    int top_bus,
 108                    int current_bus,
 109                    int pci_devfn)
 110 {
 111         u32 bar_response, bar_size, bar_value;
 112         u32 bar, addr_mask, bar_nr = 0;
 113         u32 * upper_limit;
 114         u32 * lower_limit;
 115         int found_mem64 = 0;
 116
 117         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) {
 118                 u32 bar_addr;
 119
 120                 /* Read the old BAR value */
 121                 early_read_config_dword(hose, top_bus,
 122                                         current_bus,
 123                                         pci_devfn,
 124                                         bar,
 125                                         &bar_addr);
 126
 127                 /* Tickle the BAR and get the response */
 128                 early_write_config_dword(hose, top_bus,
 129                                          current_bus,
 130                                          pci_devfn,
 131                                          bar,
 132                                          0xffffffff);
 133
 134                 early_read_config_dword(hose, top_bus,
 135                                         current_bus,
 136                                         pci_devfn,
 137                                         bar,
 138                                         &bar_response);
 139
 140                 /*
 141                  * Write the old BAR value back out, only update the BAR
 142                  * if we implicitly want resources to be updated, which
 143                  * is done by the generic code further down. -- PFM.
 144                  */
 145                 early_write_config_dword(hose, top_bus,
 146                                          current_bus,
 147                                          pci_devfn,
 148                                          bar,
 149                                          bar_addr);
 150
 151                 /* If BAR is not implemented go to the next BAR */
 152                 if (!bar_response)
 153                         continue;
 154
 155                 /*
 156                  * Workaround for a BAR that doesn't use its upper word,
 157                  * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
 158                  * bdl <brad@ltc.com>
 159                  */
 160                 if (!(bar_response & 0xffff0000))
 161                         bar_response |= 0xffff0000;
 162
 163 retry:
 164                 /* Check the BAR type and set our address mask */
 165                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 166                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 167                         upper_limit = &pciauto_upper_iospc;
 168                         lower_limit = &pciauto_lower_iospc;
 169                         DBG("        I/O");
 170                 } else {
 171                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 172                             PCI_BASE_ADDRESS_MEM_TYPE_64)
 173                                 found_mem64 = 1;
 174
 175                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
 176                         upper_limit = &pciauto_upper_memspc;
 177                         lower_limit = &pciauto_lower_memspc;
 178                         DBG("        Mem");
 179                 }
 180
 181
 182                 /* Calculate requested size */
 183                 bar_size = ~(bar_response & addr_mask) + 1;
 184
 185                 /* Allocate a base address */
 186                 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 187
 188                 if ((bar_value + bar_size) > *upper_limit) {
 189                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 190                                 if (io_resource_inuse->child) {
 191                                         io_resource_inuse =
 192                                                 io_resource_inuse->child;
 193                                         pciauto_lower_iospc =
 194                                                 io_resource_inuse->start;
 195                                         pciauto_upper_iospc =
 196                                                 io_resource_inuse->end + 1;
 197                                         goto retry;
 198                                 }
 199
 200                         } else {
 201                                 if (mem_resource_inuse->child) {
 202                                         mem_resource_inuse =
 203                                                 mem_resource_inuse->child;
 204                                         pciauto_lower_memspc =
 205                                                 mem_resource_inuse->start;
 206                                         pciauto_upper_memspc =
 207                                                 mem_resource_inuse->end + 1;
 208                                         goto retry;
 209                                 }
 210                         }
 211                         DBG(" unavailable -- skipping, value %x size %x\n",
 212                                         bar_value, bar_size);
 213                         continue;
 214                 }
 215
 216 #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
 217                 /* Write it out and update our limit */
 218                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 219                                          bar, bar_value);
 220 #endif
 221
 222                 *lower_limit = bar_value + bar_size;
 223
 224                 /*
 225                  * If we are a 64-bit decoder then increment to the
 226                  * upper 32 bits of the bar and force it to locate
 227                  * in the lower 4GB of memory.
 228                  */
 229                 if (found_mem64) {
 230                         bar += 4;
 231                         early_write_config_dword(hose, top_bus,
 232                                                  current_bus,
 233                                                  pci_devfn,
 234                                                  bar,
 235                                                  0x00000000);
 236                 }
 237
 238                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 239
 240                 bar_nr++;
 241         }
 242
 243 }
 244
 245 static void __init
 246 pciauto_prescan_setup_bridge(struct pci_channel *hose,
 247                              int top_bus,
 248                              int current_bus,
 249                              int pci_devfn,
 250                              int sub_bus)
 251 {
 252         /* Configure bus number registers */
 253         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 254                                 PCI_PRIMARY_BUS, current_bus);
 255         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 256                                 PCI_SECONDARY_BUS, sub_bus + 1);
 257         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 258                                 PCI_SUBORDINATE_BUS, 0xff);
 259
 260         /* Align memory and I/O to 1MB and 4KB boundaries. */
 261         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 262                 & ~(0x100000 - 1);
 263         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 264                 & ~(0x1000 - 1);
 265
 266         /* Set base (lower limit) of address range behind bridge. */
 267         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 268                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 269         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 270                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 271         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 272                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 273
 274         /* We don't support prefetchable memory for now, so disable */
 275         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 276                                 PCI_PREF_MEMORY_BASE, 0);
 277         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 278                                 PCI_PREF_MEMORY_LIMIT, 0);
 279 }
 280
 281 static void __init
 282 pciauto_postscan_setup_bridge(struct pci_channel *hose,
 283                               int top_bus,
 284                               int current_bus,
 285                               int pci_devfn,
 286                               int sub_bus)
 287 {
 288         u32 temp;
 289
 290         pciauto_lower_memspc += 1;
 291         pciauto_lower_iospc += 1;
 292
 293         /* Configure bus number registers */
 294         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 295                                 PCI_SUBORDINATE_BUS, sub_bus);
 296
 297         /* Set upper limit of address range behind bridge. */
 298         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 299                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 300         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 301                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 302         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 303                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 304
 305         /* Align memory and I/O to 1MB and 4KB boundaries. */
 306         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 307                 & ~(0x100000 - 1);
 308         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 309                 & ~(0x1000 - 1);
 310
 311         /* Enable memory and I/O accesses, enable bus master */
 312         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 313                 PCI_COMMAND, &temp);
 314         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 315                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 316                 | PCI_COMMAND_MASTER);
 317 }
 318
 319 static void __init
 320 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
 321                             int top_bus,
 322                             int current_bus,
 323                             int pci_devfn,
 324                             int sub_bus)
 325 {
 326        /* Configure bus number registers */
 327        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 328                                PCI_PRIMARY_BUS, current_bus);
 329        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 330                                PCI_SECONDARY_BUS, sub_bus + 1);
 331        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 332                                PCI_SUBORDINATE_BUS, 0xff);
 333
 334        /* Align memory and I/O to 4KB and 4 byte boundaries. */
 335        pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 336                & ~(0x1000 - 1);
 337        pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 338                & ~(0x4 - 1);
 339
 340        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 341                PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
 342        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 343                PCI_CB_IO_BASE_0, pciauto_lower_iospc);
 344 }
 345
 346 static void __init
 347 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
 348                              int top_bus,
 349                              int current_bus,
 350                              int pci_devfn,
 351                              int sub_bus)
 352 {
 353        u32 temp;
 354
 355        /*
 356         * [jsun] we always bump up baselines a little, so that if there
 357         * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 358         * spaces.
 359         */
 360        pciauto_lower_memspc += 1;
 361        pciauto_lower_iospc += 1;
 362
 363        /*
 364         * Configure subordinate bus number.  The PCI subsystem
 365         * bus scan will renumber buses (reserving three additional
 366         * for this PCI<->CardBus bridge for the case where a CardBus
 367         * adapter contains a P2P or CB2CB bridge.
 368         */
 369
 370        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 371                                PCI_SUBORDINATE_BUS, sub_bus);
 372
 373        /*
 374         * Reserve an additional 4MB for mem space and 16KB for
 375         * I/O space.  This should cover any additional space
 376         * requirement of unusual CardBus devices with
 377         * additional bridges that can consume more address space.
 378         *
 379         * Although pcmcia-cs currently will reprogram bridge
 380         * windows, the goal is to add an option to leave them
 381         * alone and use the bridge window ranges as the regions
 382         * that are searched for free resources upon hot-insertion
 383         * of a device.  This will allow a PCI<->CardBus bridge
 384         * configured by this routine to happily live behind a
 385         * P2P bridge in a system.
 386         */
 387
 388        /* Align memory and I/O to 4KB and 4 byte boundaries. */
 389        pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 390                & ~(0x1000 - 1);
 391        pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 392                & ~(0x4 - 1);
 393        /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 394        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 395                PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
 396        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 397                PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
 398
 399        /* Enable memory and I/O accesses, enable bus master */
 400        early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 401                PCI_COMMAND, &temp);
 402        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 403                PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 404                | PCI_COMMAND_MASTER);
 405 }
 406
 407 #define      PCIAUTO_IDE_MODE_MASK           0x05
 408
 409 static int __init
 410 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 411 {
 412         int sub_bus;
 413         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 414         unsigned short vid, did;
 415         unsigned char header_type;
 416         int devfn_start = 0;
 417         int devfn_stop = 0xff;
 418
 419         sub_bus = current_bus;
 420
 421         if (hose->first_devfn)
 422                 devfn_start = hose->first_devfn;
 423         if (hose->last_devfn)
 424                 devfn_stop = hose->last_devfn;
 425
 426         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 427
 428                 if (PCI_FUNC(pci_devfn) && !found_multi)
 429                         continue;
 430
 431                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 432                                        PCI_VENDOR_ID, &vid);
 433
 434                 if (vid == 0xffff) continue;
 435
 436                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 437                                        PCI_HEADER_TYPE, &header_type);
 438
 439                 if (!PCI_FUNC(pci_devfn))
 440                         found_multi = header_type & 0x80;
 441
 442                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 443                                        PCI_DEVICE_ID, &did);
 444
 445                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 446                                         PCI_CLASS_REVISION, &pci_class);
 447
 448                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 449                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 450                         pci_class >> 16, vid, did);
 451                 if (pci_class & 0xff)
 452                         DBG(" (rev %.2x)", pci_class & 0xff);
 453                 DBG("\n");
 454
 455                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 456                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 457                                 current_bus, sub_bus + 1);
 458                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 459                                                      pci_devfn, sub_bus);
 460                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 461                                 sub_bus + 1,
 462                                 pciauto_lower_iospc, pciauto_lower_memspc);
 463                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 464                         DBG("Back to bus %.2x\n", current_bus);
 465                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 466                                                       pci_devfn, sub_bus);
 467                         continue;
 468                 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 469                         DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
 470                                 current_bus, sub_bus + 1);
 471                         DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 472                         /* Place CardBus Socket/ExCA registers */
 473                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn);
 474
 475                         pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
 476                                         current_bus, pci_devfn, sub_bus);
 477
 478                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 479                                 sub_bus + 1,
 480                                 pciauto_lower_iospc, pciauto_lower_memspc);
 481                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 482                         DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
 483                         pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
 484                                         current_bus, pci_devfn, sub_bus);
 485                         continue;
 486                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 487
 488                         unsigned char prg_iface;
 489
 490                         early_read_config_byte(hose, top_bus, current_bus,
 491                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
 492                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 493                                 DBG("Skipping legacy mode IDE controller\n");
 494                                 continue;
 495                         }
 496                 }
 497
 498                 /*
 499                  * Found a peripheral, enable some standard
 500                  * settings
 501                  */
 502                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 503                                         PCI_COMMAND, &cmdstat);
 504                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 505                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 506                                          PCI_COMMAND_MEMORY |
 507                                          PCI_COMMAND_MASTER);
 508                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 509                                         PCI_LATENCY_TIMER, 0x80);
 510
 511                 /* Allocate PCI I/O and/or memory space */
 512                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn);
 513         }
 514         return sub_bus;
 515 }
 516
 517 int __init
 518 pciauto_assign_resources(int busno, struct pci_channel *hose)
 519 {
 520         /* setup resource limits */
 521         io_resource_inuse = hose->io_resource;
 522         mem_resource_inuse = hose->mem_resource;
 523
 524         pciauto_lower_iospc = io_resource_inuse->start;
 525         pciauto_upper_iospc = io_resource_inuse->end + 1;
 526         pciauto_lower_memspc = mem_resource_inuse->start;
 527         pciauto_upper_memspc = mem_resource_inuse->end + 1;
 528         DBG("Autoconfig PCI channel 0x%p\n", hose);
 529         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 530                 busno, pciauto_lower_iospc, pciauto_upper_iospc,
 531                 pciauto_lower_memspc, pciauto_upper_memspc);
 532
 533         return pciauto_bus_scan(hose, busno, busno);
 534 }