2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
7 * Support functions for the ST40 PCI hardware.
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/types.h>
20 #include <linux/irq.h>
24 /* This is in P2 of course */
25 #define ST40PCI_BASE_ADDRESS (0xb0000000)
26 #define ST40PCI_MEM_ADDRESS (ST40PCI_BASE_ADDRESS+0x0)
27 #define ST40PCI_IO_ADDRESS (ST40PCI_BASE_ADDRESS+0x06000000)
28 #define ST40PCI_REG_ADDRESS (ST40PCI_BASE_ADDRESS+0x07000000)
30 #define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
32 #define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
33 #define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
34 #define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
36 #define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
37 #define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
38 #define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
40 #define ST40PCI_SERR_IRQ 64
41 #define ST40PCI_SERR_INT_GROUP 0
42 #define ST40PCI_SERR_INT_POS 0
43 #define ST40PCI_SERR_INT_PRI 15
45 #define ST40PCI_ERR_IRQ 65
46 #define ST40PCI_ERR_INT_GROUP 1
47 #define ST40PCI_ERR_INT_POS 1
48 #define ST40PCI_ERR_INT_PRI 14
51 /* Macros to extract PLL params */
52 #define PLL_MDIV(reg) ( ((unsigned)reg) & 0xff )
53 #define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
54 #define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
55 #define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
57 /* Build up the appropriate settings */
58 #define PLL_SET(mdiv,ndiv,pdiv,setup) \
59 ( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
61 #define PLLPCICR (0xbb040000+0x10)
63 #define PLLPCICR_POWERON (1<<28)
64 #define PLLPCICR_OUT_EN (1<<29)
65 #define PLLPCICR_LOCKSELECT (1<<30)
66 #define PLLPCICR_LOCK (1<<31)
69 #define PLL_25MHZ 0x793c8512
70 #define PLL_33MHZ PLL_SET(18,88,3,295)
73 static __init void SetPCIPLL(void)
78 /* Always run at 33Mhz. The PCI clock is totally async
79 * to the rest of the system
81 writel(PLL_33MHZ | PLLPCICR_POWERON, PLLPCICR);
83 printk("ST40PCI: Waiting for PCI PLL to lock\n");
84 while ((readl(PLLPCICR) & PLLPCICR_LOCK) == 0);
85 writel(readl(PLLPCICR) | PLLPCICR_OUT_EN, PLLPCICR);
89 static irqreturn_t st40_pci_irq(int irq, void *dev_instance, struct pt_regs *regs)
92 unsigned pci_int, pci_air, pci_cir, pci_aint;
94 pci_int = ST40PCI_READ(INT);
95 pci_cir = ST40PCI_READ(CIR);
96 pci_air = ST40PCI_READ(AIR);
99 printk("PCI INTERRUPT!\n");
100 printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
101 printk("PCI AIR -> 0x%x\n", pci_air);
102 printk("PCI CIR -> 0x%x\n", pci_cir);
103 ST40PCI_WRITE(INT, ~0);
106 pci_aint = ST40PCI_READ(AINT);
108 printk("PCI ARB INTERRUPT!\n");
109 printk("PCI AINT -> 0x%x\n", pci_aint);
110 printk("PCI AIR -> 0x%x\n", pci_air);
111 printk("PCI CIR -> 0x%x\n", pci_cir);
112 ST40PCI_WRITE(AINT, ~0);
119 /* Rounds a number UP to the nearest power of two. Used for
120 * sizing the PCI window.
122 static u32 __init r2p2(u32 num)
138 /* If the original number isn't a power of 2, round it up */
145 static void __init pci_fixup_ide_bases(struct pci_dev *d)
150 * PCI IDE controllers use non-standard I/O port decoding, respect it.
152 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
154 printk("PCI: IDE base address fixup for %s\n", d->slot_name);
156 struct resource *r = &d->resource[i];
157 if ((r->start & ~0x80) == 0x374) {
165 /* Add future fixups here... */
166 struct pci_fixup pcibios_fixups[] = {
167 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
171 int __init st40pci_init(unsigned memStart, unsigned memSize)
177 /* Initialises the ST40 pci subsystem, performing a reset, then programming
178 * up the address space decoders appropriately
181 /* Should reset core here as well methink */
183 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
185 /* Loop while core resets */
186 while (ST40PCI_READ(CR) & CR_SOFT_RESET);
188 /* Now, lets reset all the cards on the bus with extreme prejudice */
189 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
192 /* Set bus active, take it out of reset */
193 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_CFINT | CR_PFCS | CR_PFE);
195 /* The PCI spec says that no access must be made to the bus until 1 second
196 * after reset. This seem ludicrously long, but some delay is needed here
200 /* Switch off interrupts */
201 ST40PCI_WRITE(INTM, 0);
202 ST40PCI_WRITE(AINT, 0);
204 /* Allow it to be a master */
206 ST40PCI_WRITE_SHORT(CSR_CMD,
207 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
210 /* Accesse to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
211 * on the PCI bus. This allows a nice 1-1 bus to phys mapping.
215 ST40PCI_WRITE(MBR, 0x10000000);
216 /* Always set the max size 128M (actually, it is only 96MB wide) */
217 ST40PCI_WRITE(MBMR, 0x07ff0000);
219 /* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
220 * allow cards that have legacy io such as vga to function correctly. This gives a
221 * maximum of 64K of io/space as only the bottom 16 bits of the address are copied
222 * over to the bus when the transaction is made. 64K of io space is more than enough
224 ST40PCI_WRITE(IOBR, 0x0);
225 /* Set up the 64K window */
226 ST40PCI_WRITE(IOBMR, 0x0);
228 /* Now we set up the mbars so the PCI bus can see the memory of the machine */
230 if (memSize < (64 * 1024)) {
231 printk("Ridiculous memory size of 0x%x?\n",memSize);
237 (512 * 1024 * 1024)) ? 0x1fff0001 : ((r2p2(memSize) -
240 ST40PCI_WRITE(LSR0, lsr0);
242 ST40PCI_WRITE(CSR_MBAR0, memStart);
243 ST40PCI_WRITE(LAR0, memStart);
245 /* Maximise timeout values */
246 ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
247 ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
248 ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
251 /* Install the pci interrupt handlers */
252 make_intc2_irq(ST40PCI_SERR_IRQ, INTC2_BASE0,
253 ST40PCI_SERR_INT_GROUP, ST40PCI_SERR_INT_POS,
254 ST40PCI_SERR_INT_PRI);
256 make_intc2_irq(ST40PCI_ERR_IRQ, INTC2_BASE0, ST40PCI_ERR_INT_GROUP,
257 ST40PCI_ERR_INT_POS, ST40PCI_ERR_INT_PRI);
263 char * __init pcibios_setup(char *str)
269 #define SET_CONFIG_BITS(bus,devfn,where)\
270 (((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
272 #define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
275 static int CheckForMasterAbort(void)
277 if (ST40PCI_READ(INT) & INT_MADIM) {
278 /* Should we clear config space version as well ??? */
279 ST40PCI_WRITE(INT, INT_MADIM);
280 ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
287 /* Write to config register */
288 static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
290 ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
293 *val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
296 *val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
299 *val = ST40PCI_READ(PDR);
303 if (CheckForMasterAbort()){
317 return PCIBIOS_SUCCESSFUL;
320 static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
322 ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
326 ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
329 ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
332 ST40PCI_WRITE(PDR, val);
336 CheckForMasterAbort();
338 return PCIBIOS_SUCCESSFUL;
341 static struct pci_ops pci_config_ops = {
342 .read = st40pci_read,
343 .write = st40pci_write,
347 /* Everything hangs off this */
348 static struct pci_bus *pci_root_bus;
351 static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
353 return PCI_SLOT(dev->devfn);
357 /* This needs to be shunted out of here into the board specific bit */
358 #define HARP_PCI_IRQ 1
359 #define HARP_BRIDGE_IRQ 2
360 #define OVERDRIVE_SLOT0_IRQ 0
362 static int __init map_harp_irq(struct pci_dev *dev, u8 slot, u8 pin)
365 #ifdef CONFIG_SH_STB1_HARP
366 case 2: /*This is the PCI slot on the */
368 case 1: /* this is the bridge */
369 return HARP_BRIDGE_IRQ;
370 #elif defined(CONFIG_SH_STB1_OVERDRIVE)
383 void __init pcibios_init(void)
385 extern unsigned long memory_start, memory_end;
387 if (sh_mv.mv_init_pci != NULL) {
391 /* The pci subsytem needs to know where memory is and how much
392 * of it there is. I've simply made these globals. A better mechanism
393 * is probably needed.
395 st40pci_init(PHYSADDR(memory_start),
396 PHYSADDR(memory_end) - PHYSADDR(memory_start));
398 if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
399 SA_INTERRUPT, "st40pci", NULL)) {
400 printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
404 /* Enable the PCI interrupts on the device */
405 ST40PCI_WRITE(INTM, ~0);
406 ST40PCI_WRITE(AINT, ~0);
408 /* Map the io address apprioately */
409 #ifdef CONFIG_HD64465
410 hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
411 ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
414 /* ok, do the scan man */
415 pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
416 pci_assign_unassigned_resources();
417 pci_fixup_irqs(no_swizzle, map_harp_irq);
421 void __init pcibios_fixup_bus(struct pci_bus *bus)