1 /* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $
3 * linux/arch/sh/kernel/irq_ipr.c
5 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
6 * Copyright (C) 2000 Kazumoto Kojima
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
9 * Interrupt handling for IPR-based IRQ.
12 * On-chip supporting modules (TMU, RTC, etc.).
13 * On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
14 * Hitachi SolutionEngine external I/O:
15 * MS7709SE01, MS7709ASE01, and MS7750SE01
19 #include <linux/config.h>
20 #include <linux/init.h>
21 #include <linux/irq.h>
23 #include <asm/system.h>
25 #include <asm/machvec.h>
28 unsigned int addr; /* Address of Interrupt Priority Register */
29 int shift; /* Shifts of the 16-bit data */
30 int priority; /* The priority */
32 static struct ipr_data ipr_data[NR_IRQS];
34 static void enable_ipr_irq(unsigned int irq);
35 static void disable_ipr_irq(unsigned int irq);
37 /* shutdown is same as "disable" */
38 #define shutdown_ipr_irq disable_ipr_irq
40 static void mask_and_ack_ipr(unsigned int);
41 static void end_ipr_irq(unsigned int irq);
43 static unsigned int startup_ipr_irq(unsigned int irq)
46 return 0; /* never anything pending */
49 static struct hw_interrupt_type ipr_irq_type = {
59 static void disable_ipr_irq(unsigned int irq)
61 unsigned long val, flags;
62 unsigned int addr = ipr_data[irq].addr;
63 unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
65 /* Set the priority in IPR to 0 */
66 local_irq_save(flags);
70 local_irq_restore(flags);
73 static void enable_ipr_irq(unsigned int irq)
75 unsigned long val, flags;
76 unsigned int addr = ipr_data[irq].addr;
77 int priority = ipr_data[irq].priority;
78 unsigned short value = (priority << ipr_data[irq].shift);
80 /* Set priority in IPR back to original value */
81 local_irq_save(flags);
85 local_irq_restore(flags);
88 static void mask_and_ack_ipr(unsigned int irq)
92 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
93 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
94 /* This is needed when we use edge triggered setting */
95 /* XXX: Is it really needed? */
96 if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
97 /* Clear external interrupt request */
98 int a = ctrl_inb(INTC_IRR0);
99 a &= ~(1 << (irq - IRQ0_IRQ));
100 ctrl_outb(a, INTC_IRR0);
105 static void end_ipr_irq(unsigned int irq)
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
111 void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
113 disable_irq_nosync(irq);
114 ipr_data[irq].addr = addr;
115 ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
116 ipr_data[irq].priority = priority;
118 irq_desc[irq].handler = &ipr_irq_type;
119 disable_ipr_irq(irq);
122 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
123 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
124 defined(CONFIG_CPU_SUBTYPE_SH7709)
125 static unsigned char pint_map[256];
126 static unsigned long portcr_mask = 0;
128 static void enable_pint_irq(unsigned int irq);
129 static void disable_pint_irq(unsigned int irq);
131 /* shutdown is same as "disable" */
132 #define shutdown_pint_irq disable_pint_irq
134 static void mask_and_ack_pint(unsigned int);
135 static void end_pint_irq(unsigned int irq);
137 static unsigned int startup_pint_irq(unsigned int irq)
139 enable_pint_irq(irq);
140 return 0; /* never anything pending */
143 static struct hw_interrupt_type pint_irq_type = {
153 static void disable_pint_irq(unsigned int irq)
155 unsigned long val, flags;
157 local_irq_save(flags);
158 val = ctrl_inw(INTC_INTER);
159 val &= ~(1 << (irq - PINT_IRQ_BASE));
160 ctrl_outw(val, INTC_INTER); /* disable PINTn */
161 portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
162 local_irq_restore(flags);
165 static void enable_pint_irq(unsigned int irq)
167 unsigned long val, flags;
169 local_irq_save(flags);
170 val = ctrl_inw(INTC_INTER);
171 val |= 1 << (irq - PINT_IRQ_BASE);
172 ctrl_outw(val, INTC_INTER); /* enable PINTn */
173 portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
174 local_irq_restore(flags);
177 static void mask_and_ack_pint(unsigned int irq)
179 disable_pint_irq(irq);
182 static void end_pint_irq(unsigned int irq)
184 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
185 enable_pint_irq(irq);
188 void make_pint_irq(unsigned int irq)
190 disable_irq_nosync(irq);
191 irq_desc[irq].handler = &pint_irq_type;
192 disable_pint_irq(irq);
196 void __init init_IRQ(void)
198 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
199 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
200 defined(CONFIG_CPU_SUBTYPE_SH7709)
204 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
205 make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
206 #if defined(CONFIG_SH_RTC)
207 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
211 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
212 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
213 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
217 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
218 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
219 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
220 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
223 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
224 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
225 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
226 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
227 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
231 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
232 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
233 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
234 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
238 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
239 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
240 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
241 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
244 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
245 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
247 * Initialize the Interrupt Controller (INTC)
248 * registers to their power on values
252 * Enable external irq (INTC IRQ mode).
253 * You should set corresponding bits of PFC to "00"
254 * to enable these interrupts.
256 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
257 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
258 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
259 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
260 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
261 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
262 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
263 make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
264 make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
265 enable_ipr_irq(PINT0_IRQ);
266 enable_ipr_irq(PINT8_IRQ);
268 for(i = 0; i < 16; i++)
269 make_pint_irq(PINT_IRQ_BASE + i);
270 for(i = 0; i < 256; i++)
272 if(i & 1) pint_map[i] = 0;
273 else if(i & 2) pint_map[i] = 1;
274 else if(i & 4) pint_map[i] = 2;
275 else if(i & 8) pint_map[i] = 3;
276 else if(i & 0x10) pint_map[i] = 4;
277 else if(i & 0x20) pint_map[i] = 5;
278 else if(i & 0x40) pint_map[i] = 6;
279 else if(i & 0x80) pint_map[i] = 7;
281 #endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
282 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 || CONFIG_CPU_SUBTYPE_SH7300*/
284 /* Perform the machine specific initialisation */
285 if (sh_mv.mv_init_irq != NULL) {
289 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
290 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
291 int ipr_irq_demux(int irq)
293 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
294 unsigned long creg, dreg, d, sav;
298 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
305 sav = ctrl_inw(creg);
306 ctrl_outw(sav | portcr_mask, creg);
307 d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;
308 ctrl_outw(sav, creg);
309 if(d == 0) return irq;
310 return PINT_IRQ_BASE + pint_map[d];
312 else if(irq == PINT8_IRQ)
314 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
321 sav = ctrl_inw(creg);
322 ctrl_outw(sav | (portcr_mask >> 16), creg);
323 d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;
324 ctrl_outw(sav, creg);
325 if(d == 0) return irq;
326 return PINT_IRQ_BASE + 8 + pint_map[d];