2 * arch/sh/kernel/time.c
4 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
5 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
6 * Copyright (C) 2002, 2003, 2004 Paul Mundt
7 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
9 * Some code taken from i386 version.
10 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 #include <linux/config.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/param.h>
19 #include <linux/string.h>
21 #include <linux/interrupt.h>
22 #include <linux/time.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
25 #include <linux/smp.h>
26 #include <linux/profile.h>
28 #include <asm/processor.h>
29 #include <asm/uaccess.h>
32 #include <asm/delay.h>
33 #include <asm/machvec.h>
40 #include <linux/timex.h>
41 #include <linux/irq.h>
43 #define TMU_TOCR_INIT 0x00
44 #define TMU0_TCR_INIT 0x0020
45 #define TMU_TSTR_INIT 1
47 #define TMU0_TCR_CALIB 0x0000
49 #if defined(CONFIG_CPU_SH3)
50 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
51 #define TMU_TSTR 0xA412FE92 /* Byte access */
53 #define TMU0_TCOR 0xA412FE94 /* Long access */
54 #define TMU0_TCNT 0xA412FE98 /* Long access */
55 #define TMU0_TCR 0xA412FE9C /* Word access */
57 #define TMU1_TCOR 0xA412FEA0 /* Long access */
58 #define TMU1_TCNT 0xA412FEA4 /* Long access */
59 #define TMU1_TCR 0xA412FEA8 /* Word access */
61 #define FRQCR 0xA415FF80
63 #define TMU_TOCR 0xfffffe90 /* Byte access */
64 #define TMU_TSTR 0xfffffe92 /* Byte access */
66 #define TMU0_TCOR 0xfffffe94 /* Long access */
67 #define TMU0_TCNT 0xfffffe98 /* Long access */
68 #define TMU0_TCR 0xfffffe9c /* Word access */
70 #elif defined(CONFIG_CPU_SH4)
71 #define TMU_TOCR 0xffd80000 /* Byte access */
72 #define TMU_TSTR 0xffd80004 /* Byte access */
74 #define TMU0_TCOR 0xffd80008 /* Long access */
75 #define TMU0_TCNT 0xffd8000c /* Long access */
76 #define TMU0_TCR 0xffd80010 /* Word access */
78 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
79 #define CLOCKGEN_MEMCLKCR 0xbb040038
80 #define MEMCLKCR_RATIO_MASK 0x7
81 #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */
82 #endif /* CONFIG_CPU_SH3 or CONFIG_CPU_SH4 */
84 extern unsigned long wall_jiffies;
85 #define TICK_SIZE (tick_nsec / 1000)
86 DEFINE_SPINLOCK(tmu0_lock);
88 u64 jiffies_64 = INITIAL_JIFFIES;
90 EXPORT_SYMBOL(jiffies_64);
92 /* XXX: Can we initialize this in a routine somewhere? Dreamcast doesn't want
93 * these routines anywhere... */
95 void (*rtc_get_time)(struct timespec *) = sh_rtc_gettimeofday;
96 int (*rtc_set_time)(const time_t) = sh_rtc_settimeofday;
98 void (*rtc_get_time)(struct timespec *);
99 int (*rtc_set_time)(const time_t);
102 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
103 static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
105 #if defined(CONFIG_CPU_SH3)
106 static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
107 static int stc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 };
108 #define bfc_divisors stc_multipliers
109 #define bfc_values stc_values
110 static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
111 static int ifc_values[] = { 0, 1, 4, 2, 0, 0, 0, 0 };
112 static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
113 static int pfc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 };
114 #elif defined(CONFIG_CPU_SH4)
115 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
116 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 12, 16 };
117 static int ifc_values[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
118 #define bfc_divisors ifc_divisors /* Same */
119 #define bfc_values ifc_values
120 #define pfc_divisors ifc_divisors /* Same */
121 #define pfc_values ifc_values
123 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
124 static int ifc_values[] = { 0, 1, 2, 3, 0, 4, 0, 5 };
125 #define bfc_divisors ifc_divisors /* Same */
126 #define bfc_values ifc_values
127 static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
128 static int pfc_values[] = { 0, 0, 1, 2, 0, 3, 0, 4 };
131 #error "Unknown ifc/bfc/pfc/stc values for this processor"
135 * Scheduler clock - returns current time in nanosec units.
137 unsigned long long sched_clock(void)
139 return (unsigned long long)jiffies * (1000000000 / HZ);
142 static unsigned long do_gettimeoffset(void)
147 static int count_p = 0x7fffffff; /* for the first call after boot */
148 static unsigned long jiffies_p = 0;
151 * cache volatile jiffies temporarily; we have IRQs turned off.
153 unsigned long jiffies_t;
155 spin_lock_irqsave(&tmu0_lock, flags);
156 /* timer count may underflow right here */
157 count = ctrl_inl(TMU0_TCNT); /* read the latched count */
162 * avoiding timer inconsistencies (they are rare, but they happen)...
163 * there is one kind of problem that must be avoided here:
164 * 1. the timer counter underflows
167 if( jiffies_t == jiffies_p ) {
168 if( count > count_p ) {
171 if(ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
173 * We cannot detect lost timer interrupts ...
174 * well, that's why we call them lost, don't we? :)
175 * [hmm, on the Pentium and Alpha we can ... sort of]
179 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
183 jiffies_p = jiffies_t;
186 spin_unlock_irqrestore(&tmu0_lock, flags);
188 count = ((LATCH-1) - count) * TICK_SIZE;
189 count = (count + LATCH/2) / LATCH;
194 void do_gettimeofday(struct timeval *tv)
197 unsigned long usec, sec;
201 seq = read_seqbegin(&xtime_lock);
202 usec = do_gettimeoffset();
204 lost = jiffies - wall_jiffies;
206 usec += lost * (1000000 / HZ);
209 usec += xtime.tv_nsec / 1000;
210 } while (read_seqretry(&xtime_lock, seq));
212 while (usec >= 1000000) {
221 EXPORT_SYMBOL(do_gettimeofday);
223 int do_settimeofday(struct timespec *tv)
225 time_t wtm_sec, sec = tv->tv_sec;
226 long wtm_nsec, nsec = tv->tv_nsec;
228 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
231 write_seqlock_irq(&xtime_lock);
233 * This is revolting. We need to set "xtime" correctly. However, the
234 * value in this location is the value at the most recent update of
235 * wall time. Discover what correction gettimeofday() would have
236 * made, and then undo it!
238 nsec -= 1000 * (do_gettimeoffset() +
239 (jiffies - wall_jiffies) * (1000000 / HZ));
241 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
242 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
244 set_normalized_timespec(&xtime, sec, nsec);
245 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
247 time_adjust = 0; /* stop active adjtime() */
248 time_status |= STA_UNSYNC;
249 time_maxerror = NTP_PHASE_LIMIT;
250 time_esterror = NTP_PHASE_LIMIT;
251 write_sequnlock_irq(&xtime_lock);
257 EXPORT_SYMBOL(do_settimeofday);
259 /* last time the RTC clock got updated */
260 static long last_rtc_update;
263 * timer_interrupt() needs to keep up the real-time clock,
264 * as well as call the "do_timer()" routine every clocktick
266 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
270 update_process_times(user_mode(regs));
272 profile_tick(CPU_PROFILING, regs);
274 #ifdef CONFIG_HEARTBEAT
275 if (sh_mv.mv_heartbeat != NULL)
276 sh_mv.mv_heartbeat();
280 * If we have an externally synchronized Linux clock, then update
281 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
282 * called as close as possible to 500 ms before the new second starts.
284 if ((time_status & STA_UNSYNC) == 0 &&
285 xtime.tv_sec > last_rtc_update + 660 &&
286 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
287 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
288 if (rtc_set_time(xtime.tv_sec) == 0)
289 last_rtc_update = xtime.tv_sec;
291 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
296 * This is the same as the above, except we _also_ save the current
297 * Time Stamp Counter value at the time of the timer interrupt, so that
298 * we later on can estimate the time of day more exactly.
300 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
302 unsigned long timer_status;
305 timer_status = ctrl_inw(TMU0_TCR);
306 timer_status &= ~0x100;
307 ctrl_outw(timer_status, TMU0_TCR);
310 * Here we are in the timer irq handler. We just have irqs locally
311 * disabled but we don't know if the timer_bh is running on the other
312 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
313 * the irq version of write_lock because as just said we have irq
314 * locally disabled. -arca
316 write_seqlock(&xtime_lock);
317 do_timer_interrupt(irq, NULL, regs);
318 write_sequnlock(&xtime_lock);
324 * Hah! We'll see if this works (switching from usecs to nsecs).
326 static unsigned int __init get_timer_frequency(void)
329 struct timespec ts1, ts2;
330 unsigned long diff_nsec;
331 unsigned long factor;
333 /* Setup the timer: We don't want to generate interrupts, just
334 * have it count down at its natural rate.
336 ctrl_outb(0, TMU_TSTR);
337 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
338 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
340 ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
341 ctrl_outl(0xffffffff, TMU0_TCOR);
342 ctrl_outl(0xffffffff, TMU0_TCNT);
348 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
350 /* actually start the timer */
351 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
355 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
357 freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
358 if (ts2.tv_nsec < ts1.tv_nsec) {
359 ts2.tv_nsec += 1000000000;
363 diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
365 /* this should work well if the RTC has a precision of n Hz, where
366 * n is an integer. I don't think we have to worry about the other
368 factor = (1000000000 + diff_nsec/2) / diff_nsec;
370 if (factor * diff_nsec > 1100000000 ||
371 factor * diff_nsec < 900000000)
372 panic("weird RTC (diff_nsec %ld)", diff_nsec);
374 return freq * factor;
377 void (*board_time_init)(void);
378 void (*board_timer_setup)(struct irqaction *irq);
380 static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ;
382 static int __init sh_pclk_setup(char *str)
386 if (get_option(&str, &freq))
391 __setup("sh_pclk=", sh_pclk_setup);
393 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
395 void get_current_frequency_divisors(unsigned int *ifc, unsigned int *bfc, unsigned int *pfc)
397 unsigned int frqcr = ctrl_inw(FRQCR);
399 #if defined(CONFIG_CPU_SH3)
400 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
401 *ifc = md_table[((frqcr & 0x0070) >> 4)];
402 *bfc = md_table[((frqcr & 0x0700) >> 8)];
403 *pfc = md_table[frqcr & 0x0007];
404 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
405 *bfc = stc_multipliers[(frqcr & 0x0300) >> 8];
406 *ifc = ifc_divisors[(frqcr & 0x0030) >> 4];
407 *pfc = pfc_divisors[frqcr & 0x0003];
411 tmp = (frqcr & 0x8000) >> 13;
412 tmp |= (frqcr & 0x0030) >> 4;
413 *bfc = stc_multipliers[tmp];
414 tmp = (frqcr & 0x4000) >> 12;
415 tmp |= (frqcr & 0x000c) >> 2;
416 *ifc = ifc_divisors[tmp];
417 tmp = (frqcr & 0x2000) >> 11;
418 tmp |= frqcr & 0x0003;
419 *pfc = pfc_divisors[tmp];
421 #elif defined(CONFIG_CPU_SH4)
422 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
423 *ifc = ifc_divisors[(frqcr>> 20) & 0x0007];
424 *bfc = bfc_divisors[(frqcr>> 12) & 0x0007];
425 *pfc = pfc_divisors[frqcr & 0x0007];
427 *ifc = ifc_divisors[(frqcr >> 6) & 0x0007];
428 *bfc = bfc_divisors[(frqcr >> 3) & 0x0007];
429 *pfc = pfc_divisors[frqcr & 0x0007];
435 * This bit of ugliness builds up accessor routines to get at both
436 * the divisors and the physical values.
438 #define _FREQ_TABLE(x) \
439 unsigned int get_##x##_divisor(unsigned int value) \
440 { return x##_divisors[value]; } \
442 unsigned int get_##x##_value(unsigned int divisor) \
443 { return x##_values[(divisor - 1)]; }
449 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
452 * The ST40 divisors are totally different so we set the cpu data
453 * clocks using a different algorithm
455 * I've just plugged this from the 2.4 code
456 * - Alex Bennee <kernel-hacker@bennee.com>
458 #define CCN_PVR_CHIP_SHIFT 24
459 #define CCN_PVR_CHIP_MASK 0xff
460 #define CCN_PVR_CHIP_ST40STB1 0x4
464 unsigned short frqcr;
467 unsigned char multiplier;
468 unsigned char divisor;
472 static struct frqcr_data st40_frqcr_table[] = {
473 { 0x000, {{1,1}, {1,1}, {1,2}}},
474 { 0x002, {{1,1}, {1,1}, {1,4}}},
475 { 0x004, {{1,1}, {1,1}, {1,8}}},
476 { 0x008, {{1,1}, {1,2}, {1,2}}},
477 { 0x00A, {{1,1}, {1,2}, {1,4}}},
478 { 0x00C, {{1,1}, {1,2}, {1,8}}},
479 { 0x011, {{1,1}, {2,3}, {1,6}}},
480 { 0x013, {{1,1}, {2,3}, {1,3}}},
481 { 0x01A, {{1,1}, {1,2}, {1,4}}},
482 { 0x01C, {{1,1}, {1,2}, {1,8}}},
483 { 0x023, {{1,1}, {2,3}, {1,3}}},
484 { 0x02C, {{1,1}, {1,2}, {1,8}}},
485 { 0x048, {{1,2}, {1,2}, {1,4}}},
486 { 0x04A, {{1,2}, {1,2}, {1,6}}},
487 { 0x04C, {{1,2}, {1,2}, {1,8}}},
488 { 0x05A, {{1,2}, {1,3}, {1,6}}},
489 { 0x05C, {{1,2}, {1,3}, {1,6}}},
490 { 0x063, {{1,2}, {1,4}, {1,4}}},
491 { 0x06C, {{1,2}, {1,4}, {1,8}}},
492 { 0x091, {{1,3}, {1,3}, {1,6}}},
493 { 0x093, {{1,3}, {1,3}, {1,6}}},
494 { 0x0A3, {{1,3}, {1,6}, {1,6}}},
495 { 0x0DA, {{1,4}, {1,4}, {1,8}}},
496 { 0x0DC, {{1,4}, {1,4}, {1,8}}},
497 { 0x0EC, {{1,4}, {1,8}, {1,8}}},
498 { 0x123, {{1,4}, {1,4}, {1,8}}},
499 { 0x16C, {{1,4}, {1,8}, {1,8}}},
503 unsigned char multiplier;
504 unsigned char divisor;
507 static struct memclk_data st40_memclk_table[8] = {
518 static void st40_specific_time_init(unsigned int module_clock, unsigned short frqcr)
520 unsigned int cpu_clock, master_clock, bus_clock, memory_clock;
521 struct frqcr_data *d;
523 unsigned long memclkcr;
524 struct memclk_data *e;
526 for (a = 0; a < ARRAY_SIZE(st40_frqcr_table); a++) {
527 d = &st40_frqcr_table[a];
529 if (d->frqcr == (frqcr & 0x1ff))
533 if (a == ARRAY_SIZE(st40_frqcr_table)) {
534 d = st40_frqcr_table;
536 printk("ERROR: Unrecognised FRQCR value (0x%x), "
537 "using default multipliers\n", frqcr);
540 memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR);
541 e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK];
543 printk(KERN_INFO "Clock multipliers: CPU: %d/%d Bus: %d/%d "
544 "Mem: %d/%d Periph: %d/%d\n",
545 d->factor[0].multiplier, d->factor[0].divisor,
546 d->factor[1].multiplier, d->factor[1].divisor,
547 e->multiplier, e->divisor,
548 d->factor[2].multiplier, d->factor[2].divisor);
550 master_clock = module_clock * d->factor[2].divisor
551 / d->factor[2].multiplier;
552 bus_clock = master_clock * d->factor[1].multiplier
553 / d->factor[1].divisor;
554 memory_clock = master_clock * e->multiplier
556 cpu_clock = master_clock * d->factor[0].multiplier
557 / d->factor[0].divisor;
559 current_cpu_data.cpu_clock = cpu_clock;
560 current_cpu_data.master_clock = master_clock;
561 current_cpu_data.bus_clock = bus_clock;
562 current_cpu_data.memory_clock = memory_clock;
563 current_cpu_data.module_clock = module_clock;
567 void __init time_init(void)
569 unsigned int timer_freq = 0;
570 unsigned int ifc, pfc, bfc;
571 unsigned long interval;
572 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
574 unsigned short frqcr;
581 * If we don't have an RTC (such as with the SH7300), don't attempt to
582 * probe the timer frequency. Rely on an either hardcoded peripheral
583 * clock value, or on the sh_pclk command line option. Note that we
584 * still need to have CONFIG_SH_PCLK_FREQ set in order for things like
585 * CLOCK_TICK_RATE to be sane.
587 current_cpu_data.module_clock = sh_pclk_freq;
589 #ifdef CONFIG_SH_PCLK_CALC
590 /* XXX: Switch this over to a more generic test. */
595 * If we've specified a peripheral clock frequency, and we have
596 * an RTC, compare it against the autodetected value. Complain
597 * if there's a mismatch.
599 timer_freq = get_timer_frequency();
600 freq = timer_freq * 4;
602 if (sh_pclk_freq && (sh_pclk_freq/100*99 > freq || sh_pclk_freq/100*101 < freq)) {
603 printk(KERN_NOTICE "Calculated peripheral clock value "
604 "%d differs from sh_pclk value %d, fixing..\n",
606 current_cpu_data.module_clock = freq;
611 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
612 /* XXX: Update ST40 code to use board_time_init() */
613 pvr = ctrl_inl(CCN_PVR);
614 frqcr = ctrl_inw(FRQCR);
615 printk("time.c ST40 Probe: PVR %08lx, FRQCR %04hx\n", pvr, frqcr);
617 if (((pvr >> CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1)
618 st40_specific_time_init(current_cpu_data.module_clock, frqcr);
621 get_current_frequency_divisors(&ifc, &bfc, &pfc);
624 rtc_get_time(&xtime);
626 xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
630 set_normalized_timespec(&wall_to_monotonic,
631 -xtime.tv_sec, -xtime.tv_nsec);
633 if (board_timer_setup) {
634 board_timer_setup(&irq0);
636 setup_irq(TIMER_IRQ, &irq0);
640 * for ST40 chips the current_cpu_data should already be set
641 * so not having valid pfc/bfc/ifc shouldn't be a problem
643 if (!current_cpu_data.master_clock)
644 current_cpu_data.master_clock = current_cpu_data.module_clock * pfc;
645 if (!current_cpu_data.bus_clock)
646 current_cpu_data.bus_clock = current_cpu_data.master_clock / bfc;
647 if (!current_cpu_data.cpu_clock)
648 current_cpu_data.cpu_clock = current_cpu_data.master_clock / ifc;
650 printk("CPU clock: %d.%02dMHz\n",
651 (current_cpu_data.cpu_clock / 1000000),
652 (current_cpu_data.cpu_clock % 1000000)/10000);
653 printk("Bus clock: %d.%02dMHz\n",
654 (current_cpu_data.bus_clock / 1000000),
655 (current_cpu_data.bus_clock % 1000000)/10000);
656 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
657 printk("Memory clock: %d.%02dMHz\n",
658 (current_cpu_data.memory_clock / 1000000),
659 (current_cpu_data.memory_clock % 1000000)/10000);
661 printk("Module clock: %d.%02dMHz\n",
662 (current_cpu_data.module_clock / 1000000),
663 (current_cpu_data.module_clock % 1000000)/10000);
665 interval = (current_cpu_data.module_clock/4 + HZ/2) / HZ;
667 printk("Interval = %ld\n", interval);
670 ctrl_outb(0, TMU_TSTR);
671 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
672 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
674 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
675 ctrl_outl(interval, TMU0_TCOR);
676 ctrl_outl(interval, TMU0_TCNT);
677 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
679 #if defined(CONFIG_SH_KGDB)
681 * Set up kgdb as requested. We do it here because the serial
682 * init uses the timer vars we just set up for figuring baud.