2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * arch/sh64/kernel/time.c
8 * Copyright (C) 2000, 2001 Paolo Alberelli
9 * Copyright (C) 2003, 2004 Paul Mundt
10 * Copyright (C) 2003 Richard Curnow
12 * Original TMU/RTC code taken from sh version.
13 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
14 * Some code taken from i386 version.
15 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
18 #include <linux/config.h>
19 #include <linux/errno.h>
20 #include <linux/rwsem.h>
21 #include <linux/sched.h>
22 #include <linux/kernel.h>
23 #include <linux/param.h>
24 #include <linux/string.h>
26 #include <linux/interrupt.h>
27 #include <linux/time.h>
28 #include <linux/delay.h>
29 #include <linux/init.h>
30 #include <linux/profile.h>
31 #include <linux/smp.h>
33 #include <asm/registers.h> /* required by inline __asm__ stmt. */
35 #include <asm/processor.h>
36 #include <asm/uaccess.h>
39 #include <asm/delay.h>
41 #include <linux/timex.h>
42 #include <linux/irq.h>
43 #include <asm/hardware.h>
45 #define TMU_TOCR_INIT 0x00
46 #define TMU0_TCR_INIT 0x0020
47 #define TMU_TSTR_INIT 1
50 #define RCR1_CF 0x80 /* Carry Flag */
51 #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
52 #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
53 #define RCR1_AF 0x01 /* Alarm Flag */
56 #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
57 #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
58 #define RCR2_RTCEN 0x08 /* ENable RTC */
59 #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
60 #define RCR2_RESET 0x02 /* Reset bit */
61 #define RCR2_START 0x01 /* Start bit */
63 /* Clock, Power and Reset Controller */
64 #define CPRC_BLOCK_OFF 0x01010000
65 #define CPRC_BASE PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF
67 #define FRQCR (cprc_base+0x0)
68 #define WTCSR (cprc_base+0x0018)
69 #define STBCR (cprc_base+0x0030)
71 /* Time Management Unit */
72 #define TMU_BLOCK_OFF 0x01020000
73 #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
74 #define TMU0_BASE tmu_base + 0x8 + (0xc * 0x0)
75 #define TMU1_BASE tmu_base + 0x8 + (0xc * 0x1)
76 #define TMU2_BASE tmu_base + 0x8 + (0xc * 0x2)
78 #define TMU_TOCR tmu_base+0x0 /* Byte access */
79 #define TMU_TSTR tmu_base+0x4 /* Byte access */
81 #define TMU0_TCOR TMU0_BASE+0x0 /* Long access */
82 #define TMU0_TCNT TMU0_BASE+0x4 /* Long access */
83 #define TMU0_TCR TMU0_BASE+0x8 /* Word access */
86 #define RTC_BLOCK_OFF 0x01040000
87 #define RTC_BASE PHYS_PERIPHERAL_BLOCK + RTC_BLOCK_OFF
89 #define R64CNT rtc_base+0x00
90 #define RSECCNT rtc_base+0x04
91 #define RMINCNT rtc_base+0x08
92 #define RHRCNT rtc_base+0x0c
93 #define RWKCNT rtc_base+0x10
94 #define RDAYCNT rtc_base+0x14
95 #define RMONCNT rtc_base+0x18
96 #define RYRCNT rtc_base+0x1c /* 16bit */
97 #define RSECAR rtc_base+0x20
98 #define RMINAR rtc_base+0x24
99 #define RHRAR rtc_base+0x28
100 #define RWKAR rtc_base+0x2c
101 #define RDAYAR rtc_base+0x30
102 #define RMONAR rtc_base+0x34
103 #define RCR1 rtc_base+0x38
104 #define RCR2 rtc_base+0x3c
107 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
111 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
114 #define TICK_SIZE (tick_nsec / 1000)
116 extern unsigned long wall_jiffies;
118 u64 jiffies_64 = INITIAL_JIFFIES;
120 static unsigned long tmu_base, rtc_base;
121 unsigned long cprc_base;
123 /* Variables to allow interpolation of time of day to resolution better than a
126 /* This is effectively protected by xtime_lock */
127 static unsigned long ctc_last_interrupt;
128 static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
130 #define CTC_JIFFY_SCALE_SHIFT 40
132 /* 2**CTC_JIFFY_SCALE_SHIFT / ctc_ticks_per_jiffy */
133 static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
135 /* Estimate number of microseconds that have elapsed since the last timer tick,
136 by scaling the delta that has occured in the CTC register.
138 WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
139 the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this
140 in mind if enabling SLEEP_WORKS in process.c. In that case, this algorithm
141 probably needs to use TMU.TCNT0 instead. This will work even if the CPU is
142 sleeping, though will be coarser.
144 FIXME : What if usecs_per_tick is moving around too much, e.g. if an adjtime
145 is running or if the freq or tick arguments of adjtimex are modified after
146 we have calibrated the scaling factor? This will result in either a jump at
147 the end of a tick period, or a wrap backwards at the start of the next one,
148 if the application is reading the time of day often enough. I think we
149 ought to do better than this. For this reason, usecs_per_jiffy is left
150 separated out in the calculation below. This allows some future hook into
151 the adjtime-related stuff in kernel/timer.c to remove this hazard.
155 static unsigned long usecs_since_tick(void)
157 unsigned long long current_ctc;
158 long ctc_ticks_since_interrupt;
159 unsigned long long ull_ctc_ticks_since_interrupt;
160 unsigned long result;
162 unsigned long long mul1_out;
163 unsigned long long mul1_out_high;
164 unsigned long long mul2_out_low, mul2_out_high;
166 /* Read CTC register */
167 asm ("getcon cr62, %0" : "=r" (current_ctc));
168 /* Note, the CTC counts down on each CPU clock, not up.
169 Note(2), use long type to get correct wraparound arithmetic when
170 the counter crosses zero. */
171 ctc_ticks_since_interrupt = (long) ctc_last_interrupt - (long) current_ctc;
172 ull_ctc_ticks_since_interrupt = (unsigned long long) ctc_ticks_since_interrupt;
174 /* Inline assembly to do 32x32x32->64 multiplier */
175 asm volatile ("mulu.l %1, %2, %0" :
177 "r" (ull_ctc_ticks_since_interrupt), "r" (usecs_per_jiffy));
179 mul1_out_high = mul1_out >> 32;
181 asm volatile ("mulu.l %1, %2, %0" :
182 "=r" (mul2_out_low) :
183 "r" (mul1_out), "r" (scaled_recip_ctc_ticks_per_jiffy));
186 asm volatile ("mulu.l %1, %2, %0" :
187 "=r" (mul2_out_high) :
188 "r" (mul1_out_high), "r" (scaled_recip_ctc_ticks_per_jiffy));
191 result = (unsigned long) (((mul2_out_high << 32) + mul2_out_low) >> CTC_JIFFY_SCALE_SHIFT);
196 void do_gettimeofday(struct timeval *tv)
200 unsigned long usec, sec;
203 seq = read_seqbegin_irqsave(&xtime_lock, flags);
204 usec = usecs_since_tick();
206 unsigned long lost = jiffies - wall_jiffies;
209 usec += lost * (1000000 / HZ);
213 usec += xtime.tv_nsec / 1000;
214 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
216 while (usec >= 1000000) {
225 int do_settimeofday(struct timespec *tv)
227 time_t wtm_sec, sec = tv->tv_sec;
228 long wtm_nsec, nsec = tv->tv_nsec;
230 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
233 write_seqlock_irq(&xtime_lock);
235 * This is revolting. We need to set "xtime" correctly. However, the
236 * value in this location is the value at the most recent update of
237 * wall time. Discover what correction gettimeofday() would have
238 * made, and then undo it!
240 nsec -= 1000 * (usecs_since_tick() +
241 (jiffies - wall_jiffies) * (1000000 / HZ));
243 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
244 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
246 set_normalized_timespec(&xtime, sec, nsec);
247 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
249 time_adjust = 0; /* stop active adjtime() */
250 time_status |= STA_UNSYNC;
251 time_maxerror = NTP_PHASE_LIMIT;
252 time_esterror = NTP_PHASE_LIMIT;
253 write_sequnlock_irq(&xtime_lock);
259 static int set_rtc_time(unsigned long nowtime)
262 int real_seconds, real_minutes, cmos_minutes;
264 ctrl_outb(RCR2_RESET, RCR2); /* Reset pre-scaler & stop RTC */
266 cmos_minutes = ctrl_inb(RMINCNT);
267 BCD_TO_BIN(cmos_minutes);
270 * since we're only adjusting minutes and seconds,
271 * don't interfere with hour overflow. This avoids
272 * messing with unknown time zones but requires your
273 * RTC not to be off by more than 15 minutes
275 real_seconds = nowtime % 60;
276 real_minutes = nowtime / 60;
277 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
278 real_minutes += 30; /* correct for half hour time zone */
281 if (abs(real_minutes - cmos_minutes) < 30) {
282 BIN_TO_BCD(real_seconds);
283 BIN_TO_BCD(real_minutes);
284 ctrl_outb(real_seconds, RSECCNT);
285 ctrl_outb(real_minutes, RMINCNT);
288 "set_rtc_time: can't update from %d to %d\n",
289 cmos_minutes, real_minutes);
293 ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2); /* Start RTC */
298 /* last time the RTC clock got updated */
299 static long last_rtc_update = 0;
302 * timer_interrupt() needs to keep up the real-time clock,
303 * as well as call the "do_timer()" routine every clocktick
305 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
307 unsigned long long current_ctc;
308 asm ("getcon cr62, %0" : "=r" (current_ctc));
309 ctc_last_interrupt = (unsigned long) current_ctc;
313 update_process_times(user_mode(regs));
315 profile_tick(CPU_PROFILING, regs);
317 #ifdef CONFIG_HEARTBEAT
319 extern void heartbeat(void);
326 * If we have an externally synchronized Linux clock, then update
327 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
328 * called as close as possible to 500 ms before the new second starts.
330 if ((time_status & STA_UNSYNC) == 0 &&
331 xtime.tv_sec > last_rtc_update + 660 &&
332 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
333 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
334 if (set_rtc_time(xtime.tv_sec) == 0)
335 last_rtc_update = xtime.tv_sec;
337 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
342 * This is the same as the above, except we _also_ save the current
343 * Time Stamp Counter value at the time of the timer interrupt, so that
344 * we later on can estimate the time of day more exactly.
346 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
348 unsigned long timer_status;
351 timer_status = ctrl_inw(TMU0_TCR);
352 timer_status &= ~0x100;
353 ctrl_outw(timer_status, TMU0_TCR);
356 * Here we are in the timer irq handler. We just have irqs locally
357 * disabled but we don't know if the timer_bh is running on the other
358 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
359 * the irq version of write_lock because as just said we have irq
360 * locally disabled. -arca
362 write_lock(&xtime_lock);
363 do_timer_interrupt(irq, NULL, regs);
364 write_unlock(&xtime_lock);
369 static unsigned long get_rtc_time(void)
371 unsigned int sec, min, hr, wk, day, mon, yr, yr100;
375 ctrl_outb(0, RCR1); /* Clear CF-bit */
376 sec = ctrl_inb(RSECCNT);
377 min = ctrl_inb(RMINCNT);
378 hr = ctrl_inb(RHRCNT);
379 wk = ctrl_inb(RWKCNT);
380 day = ctrl_inb(RDAYCNT);
381 mon = ctrl_inb(RMONCNT);
382 yr = ctrl_inw(RYRCNT);
385 } while ((ctrl_inb(RCR1) & RCR1_CF) != 0);
395 if (yr > 99 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
396 hr > 23 || min > 59 || sec > 59) {
398 "SH RTC: invalid value, resetting to 1 Jan 2000\n");
399 ctrl_outb(RCR2_RESET, RCR2); /* Reset & Stop */
400 ctrl_outb(0, RSECCNT);
401 ctrl_outb(0, RMINCNT);
402 ctrl_outb(0, RHRCNT);
403 ctrl_outb(6, RWKCNT);
404 ctrl_outb(1, RDAYCNT);
405 ctrl_outb(1, RMONCNT);
406 ctrl_outw(0x2000, RYRCNT);
407 ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2); /* Start */
411 return mktime(yr100 * 100 + yr, mon, day, hr, min, sec);
414 static __init unsigned int get_cpu_hz(void)
417 unsigned long __dummy;
418 unsigned long ctc_val_init, ctc_val;
421 ** Regardless the toolchain, force the compiler to use the
422 ** arbitrary register r3 as a clock tick counter.
423 ** NOTE: r3 must be in accordance with rtc_interrupt()
425 register unsigned long long __rtc_irq_flag __asm__ ("r3");
428 do {} while (ctrl_inb(R64CNT) != 0);
429 ctrl_outb(RCR1_CIE, RCR1); /* Enable carry interrupt */
432 * r3 is arbitrary. CDC does not support "=z".
434 ctc_val_init = 0xffffffff;
435 ctc_val = ctc_val_init;
437 asm volatile("gettr tr0, %1\n\t"
438 "putcon %0, " __CTC "\n\t"
439 "and %2, r63, %2\n\t"
441 "beq/l %2, r63, tr0\n\t"
443 "getcon " __CTC ", %0\n\t"
444 : "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag)
449 * CPU clock = 4 stages * loop
453 * (if) pipe line stole
459 * CPU clock = 6 stages * loop
464 * Use CTC register to count. This approach returns the right value
465 * even if the I-cache is disabled (e.g. whilst debugging.)
469 count = ctc_val_init - ctc_val; /* CTC counts down */
471 #if defined (CONFIG_SH_SIMULATOR)
473 * Let's pretend we are a 5MHz SH-5 to avoid a too
474 * little timer interval. Also to keep delay
475 * calibration within a reasonable time.
480 * This really is count by the number of clock cycles
481 * by the ratio between a complete R64CNT
482 * wrap-around (128) and CUI interrupt being raised (64).
488 static irqreturn_t rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
490 ctrl_outb(0, RCR1); /* Disable Carry Interrupts */
491 regs->regs[3] = 1; /* Using r3 */
496 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
497 static struct irqaction irq1 = { rtc_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "rtc", NULL, NULL};
499 void __init time_init(void)
501 unsigned int cpu_clock, master_clock, bus_clock, module_clock;
502 unsigned long interval;
503 unsigned long frqcr, ifc, pfc;
504 static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
505 #define bfc_table ifc_table /* Same */
506 #define pfc_table ifc_table /* Same */
508 tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
510 panic("Unable to remap TMU\n");
513 rtc_base = onchip_remap(RTC_BASE, 1024, "RTC");
515 panic("Unable to remap RTC\n");
518 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
520 panic("Unable to remap CPRC\n");
523 xtime.tv_sec = get_rtc_time();
526 setup_irq(TIMER_IRQ, &irq0);
527 setup_irq(RTC_IRQ, &irq1);
529 /* Check how fast it is.. */
530 cpu_clock = get_cpu_hz();
532 /* Note careful order of operations to maintain reasonable precision and avoid overflow. */
533 scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ));
535 disable_irq(RTC_IRQ);
537 printk("CPU clock: %d.%02dMHz\n",
538 (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
541 frqcr = ctrl_inl(FRQCR);
542 ifc = ifc_table[(frqcr>> 6) & 0x0007];
543 bfc = bfc_table[(frqcr>> 3) & 0x0007];
544 pfc = pfc_table[(frqcr>> 12) & 0x0007];
545 master_clock = cpu_clock * ifc;
546 bus_clock = master_clock/bfc;
549 printk("Bus clock: %d.%02dMHz\n",
550 (bus_clock/1000000), (bus_clock % 1000000)/10000);
551 module_clock = master_clock/pfc;
552 printk("Module clock: %d.%02dMHz\n",
553 (module_clock/1000000), (module_clock % 1000000)/10000);
554 interval = (module_clock/(HZ*4));
556 printk("Interval = %ld\n", interval);
558 current_cpu_data.cpu_clock = cpu_clock;
559 current_cpu_data.master_clock = master_clock;
560 current_cpu_data.bus_clock = bus_clock;
561 current_cpu_data.module_clock = module_clock;
564 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
565 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
566 ctrl_outl(interval, TMU0_TCOR);
567 ctrl_outl(interval, TMU0_TCNT);
568 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
571 void enter_deep_standby(void)
573 /* Disable watchdog timer */
574 ctrl_outl(0xa5000000, WTCSR);
575 /* Configure deep standby on sleep */
576 ctrl_outl(0x03, STBCR);
578 #ifdef CONFIG_SH_ALPHANUMERIC
580 extern void mach_alphanum(int position, unsigned char value);
581 extern void mach_alphanum_brightness(int setting);
582 char halted[] = "Halted. ";
584 mach_alphanum_brightness(6); /* dimmest setting above off */
585 for (i=0; i<8; i++) {
586 mach_alphanum(i, halted[i]);
588 asm __volatile__ ("synco");
592 asm __volatile__ ("sleep");
593 asm __volatile__ ("synci");
594 asm __volatile__ ("nop");
595 asm __volatile__ ("nop");
596 asm __volatile__ ("nop");
597 asm __volatile__ ("nop");
598 panic("Unexpected wakeup!\n");
602 * Scheduler clock - returns current time in nanosec units.
604 unsigned long long sched_clock(void)
606 return (unsigned long long)jiffies * (1000000000 / HZ);