arch/sh64/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * arch/sh64/kernel/traps.c
   7  *
   8  * Copyright (C) 2000, 2001  Paolo Alberelli
   9  * Copyright (C) 2003, 2004  Paul Mundt
  10  * Copyright (C) 2003, 2004  Richard Curnow
  11  *
  12  */
  13
  14 /*
  15  * 'Traps.c' handles hardware traps and faults after we have saved some
  16  * state in 'entry.S'.
  17  */
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/ptrace.h>
  23 #include <linux/timer.h>
  24 #include <linux/mm.h>
  25 #include <linux/smp.h>
  26 #include <linux/smp_lock.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/kallsyms.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/sysctl.h>
  33
  34 #include <asm/system.h>
  35 #include <asm/uaccess.h>
  36 #include <asm/io.h>
  37 #include <asm/atomic.h>
  38 #include <asm/processor.h>
  39 #include <asm/pgtable.h>
  40
  41 #undef DEBUG_EXCEPTION
  42 #ifdef DEBUG_EXCEPTION
  43 /* implemented in ../lib/dbg.c */
  44 extern void show_excp_regs(char *fname, int trapnr, int signr,
  45                            struct pt_regs *regs);
  46 #else
  47 #define show_excp_regs(a, b, c, d)
  48 #endif
  49
  50 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
  51                 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
  52
  53 #define DO_ERROR(trapnr, signr, str, name, tsk) \
  54 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
  55 { \
  56         do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
  57 }
  58
  59 spinlock_t die_lock;
  60
  61 void die(const char * str, struct pt_regs * regs, long err)
  62 {
  63         console_verbose();
  64         spin_lock_irq(&die_lock);
  65         printk("%s: %lx\n", str, (err & 0xffffff));
  66         show_regs(regs);
  67         spin_unlock_irq(&die_lock);
  68         do_exit(SIGSEGV);
  69 }
  70
  71 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
  72 {
  73         if (!user_mode(regs))
  74                 die(str, regs, err);
  75 }
  76
  77 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
  78 {
  79         if (!user_mode(regs)) {
  80                 const struct exception_table_entry *fixup;
  81                 fixup = search_exception_tables(regs->pc);
  82                 if (fixup) {
  83                         regs->pc = fixup->fixup;
  84                         return;
  85                 }
  86                 die(str, regs, err);
  87         }
  88 }
  89
  90 DO_ERROR(13, SIGILL,  "illegal slot instruction", illegal_slot_inst, current)
  91 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
  92
  93
  94 /* Implement misaligned load/store handling for kernel (and optionally for user
  95    mode too).  Limitation : only SHmedia mode code is handled - there is no
  96    handling at all for misaligned accesses occurring in SHcompact code yet. */
  97
  98 static int misaligned_fixup(struct pt_regs *regs);
  99
 100 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
 101 {
 102         if (misaligned_fixup(regs) < 0) {
 103                 do_unhandled_exception(7, SIGSEGV, "address error(load)",
 104                                 "do_address_error_load",
 105                                 error_code, regs, current);
 106         }
 107         return;
 108 }
 109
 110 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
 111 {
 112         if (misaligned_fixup(regs) < 0) {
 113                 do_unhandled_exception(8, SIGSEGV, "address error(store)",
 114                                 "do_address_error_store",
 115                                 error_code, regs, current);
 116         }
 117         return;
 118 }
 119
 120 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
 121
 122 #define OPCODE_INVALID      0
 123 #define OPCODE_USER_VALID   1
 124 #define OPCODE_PRIV_VALID   2
 125
 126 /* getcon/putcon - requires checking which control register is referenced. */
 127 #define OPCODE_CTRL_REG     3
 128
 129 /* Table of valid opcodes for SHmedia mode.
 130    Form a 10-bit value by concatenating the major/minor opcodes i.e.
 131    opcode[31:26,20:16].  The 6 MSBs of this value index into the following
 132    array.  The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
 133    LSBs==4'b0000 etc). */
 134 static unsigned long shmedia_opcode_table[64] = {
 135         0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
 136         0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
 137         0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
 138         0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
 139         0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 140         0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 141         0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 142         0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
 143 };
 144
 145 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
 146 {
 147         /* Workaround SH5-101 cut2 silicon defect #2815 :
 148            in some situations, inter-mode branches from SHcompact -> SHmedia
 149            which should take ITLBMISS or EXECPROT exceptions at the target
 150            falsely take RESINST at the target instead. */
 151
 152         unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
 153         unsigned long pc, aligned_pc;
 154         int get_user_error;
 155         int trapnr = 12;
 156         int signr = SIGILL;
 157         char *exception_name = "reserved_instruction";
 158
 159         pc = regs->pc;
 160         if ((pc & 3) == 1) {
 161                 /* SHmedia : check for defect.  This requires executable vmas
 162                    to be readable too. */
 163                 aligned_pc = pc & ~3;
 164                 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
 165                         get_user_error = -EFAULT;
 166                 } else {
 167                         get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
 168                 }
 169                 if (get_user_error >= 0) {
 170                         unsigned long index, shift;
 171                         unsigned long major, minor, combined;
 172                         unsigned long reserved_field;
 173                         reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
 174                         major = (opcode >> 26) & 0x3f;
 175                         minor = (opcode >> 16) & 0xf;
 176                         combined = (major << 4) | minor;
 177                         index = major;
 178                         shift = minor << 1;
 179                         if (reserved_field == 0) {
 180                                 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
 181                                 switch (opcode_state) {
 182                                         case OPCODE_INVALID:
 183                                                 /* Trap. */
 184                                                 break;
 185                                         case OPCODE_USER_VALID:
 186                                                 /* Restart the instruction : the branch to the instruction will now be from an RTE
 187                                                    not from SHcompact so the silicon defect won't be triggered. */
 188                                                 return;
 189                                         case OPCODE_PRIV_VALID:
 190                                                 if (!user_mode(regs)) {
 191                                                         /* Should only ever get here if a module has
 192                                                            SHcompact code inside it.  If so, the same fix up is needed. */
 193                                                         return; /* same reason */
 194                                                 }
 195                                                 /* Otherwise, user mode trying to execute a privileged instruction -
 196                                                    fall through to trap. */
 197                                                 break;
 198                                         case OPCODE_CTRL_REG:
 199                                                 /* If in privileged mode, return as above. */
 200                                                 if (!user_mode(regs)) return;
 201                                                 /* In user mode ... */
 202                                                 if (combined == 0x9f) { /* GETCON */
 203                                                         unsigned long regno = (opcode >> 20) & 0x3f;
 204                                                         if (regno >= 62) {
 205                                                                 return;
 206                                                         }
 207                                                         /* Otherwise, reserved or privileged control register, => trap */
 208                                                 } else if (combined == 0x1bf) { /* PUTCON */
 209                                                         unsigned long regno = (opcode >> 4) & 0x3f;
 210                                                         if (regno >= 62) {
 211                                                                 return;
 212                                                         }
 213                                                         /* Otherwise, reserved or privileged control register, => trap */
 214                                                 } else {
 215                                                         /* Trap */
 216                                                 }
 217                                                 break;
 218                                         default:
 219                                                 /* Fall through to trap. */
 220                                                 break;
 221                                 }
 222                         }
 223                         /* fall through to normal resinst processing */
 224                 } else {
 225                         /* Error trying to read opcode.  This typically means a
 226                            real fault, not a RESINST any more.  So change the
 227                            codes. */
 228                         trapnr = 87;
 229                         exception_name = "address error (exec)";
 230                         signr = SIGSEGV;
 231                 }
 232         }
 233
 234         do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
 235 }
 236
 237 #else /* CONFIG_SH64_ID2815_WORKAROUND */
 238
 239 /* If the workaround isn't needed, this is just a straightforward reserved
 240    instruction */
 241 DO_ERROR(12, SIGILL,  "reserved instruction", reserved_inst, current)
 242
 243 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
 244
 245
 246 #include <asm/system.h>
 247
 248 /* Called with interrupts disabled */
 249 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
 250 {
 251         PLS();
 252         show_excp_regs(__FUNCTION__, -1, -1, regs);
 253         die_if_kernel("exception", regs, ex);
 254 }
 255
 256 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
 257 {
 258         /* Syscall debug */
 259         printk("System call ID error: [0x1#args:8 #syscall:16  0x%lx]\n", scId);
 260
 261         die_if_kernel("unknown trapa", regs, scId);
 262
 263         return -ENOSYS;
 264 }
 265
 266 void show_stack(struct task_struct *tsk, unsigned long *sp)
 267 {
 268 #ifdef CONFIG_KALLSYMS
 269         extern void sh64_unwind(struct pt_regs *regs);
 270         struct pt_regs *regs;
 271
 272         regs = tsk ? tsk->thread.kregs : NULL;
 273
 274         sh64_unwind(regs);
 275 #else
 276         printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
 277 #endif
 278 }
 279
 280 void show_task(unsigned long *sp)
 281 {
 282         show_stack(NULL, sp);
 283 }
 284
 285 void dump_stack(void)
 286 {
 287         show_task(NULL);
 288 }
 289
 290 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
 291                 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
 292 {
 293         show_excp_regs(fn_name, trapnr, signr, regs);
 294         tsk->thread.error_code = error_code;
 295         tsk->thread.trap_no = trapnr;
 296
 297         if (user_mode(regs))
 298                 force_sig(signr, tsk);
 299
 300         die_if_no_fixup(str, regs, error_code);
 301 }
 302
 303 static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
 304 {
 305         int get_user_error;
 306         unsigned long aligned_pc;
 307         unsigned long opcode;
 308
 309         if ((pc & 3) == 1) {
 310                 /* SHmedia */
 311                 aligned_pc = pc & ~3;
 312                 if (from_user_mode) {
 313                         if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
 314                                 get_user_error = -EFAULT;
 315                         } else {
 316                                 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
 317                                 *result_opcode = opcode;
 318                         }
 319                         return get_user_error;
 320                 } else {
 321                         /* If the fault was in the kernel, we can either read
 322                          * this directly, or if not, we fault.
 323                         */
 324                         *result_opcode = *(unsigned long *) aligned_pc;
 325                         return 0;
 326                 }
 327         } else if ((pc & 1) == 0) {
 328                 /* SHcompact */
 329                 /* TODO : provide handling for this.  We don't really support
 330                    user-mode SHcompact yet, and for a kernel fault, this would
 331                    have to come from a module built for SHcompact.  */
 332                 return -EFAULT;
 333         } else {
 334                 /* misaligned */
 335                 return -EFAULT;
 336         }
 337 }
 338
 339 static int address_is_sign_extended(__u64 a)
 340 {
 341         __u64 b;
 342 #if (NEFF == 32)
 343         b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
 344         return (b == a) ? 1 : 0;
 345 #else
 346 #error "Sign extend check only works for NEFF==32"
 347 #endif
 348 }
 349
 350 static int generate_and_check_address(struct pt_regs *regs,
 351                                       __u32 opcode,
 352                                       int displacement_not_indexed,
 353                                       int width_shift,
 354                                       __u64 *address)
 355 {
 356         /* return -1 for fault, 0 for OK */
 357
 358         __u64 base_address, addr;
 359         int basereg;
 360
 361         basereg = (opcode >> 20) & 0x3f;
 362         base_address = regs->regs[basereg];
 363         if (displacement_not_indexed) {
 364                 __s64 displacement;
 365                 displacement = (opcode >> 10) & 0x3ff;
 366                 displacement = ((displacement << 54) >> 54); /* sign extend */
 367                 addr = (__u64)((__s64)base_address + (displacement << width_shift));
 368         } else {
 369                 __u64 offset;
 370                 int offsetreg;
 371                 offsetreg = (opcode >> 10) & 0x3f;
 372                 offset = regs->regs[offsetreg];
 373                 addr = base_address + offset;
 374         }
 375
 376         /* Check sign extended */
 377         if (!address_is_sign_extended(addr)) {
 378                 return -1;
 379         }
 380
 381 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 382         /* Check accessible.  For misaligned access in the kernel, assume the
 383            address is always accessible (and if not, just fault when the
 384            load/store gets done.) */
 385         if (user_mode(regs)) {
 386                 if (addr >= TASK_SIZE) {
 387                         return -1;
 388                 }
 389                 /* Do access_ok check later - it depends on whether it's a load or a store. */
 390         }
 391 #endif
 392
 393         *address = addr;
 394         return 0;
 395 }
 396
 397 /* Default value as for sh */
 398 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 399 static int user_mode_unaligned_fixup_count = 10;
 400 static int user_mode_unaligned_fixup_enable = 1;
 401 #endif
 402
 403 static int kernel_mode_unaligned_fixup_count = 32;
 404
 405 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
 406 {
 407         unsigned short x;
 408         unsigned char *p, *q;
 409         p = (unsigned char *) (int) address;
 410         q = (unsigned char *) &x;
 411         q[0] = p[0];
 412         q[1] = p[1];
 413
 414         if (do_sign_extend) {
 415                 *result = (__u64)(__s64) *(short *) &x;
 416         } else {
 417                 *result = (__u64) x;
 418         }
 419 }
 420
 421 static void misaligned_kernel_word_store(__u64 address, __u64 value)
 422 {
 423         unsigned short x;
 424         unsigned char *p, *q;
 425         p = (unsigned char *) (int) address;
 426         q = (unsigned char *) &x;
 427
 428         x = (__u16) value;
 429         p[0] = q[0];
 430         p[1] = q[1];
 431 }
 432
 433 static int misaligned_load(struct pt_regs *regs,
 434                            __u32 opcode,
 435                            int displacement_not_indexed,
 436                            int width_shift,
 437                            int do_sign_extend)
 438 {
 439         /* Return -1 for a fault, 0 for OK */
 440         int error;
 441         int destreg;
 442         __u64 address;
 443
 444         error = generate_and_check_address(regs, opcode,
 445                         displacement_not_indexed, width_shift, &address);
 446         if (error < 0) {
 447                 return error;
 448         }
 449
 450         destreg = (opcode >> 4) & 0x3f;
 451 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 452         if (user_mode(regs)) {
 453                 __u64 buffer;
 454
 455                 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
 456                         return -1;
 457                 }
 458
 459                 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
 460                         return -1; /* fault */
 461                 }
 462                 switch (width_shift) {
 463                 case 1:
 464                         if (do_sign_extend) {
 465                                 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
 466                         } else {
 467                                 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
 468                         }
 469                         break;
 470                 case 2:
 471                         regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
 472                         break;
 473                 case 3:
 474                         regs->regs[destreg] = buffer;
 475                         break;
 476                 default:
 477                         printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
 478                                 width_shift, (unsigned long) regs->pc);
 479                         break;
 480                 }
 481         } else
 482 #endif
 483         {
 484                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
 485                 __u64 lo, hi;
 486
 487                 switch (width_shift) {
 488                 case 1:
 489                         misaligned_kernel_word_load(address, do_sign_extend, &regs->regs[destreg]);
 490                         break;
 491                 case 2:
 492                         asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
 493                         asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
 494                         regs->regs[destreg] = lo | hi;
 495                         break;
 496                 case 3:
 497                         asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
 498                         asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
 499                         regs->regs[destreg] = lo | hi;
 500                         break;
 501
 502                 default:
 503                         printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
 504                                 width_shift, (unsigned long) regs->pc);
 505                         break;
 506                 }
 507         }
 508
 509         return 0;
 510
 511 }
 512
 513 static int misaligned_store(struct pt_regs *regs,
 514                             __u32 opcode,
 515                             int displacement_not_indexed,
 516                             int width_shift)
 517 {
 518         /* Return -1 for a fault, 0 for OK */
 519         int error;
 520         int srcreg;
 521         __u64 address;
 522
 523         error = generate_and_check_address(regs, opcode,
 524                         displacement_not_indexed, width_shift, &address);
 525         if (error < 0) {
 526                 return error;
 527         }
 528
 529         srcreg = (opcode >> 4) & 0x3f;
 530 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 531         if (user_mode(regs)) {
 532                 __u64 buffer;
 533
 534                 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
 535                         return -1;
 536                 }
 537
 538                 switch (width_shift) {
 539                 case 1:
 540                         *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
 541                         break;
 542                 case 2:
 543                         *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
 544                         break;
 545                 case 3:
 546                         buffer = regs->regs[srcreg];
 547                         break;
 548                 default:
 549                         printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
 550                                 width_shift, (unsigned long) regs->pc);
 551                         break;
 552                 }
 553
 554                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
 555                         return -1; /* fault */
 556                 }
 557         } else
 558 #endif
 559         {
 560                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
 561                 __u64 val = regs->regs[srcreg];
 562
 563                 switch (width_shift) {
 564                 case 1:
 565                         misaligned_kernel_word_store(address, val);
 566                         break;
 567                 case 2:
 568                         asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
 569                         asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
 570                         break;
 571                 case 3:
 572                         asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
 573                         asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
 574                         break;
 575
 576                 default:
 577                         printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
 578                                 width_shift, (unsigned long) regs->pc);
 579                         break;
 580                 }
 581         }
 582
 583         return 0;
 584
 585 }
 586
 587 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 588 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
 589    error. */
 590 static int misaligned_fpu_load(struct pt_regs *regs,
 591                            __u32 opcode,
 592                            int displacement_not_indexed,
 593                            int width_shift,
 594                            int do_paired_load)
 595 {
 596         /* Return -1 for a fault, 0 for OK */
 597         int error;
 598         int destreg;
 599         __u64 address;
 600
 601         error = generate_and_check_address(regs, opcode,
 602                         displacement_not_indexed, width_shift, &address);
 603         if (error < 0) {
 604                 return error;
 605         }
 606
 607         destreg = (opcode >> 4) & 0x3f;
 608         if (user_mode(regs)) {
 609                 __u64 buffer;
 610                 __u32 buflo, bufhi;
 611
 612                 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
 613                         return -1;
 614                 }
 615
 616                 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
 617                         return -1; /* fault */
 618                 }
 619                 /* 'current' may be the current owner of the FPU state, so
 620                    context switch the registers into memory so they can be
 621                    indexed by register number. */
 622                 if (last_task_used_math == current) {
 623                         grab_fpu();
 624                         fpsave(&current->thread.fpu.hard);
 625                         release_fpu();
 626                         last_task_used_math = NULL;
 627                         regs->sr |= SR_FD;
 628                 }
 629
 630                 buflo = *(__u32*) &buffer;
 631                 bufhi = *(1 + (__u32*) &buffer);
 632
 633                 switch (width_shift) {
 634                 case 2:
 635                         current->thread.fpu.hard.fp_regs[destreg] = buflo;
 636                         break;
 637                 case 3:
 638                         if (do_paired_load) {
 639                                 current->thread.fpu.hard.fp_regs[destreg] = buflo;
 640                                 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
 641                         } else {
 642 #if defined(CONFIG_LITTLE_ENDIAN)
 643                                 current->thread.fpu.hard.fp_regs[destreg] = bufhi;
 644                                 current->thread.fpu.hard.fp_regs[destreg+1] = buflo;
 645 #else
 646                                 current->thread.fpu.hard.fp_regs[destreg] = buflo;
 647                                 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
 648 #endif
 649                         }
 650                         break;
 651                 default:
 652                         printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
 653                                 width_shift, (unsigned long) regs->pc);
 654                         break;
 655                 }
 656                 return 0;
 657         } else {
 658                 die ("Misaligned FPU load inside kernel", regs, 0);
 659                 return -1;
 660         }
 661
 662
 663 }
 664
 665 static int misaligned_fpu_store(struct pt_regs *regs,
 666                            __u32 opcode,
 667                            int displacement_not_indexed,
 668                            int width_shift,
 669                            int do_paired_load)
 670 {
 671         /* Return -1 for a fault, 0 for OK */
 672         int error;
 673         int srcreg;
 674         __u64 address;
 675
 676         error = generate_and_check_address(regs, opcode,
 677                         displacement_not_indexed, width_shift, &address);
 678         if (error < 0) {
 679                 return error;
 680         }
 681
 682         srcreg = (opcode >> 4) & 0x3f;
 683         if (user_mode(regs)) {
 684                 __u64 buffer;
 685                 /* Initialise these to NaNs. */
 686                 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
 687
 688                 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
 689                         return -1;
 690                 }
 691
 692                 /* 'current' may be the current owner of the FPU state, so
 693                    context switch the registers into memory so they can be
 694                    indexed by register number. */
 695                 if (last_task_used_math == current) {
 696                         grab_fpu();
 697                         fpsave(&current->thread.fpu.hard);
 698                         release_fpu();
 699                         last_task_used_math = NULL;
 700                         regs->sr |= SR_FD;
 701                 }
 702
 703                 switch (width_shift) {
 704                 case 2:
 705                         buflo = current->thread.fpu.hard.fp_regs[srcreg];
 706                         break;
 707                 case 3:
 708                         if (do_paired_load) {
 709                                 buflo = current->thread.fpu.hard.fp_regs[srcreg];
 710                                 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
 711                         } else {
 712 #if defined(CONFIG_LITTLE_ENDIAN)
 713                                 bufhi = current->thread.fpu.hard.fp_regs[srcreg];
 714                                 buflo = current->thread.fpu.hard.fp_regs[srcreg+1];
 715 #else
 716                                 buflo = current->thread.fpu.hard.fp_regs[srcreg];
 717                                 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
 718 #endif
 719                         }
 720                         break;
 721                 default:
 722                         printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
 723                                 width_shift, (unsigned long) regs->pc);
 724                         break;
 725                 }
 726
 727                 *(__u32*) &buffer = buflo;
 728                 *(1 + (__u32*) &buffer) = bufhi;
 729                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
 730                         return -1; /* fault */
 731                 }
 732                 return 0;
 733         } else {
 734                 die ("Misaligned FPU load inside kernel", regs, 0);
 735                 return -1;
 736         }
 737 }
 738 #endif
 739
 740 static int misaligned_fixup(struct pt_regs *regs)
 741 {
 742         unsigned long opcode;
 743         int error;
 744         int major, minor;
 745
 746 #if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 747         /* Never fixup user mode misaligned accesses without this option enabled. */
 748         return -1;
 749 #else
 750         if (!user_mode_unaligned_fixup_enable) return -1;
 751 #endif
 752
 753         error = read_opcode(regs->pc, &opcode, user_mode(regs));
 754         if (error < 0) {
 755                 return error;
 756         }
 757         major = (opcode >> 26) & 0x3f;
 758         minor = (opcode >> 16) & 0xf;
 759
 760 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 761         if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
 762                 --user_mode_unaligned_fixup_count;
 763                 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
 764                 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
 765                        current->comm, current->pid, (__u32)regs->pc, opcode);
 766         } else
 767 #endif
 768         if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
 769                 --kernel_mode_unaligned_fixup_count;
 770                 if (in_interrupt()) {
 771                         printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
 772                                (__u32)regs->pc, opcode);
 773                 } else {
 774                         printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
 775                                current->comm, current->pid, (__u32)regs->pc, opcode);
 776                 }
 777         }
 778
 779
 780         switch (major) {
 781                 case (0x84>>2): /* LD.W */
 782                         error = misaligned_load(regs, opcode, 1, 1, 1);
 783                         break;
 784                 case (0xb0>>2): /* LD.UW */
 785                         error = misaligned_load(regs, opcode, 1, 1, 0);
 786                         break;
 787                 case (0x88>>2): /* LD.L */
 788                         error = misaligned_load(regs, opcode, 1, 2, 1);
 789                         break;
 790                 case (0x8c>>2): /* LD.Q */
 791                         error = misaligned_load(regs, opcode, 1, 3, 0);
 792                         break;
 793
 794                 case (0xa4>>2): /* ST.W */
 795                         error = misaligned_store(regs, opcode, 1, 1);
 796                         break;
 797                 case (0xa8>>2): /* ST.L */
 798                         error = misaligned_store(regs, opcode, 1, 2);
 799                         break;
 800                 case (0xac>>2): /* ST.Q */
 801                         error = misaligned_store(regs, opcode, 1, 3);
 802                         break;
 803
 804                 case (0x40>>2): /* indexed loads */
 805                         switch (minor) {
 806                                 case 0x1: /* LDX.W */
 807                                         error = misaligned_load(regs, opcode, 0, 1, 1);
 808                                         break;
 809                                 case 0x5: /* LDX.UW */
 810                                         error = misaligned_load(regs, opcode, 0, 1, 0);
 811                                         break;
 812                                 case 0x2: /* LDX.L */
 813                                         error = misaligned_load(regs, opcode, 0, 2, 1);
 814                                         break;
 815                                 case 0x3: /* LDX.Q */
 816                                         error = misaligned_load(regs, opcode, 0, 3, 0);
 817                                         break;
 818                                 default:
 819                                         error = -1;
 820                                         break;
 821                         }
 822                         break;
 823
 824                 case (0x60>>2): /* indexed stores */
 825                         switch (minor) {
 826                                 case 0x1: /* STX.W */
 827                                         error = misaligned_store(regs, opcode, 0, 1);
 828                                         break;
 829                                 case 0x2: /* STX.L */
 830                                         error = misaligned_store(regs, opcode, 0, 2);
 831                                         break;
 832                                 case 0x3: /* STX.Q */
 833                                         error = misaligned_store(regs, opcode, 0, 3);
 834                                         break;
 835                                 default:
 836                                         error = -1;
 837                                         break;
 838                         }
 839                         break;
 840
 841 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 842                 case (0x94>>2): /* FLD.S */
 843                         error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
 844                         break;
 845                 case (0x98>>2): /* FLD.P */
 846                         error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
 847                         break;
 848                 case (0x9c>>2): /* FLD.D */
 849                         error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
 850                         break;
 851                 case (0x1c>>2): /* floating indexed loads */
 852                         switch (minor) {
 853                         case 0x8: /* FLDX.S */
 854                                 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
 855                                 break;
 856                         case 0xd: /* FLDX.P */
 857                                 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
 858                                 break;
 859                         case 0x9: /* FLDX.D */
 860                                 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
 861                                 break;
 862                         default:
 863                                 error = -1;
 864                                 break;
 865                         }
 866                         break;
 867                 case (0xb4>>2): /* FLD.S */
 868                         error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
 869                         break;
 870                 case (0xb8>>2): /* FLD.P */
 871                         error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
 872                         break;
 873                 case (0xbc>>2): /* FLD.D */
 874                         error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
 875                         break;
 876                 case (0x3c>>2): /* floating indexed stores */
 877                         switch (minor) {
 878                         case 0x8: /* FSTX.S */
 879                                 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
 880                                 break;
 881                         case 0xd: /* FSTX.P */
 882                                 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
 883                                 break;
 884                         case 0x9: /* FSTX.D */
 885                                 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
 886                                 break;
 887                         default:
 888                                 error = -1;
 889                                 break;
 890                         }
 891                         break;
 892 #endif
 893
 894                 default:
 895                         /* Fault */
 896                         error = -1;
 897                         break;
 898         }
 899
 900         if (error < 0) {
 901                 return error;
 902         } else {
 903                 regs->pc += 4; /* Skip the instruction that's just been emulated */
 904                 return 0;
 905         }
 906
 907 }
 908
 909 static ctl_table unaligned_table[] = {
 910         {1, "kernel_reports", &kernel_mode_unaligned_fixup_count,
 911                 sizeof(int), 0644, NULL, &proc_dointvec},
 912 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 913         {2, "user_reports", &user_mode_unaligned_fixup_count,
 914                 sizeof(int), 0644, NULL, &proc_dointvec},
 915         {3, "user_enable", &user_mode_unaligned_fixup_enable,
 916                 sizeof(int), 0644, NULL, &proc_dointvec},
 917 #endif
 918         {0}
 919 };
 920
 921 static ctl_table unaligned_root[] = {
 922         {1, "unaligned_fixup", NULL, 0, 0555, unaligned_table},
 923         {0}
 924 };
 925
 926 static ctl_table sh64_root[] = {
 927         {1, "sh64", NULL, 0, 0555, unaligned_root},
 928         {0}
 929 };
 930 static struct ctl_table_header *sysctl_header;
 931 static int __init init_sysctl(void)
 932 {
 933         sysctl_header = register_sysctl_table(sh64_root, 0);
 934         return 0;
 935 }
 936
 937 __initcall(init_sysctl);
 938
 939
 940 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
 941 {
 942         u64 peek_real_address_q(u64 addr);
 943         u64 poke_real_address_q(u64 addr, u64 val);
 944         unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
 945         unsigned long long exp_cause;
 946         /* It's not worth ioremapping the debug module registers for the amount
 947            of access we make to them - just go direct to their physical
 948            addresses. */
 949         exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
 950         if (exp_cause & ~4) {
 951                 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
 952                         (unsigned long)(exp_cause & 0xffffffff));
 953         }
 954         show_state();
 955         /* Clear all DEBUGINT causes */
 956         poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
 957 }
 958