arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/slab.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/pagemap.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/bitext.h>
  24 #include <asm/page.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/io.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/sbus.h>
  36 #include <asm/asi.h>
  37 #include <asm/msi.h>
  38 #include <asm/a.out.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/io-unit.h>
  41 #include <asm/cacheflush.h>
  42 #include <asm/tlbflush.h>
  43
  44 /* Now the cpu specific definitions. */
  45 #include <asm/viking.h>
  46 #include <asm/mxcc.h>
  47 #include <asm/ross.h>
  48 #include <asm/tsunami.h>
  49 #include <asm/swift.h>
  50 #include <asm/turbosparc.h>
  51
  52 #include <asm/btfixup.h>
  53
  54 enum mbus_module srmmu_modtype;
  55 unsigned int hwbug_bitmask;
  56 int vac_cache_size;
  57 int vac_line_size;
  58
  59 extern struct resource sparc_iomap;
  60
  61 extern unsigned long last_valid_pfn;
  62
  63 extern unsigned long page_kernel;
  64
  65 pgd_t *srmmu_swapper_pg_dir;
  66
  67 #ifdef CONFIG_SMP
  68 #define FLUSH_BEGIN(mm)
  69 #define FLUSH_END
  70 #else
  71 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  72 #define FLUSH_END       }
  73 #endif
  74
  75 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  76 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  77
  78 int flush_page_for_dma_global = 1;
  79
  80 #ifdef CONFIG_SMP
  81 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  82 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  83 #endif
  84
  85 char *srmmu_name;
  86
  87 ctxd_t *srmmu_ctx_table_phys;
  88 ctxd_t *srmmu_context_table;
  89
  90 int viking_mxcc_present;
  91 static spinlock_t srmmu_context_spinlock = SPIN_LOCK_UNLOCKED;
  92
  93 int is_hypersparc;
  94
  95 /*
  96  * In general all page table modifications should use the V8 atomic
  97  * swap instruction.  This insures the mmu and the cpu are in sync
  98  * with respect to ref/mod bits in the page tables.
  99  */
 100 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
 101 {
 102         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 103         return value;
 104 }
 105
 106 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 107 {
 108         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 109 }
 110
 111 /* The very generic SRMMU page table operations. */
 112 static inline int srmmu_device_memory(unsigned long x)
 113 {
 114         return ((x & 0xF0000000) != 0);
 115 }
 116
 117 int srmmu_cache_pagetables;
 118
 119 /* these will be initialized in srmmu_nocache_calcsize() */
 120 unsigned long srmmu_nocache_size;
 121 unsigned long srmmu_nocache_end;
 122
 123 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 124 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 125
 126 /* The context table is a nocache user with the biggest alignment needs. */
 127 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 128
 129 void *srmmu_nocache_pool;
 130 void *srmmu_nocache_bitmap;
 131 static struct bit_map srmmu_nocache_map;
 132
 133 static unsigned long srmmu_pte_pfn(pte_t pte)
 134 {
 135         if (srmmu_device_memory(pte_val(pte))) {
 136                 /* XXX Anton obviously had something in mind when he did this.
 137                  * But what?
 138                  */
 139                 /* return (struct page *)~0; */
 140                 BUG();
 141         }
 142         return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
 143 }
 144
 145 static struct page *srmmu_pmd_page(pmd_t pmd)
 146 {
 147
 148         if (srmmu_device_memory(pmd_val(pmd)))
 149                 BUG();
 150         return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
 151 }
 152
 153 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 154 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 155
 156
 157 static inline int srmmu_pte_none(pte_t pte)
 158 { return !(pte_val(pte) & 0xFFFFFFF); }
 159
 160 static inline int srmmu_pte_present(pte_t pte)
 161 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 162
 163 static inline void srmmu_pte_clear(pte_t *ptep)
 164 { srmmu_set_pte(ptep, __pte(0)); }
 165
 166 static inline int srmmu_pmd_none(pmd_t pmd)
 167 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 168
 169 static inline int srmmu_pmd_bad(pmd_t pmd)
 170 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 171
 172 static inline int srmmu_pmd_present(pmd_t pmd)
 173 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 174
 175 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
 176         int i;
 177         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
 178                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
 179 }
 180
 181 static inline int srmmu_pgd_none(pgd_t pgd)
 182 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 183
 184 static inline int srmmu_pgd_bad(pgd_t pgd)
 185 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 186
 187 static inline int srmmu_pgd_present(pgd_t pgd)
 188 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 189
 190 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 191 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 192
 193 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 194 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 195
 196 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 197 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 198
 199 static inline pte_t srmmu_pte_mkold(pte_t pte)
 200 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 201
 202 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 203 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 204
 205 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 206 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 207
 208 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 209 { return __pte(pte_val(pte) | SRMMU_REF);}
 210
 211 /*
 212  * Conversion functions: convert a page and protection to a page entry,
 213  * and a page entry and page directory to the page they refer to.
 214  */
 215 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 216 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 217
 218 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 219 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 220
 221 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 222 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 223
 224 /* XXX should we hyper_flush_whole_icache here - Anton */
 225 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 226 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 227
 228 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 229 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 230
 231 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 232 {
 233         unsigned long ptp;      /* Physical address, shifted right by 4 */
 234         int i;
 235
 236         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 237         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 238                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 239                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 240         }
 241 }
 242
 243 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 244 {
 245         unsigned long ptp;      /* Physical address, shifted right by 4 */
 246         int i;
 247
 248         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 249         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 250                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 251                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 252         }
 253 }
 254
 255 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 256 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 257
 258 /* to find an entry in a top-level page table... */
 259 extern inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 260 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 261
 262 /* Find an entry in the second-level page table.. */
 263 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 264 {
 265         return (pmd_t *) srmmu_pgd_page(*dir) +
 266             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 267 }
 268
 269 /* Find an entry in the third-level page table.. */
 270 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 271 {
 272         void *pte;
 273
 274         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 275         return (pte_t *) pte +
 276             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 277 }
 278
 279 static unsigned long srmmu_swp_type(swp_entry_t entry)
 280 {
 281         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 282 }
 283
 284 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 285 {
 286         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 287 }
 288
 289 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 290 {
 291         return (swp_entry_t) {
 292                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 293                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 294 }
 295
 296 /*
 297  * size: bytes to allocate in the nocache area.
 298  * align: bytes, number to align at.
 299  * Returns the virtual address of the allocated area.
 300  */
 301 static unsigned long __srmmu_get_nocache(int size, int align)
 302 {
 303         int offset;
 304
 305         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 306                 printk("Size 0x%x too small for nocache request\n", size);
 307                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 308         }
 309         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 310                 printk("Size 0x%x unaligned int nocache request\n", size);
 311                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 312         }
 313         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 314
 315         offset = bit_map_string_get(&srmmu_nocache_map,
 316                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 317                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 318         if (offset == -1) {
 319                 printk("srmmu: out of nocache %d: %d/%d\n",
 320                     size, (int) srmmu_nocache_size,
 321                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 322                 return 0;
 323         }
 324
 325         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 326 }
 327
 328 unsigned inline long srmmu_get_nocache(int size, int align)
 329 {
 330         unsigned long tmp;
 331
 332         tmp = __srmmu_get_nocache(size, align);
 333
 334         if (tmp)
 335                 memset((void *)tmp, 0, size);
 336
 337         return tmp;
 338 }
 339
 340 void srmmu_free_nocache(unsigned long vaddr, int size)
 341 {
 342         int offset;
 343
 344         if (vaddr < SRMMU_NOCACHE_VADDR) {
 345                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 346                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 347                 BUG();
 348         }
 349         if (vaddr+size > srmmu_nocache_end) {
 350                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 351                     vaddr, srmmu_nocache_end);
 352                 BUG();
 353         }
 354         if (size & (size-1)) {
 355                 printk("Size 0x%x is not a power of 2\n", size);
 356                 BUG();
 357         }
 358         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 359                 printk("Size 0x%x is too small\n", size);
 360                 BUG();
 361         }
 362         if (vaddr & (size-1)) {
 363                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 364                 BUG();
 365         }
 366
 367         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 368         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 369
 370         bit_map_clear(&srmmu_nocache_map, offset, size);
 371 }
 372
 373 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);
 374
 375 extern unsigned long probe_memory(void);        /* in fault.c */
 376
 377 /*
 378  * Reserve nocache dynamically proportionally to the amount of
 379  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 380  */
 381 void srmmu_nocache_calcsize(void)
 382 {
 383         unsigned long sysmemavail = probe_memory() / 1024;
 384         int srmmu_nocache_npages;
 385
 386         srmmu_nocache_npages =
 387                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 388
 389  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 390         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 391         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 392                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 393
 394         /* anything above 1280 blows up */
 395         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 396                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 397
 398         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 399         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 400 }
 401
 402 void srmmu_nocache_init(void)
 403 {
 404         unsigned int bitmap_bits;
 405         pgd_t *pgd;
 406         pmd_t *pmd;
 407         pte_t *pte;
 408         unsigned long paddr, vaddr;
 409         unsigned long pteval;
 410
 411         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 412
 413         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 414                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 415         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 416
 417         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 418         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 419
 420         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 421         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 422         init_mm.pgd = srmmu_swapper_pg_dir;
 423
 424         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 425
 426         paddr = __pa((unsigned long)srmmu_nocache_pool);
 427         vaddr = SRMMU_NOCACHE_VADDR;
 428
 429         while (vaddr < srmmu_nocache_end) {
 430                 pgd = pgd_offset_k(vaddr);
 431                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 432                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 433
 434                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 435
 436                 if (srmmu_cache_pagetables)
 437                         pteval |= SRMMU_CACHE;
 438
 439                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 440
 441                 vaddr += PAGE_SIZE;
 442                 paddr += PAGE_SIZE;
 443         }
 444
 445         flush_cache_all();
 446         flush_tlb_all();
 447 }
 448
 449 static inline pgd_t *srmmu_get_pgd_fast(void)
 450 {
 451         pgd_t *pgd = NULL;
 452
 453         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 454         if (pgd) {
 455                 pgd_t *init = pgd_offset_k(0);
 456                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 457                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 458                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 459         }
 460
 461         return pgd;
 462 }
 463
 464 static void srmmu_free_pgd_fast(pgd_t *pgd)
 465 {
 466         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 467 }
 468
 469 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 470 {
 471         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 472 }
 473
 474 static void srmmu_pmd_free(pmd_t * pmd)
 475 {
 476         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 477 }
 478
 479 /*
 480  * Hardware needs alignment to 256 only, but we align to whole page size
 481  * to reduce fragmentation problems due to the buddy principle.
 482  * XXX Provide actual fragmentation statistics in /proc.
 483  *
 484  * Alignments up to the page size are the same for physical and virtual
 485  * addresses of the nocache area.
 486  */
 487 static pte_t *
 488 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 489 {
 490         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 491 }
 492
 493 static struct page *
 494 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 495 {
 496         unsigned long pte;
 497
 498         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 499                 return NULL;
 500         return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 501 }
 502
 503 static void srmmu_free_pte_fast(pte_t *pte)
 504 {
 505         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 506 }
 507
 508 static void srmmu_pte_free(struct page *pte)
 509 {
 510         unsigned long p;
 511
 512         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 513         if (p == 0)
 514                 BUG();
 515         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 516         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 517         srmmu_free_nocache(p, PTE_SIZE);
 518 }
 519
 520 /*
 521  */
 522 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 523 {
 524         struct ctx_list *ctxp;
 525
 526         ctxp = ctx_free.next;
 527         if(ctxp != &ctx_free) {
 528                 remove_from_ctx_list(ctxp);
 529                 add_to_used_ctxlist(ctxp);
 530                 mm->context = ctxp->ctx_number;
 531                 ctxp->ctx_mm = mm;
 532                 return;
 533         }
 534         ctxp = ctx_used.next;
 535         if(ctxp->ctx_mm == old_mm)
 536                 ctxp = ctxp->next;
 537         if(ctxp == &ctx_used)
 538                 panic("out of mmu contexts");
 539         flush_cache_mm(ctxp->ctx_mm);
 540         flush_tlb_mm(ctxp->ctx_mm);
 541         remove_from_ctx_list(ctxp);
 542         add_to_used_ctxlist(ctxp);
 543         ctxp->ctx_mm->context = NO_CONTEXT;
 544         ctxp->ctx_mm = mm;
 545         mm->context = ctxp->ctx_number;
 546 }
 547
 548 static inline void free_context(int context)
 549 {
 550         struct ctx_list *ctx_old;
 551
 552         ctx_old = ctx_list_pool + context;
 553         remove_from_ctx_list(ctx_old);
 554         add_to_free_ctxlist(ctx_old);
 555 }
 556
 557
 558 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 559     struct task_struct *tsk, int cpu)
 560 {
 561         if(mm->context == NO_CONTEXT) {
 562                 spin_lock(&srmmu_context_spinlock);
 563                 alloc_context(old_mm, mm);
 564                 spin_unlock(&srmmu_context_spinlock);
 565                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 566         }
 567
 568         if (is_hypersparc)
 569                 hyper_flush_whole_icache();
 570
 571         srmmu_set_context(mm->context);
 572 }
 573
 574 /* Low level IO area allocation on the SRMMU. */
 575 static inline void srmmu_mapioaddr(unsigned long physaddr,
 576     unsigned long virt_addr, int bus_type)
 577 {
 578         pgd_t *pgdp;
 579         pmd_t *pmdp;
 580         pte_t *ptep;
 581         unsigned long tmp;
 582
 583         physaddr &= PAGE_MASK;
 584         pgdp = pgd_offset_k(virt_addr);
 585         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 586         ptep = srmmu_pte_offset(pmdp, virt_addr);
 587         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 588
 589         /*
 590          * I need to test whether this is consistent over all
 591          * sun4m's.  The bus_type represents the upper 4 bits of
 592          * 36-bit physical address on the I/O space lines...
 593          */
 594         tmp |= (bus_type << 28);
 595         tmp |= SRMMU_PRIV;
 596         __flush_page_to_ram(virt_addr);
 597         srmmu_set_pte(ptep, __pte(tmp));
 598 }
 599
 600 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 601     unsigned long xva, unsigned int len)
 602 {
 603         while (len != 0) {
 604                 len -= PAGE_SIZE;
 605                 srmmu_mapioaddr(xpa, xva, bus);
 606                 xva += PAGE_SIZE;
 607                 xpa += PAGE_SIZE;
 608         }
 609         flush_tlb_all();
 610 }
 611
 612 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 613 {
 614         pgd_t *pgdp;
 615         pmd_t *pmdp;
 616         pte_t *ptep;
 617
 618         pgdp = pgd_offset_k(virt_addr);
 619         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 620         ptep = srmmu_pte_offset(pmdp, virt_addr);
 621
 622         /* No need to flush uncacheable page. */
 623         srmmu_pte_clear(ptep);
 624 }
 625
 626 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 627 {
 628         while (len != 0) {
 629                 len -= PAGE_SIZE;
 630                 srmmu_unmapioaddr(virt_addr);
 631                 virt_addr += PAGE_SIZE;
 632         }
 633         flush_tlb_all();
 634 }
 635
 636 /*
 637  * On the SRMMU we do not have the problems with limited tlb entries
 638  * for mapping kernel pages, so we just take things from the free page
 639  * pool.  As a side effect we are putting a little too much pressure
 640  * on the gfp() subsystem.  This setup also makes the logic of the
 641  * iommu mapping code a lot easier as we can transparently handle
 642  * mappings on the kernel stack without any special code as we did
 643  * need on the sun4c.
 644  */
 645 struct thread_info *srmmu_alloc_thread_info(void)
 646 {
 647         struct thread_info *ret;
 648
 649         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 650                                                      THREAD_INFO_ORDER);
 651 #ifdef CONFIG_DEBUG_STACK_USAGE
 652         if (ret)
 653                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 654 #endif /* DEBUG_STACK_USAGE */
 655
 656         return ret;
 657 }
 658
 659 static void srmmu_free_thread_info(struct thread_info *ti)
 660 {
 661         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 662 }
 663
 664 /* tsunami.S */
 665 extern void tsunami_flush_cache_all(void);
 666 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 667 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 668 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 669 extern void tsunami_flush_page_to_ram(unsigned long page);
 670 extern void tsunami_flush_page_for_dma(unsigned long page);
 671 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 672 extern void tsunami_flush_tlb_all(void);
 673 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 674 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 675 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 676 extern void tsunami_setup_blockops(void);
 677
 678 /*
 679  * Workaround, until we find what's going on with Swift. When low on memory,
 680  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 681  * out it is already in page tables/ fault again on the same instruction.
 682  * I really don't understand it, have checked it and contexts
 683  * are right, flush_tlb_all is done as well, and it faults again...
 684  * Strange. -jj
 685  *
 686  * The following code is a deadwood that may be necessary when
 687  * we start to make precise page flushes again. --zaitcev
 688  */
 689 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 690 {
 691 #if 0
 692         static unsigned long last;
 693         unsigned int val;
 694         /* unsigned int n; */
 695
 696         if (address == last) {
 697                 val = srmmu_hwprobe(address);
 698                 if (val != 0 && pte_val(pte) != val) {
 699                         printk("swift_update_mmu_cache: "
 700                             "addr %lx put %08x probed %08x from %p\n",
 701                             address, pte_val(pte), val,
 702                             __builtin_return_address(0));
 703                         srmmu_flush_whole_tlb();
 704                 }
 705         }
 706         last = address;
 707 #endif
 708 }
 709
 710 /* swift.S */
 711 extern void swift_flush_cache_all(void);
 712 extern void swift_flush_cache_mm(struct mm_struct *mm);
 713 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 714                                     unsigned long start, unsigned long end);
 715 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 716 extern void swift_flush_page_to_ram(unsigned long page);
 717 extern void swift_flush_page_for_dma(unsigned long page);
 718 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 719 extern void swift_flush_tlb_all(void);
 720 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 721 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 722                                   unsigned long start, unsigned long end);
 723 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 724
 725 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 726 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 727 {
 728         int cctx, ctx1;
 729
 730         page &= PAGE_MASK;
 731         if ((ctx1 = vma->vm_mm->context) != -1) {
 732                 cctx = srmmu_get_context();
 733 /* Is context # ever different from current context? P3 */
 734                 if (cctx != ctx1) {
 735                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 736                         srmmu_set_context(ctx1);
 737                         swift_flush_page(page);
 738                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 739                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 740                         srmmu_set_context(cctx);
 741                 } else {
 742                          /* Rm. prot. bits from virt. c. */
 743                         /* swift_flush_cache_all(); */
 744                         /* swift_flush_cache_page(vma, page); */
 745                         swift_flush_page(page);
 746
 747                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 748                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 749                         /* same as above: srmmu_flush_tlb_page() */
 750                 }
 751         }
 752 }
 753 #endif
 754
 755 /*
 756  * The following are all MBUS based SRMMU modules, and therefore could
 757  * be found in a multiprocessor configuration.  On the whole, these
 758  * chips seems to be much more touchy about DVMA and page tables
 759  * with respect to cache coherency.
 760  */
 761
 762 /* Cypress flushes. */
 763 static void cypress_flush_cache_all(void)
 764 {
 765         volatile unsigned long cypress_sucks;
 766         unsigned long faddr, tagval;
 767
 768         flush_user_windows();
 769         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 770                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 771                                      "=r" (tagval) :
 772                                      "r" (faddr), "r" (0x40000),
 773                                      "i" (ASI_M_DATAC_TAG));
 774
 775                 /* If modified and valid, kick it. */
 776                 if((tagval & 0x60) == 0x60)
 777                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 778         }
 779 }
 780
 781 static void cypress_flush_cache_mm(struct mm_struct *mm)
 782 {
 783         register unsigned long a, b, c, d, e, f, g;
 784         unsigned long flags, faddr;
 785         int octx;
 786
 787         FLUSH_BEGIN(mm)
 788         flush_user_windows();
 789         local_irq_save(flags);
 790         octx = srmmu_get_context();
 791         srmmu_set_context(mm->context);
 792         a = 0x20; b = 0x40; c = 0x60;
 793         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 794
 795         faddr = (0x10000 - 0x100);
 796         goto inside;
 797         do {
 798                 faddr -= 0x100;
 799         inside:
 800                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 801                                      "sta %%g0, [%0 + %2] %1\n\t"
 802                                      "sta %%g0, [%0 + %3] %1\n\t"
 803                                      "sta %%g0, [%0 + %4] %1\n\t"
 804                                      "sta %%g0, [%0 + %5] %1\n\t"
 805                                      "sta %%g0, [%0 + %6] %1\n\t"
 806                                      "sta %%g0, [%0 + %7] %1\n\t"
 807                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 808                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 809                                      "r" (a), "r" (b), "r" (c), "r" (d),
 810                                      "r" (e), "r" (f), "r" (g));
 811         } while(faddr);
 812         srmmu_set_context(octx);
 813         local_irq_restore(flags);
 814         FLUSH_END
 815 }
 816
 817 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 818 {
 819         struct mm_struct *mm = vma->vm_mm;
 820         register unsigned long a, b, c, d, e, f, g;
 821         unsigned long flags, faddr;
 822         int octx;
 823
 824         FLUSH_BEGIN(mm)
 825         flush_user_windows();
 826         local_irq_save(flags);
 827         octx = srmmu_get_context();
 828         srmmu_set_context(mm->context);
 829         a = 0x20; b = 0x40; c = 0x60;
 830         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 831
 832         start &= SRMMU_REAL_PMD_MASK;
 833         while(start < end) {
 834                 faddr = (start + (0x10000 - 0x100));
 835                 goto inside;
 836                 do {
 837                         faddr -= 0x100;
 838                 inside:
 839                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 840                                              "sta %%g0, [%0 + %2] %1\n\t"
 841                                              "sta %%g0, [%0 + %3] %1\n\t"
 842                                              "sta %%g0, [%0 + %4] %1\n\t"
 843                                              "sta %%g0, [%0 + %5] %1\n\t"
 844                                              "sta %%g0, [%0 + %6] %1\n\t"
 845                                              "sta %%g0, [%0 + %7] %1\n\t"
 846                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 847                                              "r" (faddr),
 848                                              "i" (ASI_M_FLUSH_SEG),
 849                                              "r" (a), "r" (b), "r" (c), "r" (d),
 850                                              "r" (e), "r" (f), "r" (g));
 851                 } while (faddr != start);
 852                 start += SRMMU_REAL_PMD_SIZE;
 853         }
 854         srmmu_set_context(octx);
 855         local_irq_restore(flags);
 856         FLUSH_END
 857 }
 858
 859 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 860 {
 861         register unsigned long a, b, c, d, e, f, g;
 862         struct mm_struct *mm = vma->vm_mm;
 863         unsigned long flags, line;
 864         int octx;
 865
 866         FLUSH_BEGIN(mm)
 867         flush_user_windows();
 868         local_irq_save(flags);
 869         octx = srmmu_get_context();
 870         srmmu_set_context(mm->context);
 871         a = 0x20; b = 0x40; c = 0x60;
 872         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 873
 874         page &= PAGE_MASK;
 875         line = (page + PAGE_SIZE) - 0x100;
 876         goto inside;
 877         do {
 878                 line -= 0x100;
 879         inside:
 880                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 881                                              "sta %%g0, [%0 + %2] %1\n\t"
 882                                              "sta %%g0, [%0 + %3] %1\n\t"
 883                                              "sta %%g0, [%0 + %4] %1\n\t"
 884                                              "sta %%g0, [%0 + %5] %1\n\t"
 885                                              "sta %%g0, [%0 + %6] %1\n\t"
 886                                              "sta %%g0, [%0 + %7] %1\n\t"
 887                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 888                                              "r" (line),
 889                                              "i" (ASI_M_FLUSH_PAGE),
 890                                              "r" (a), "r" (b), "r" (c), "r" (d),
 891                                              "r" (e), "r" (f), "r" (g));
 892         } while(line != page);
 893         srmmu_set_context(octx);
 894         local_irq_restore(flags);
 895         FLUSH_END
 896 }
 897
 898 /* Cypress is copy-back, at least that is how we configure it. */
 899 static void cypress_flush_page_to_ram(unsigned long page)
 900 {
 901         register unsigned long a, b, c, d, e, f, g;
 902         unsigned long line;
 903
 904         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 905         page &= PAGE_MASK;
 906         line = (page + PAGE_SIZE) - 0x100;
 907         goto inside;
 908         do {
 909                 line -= 0x100;
 910         inside:
 911                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 912                                      "sta %%g0, [%0 + %2] %1\n\t"
 913                                      "sta %%g0, [%0 + %3] %1\n\t"
 914                                      "sta %%g0, [%0 + %4] %1\n\t"
 915                                      "sta %%g0, [%0 + %5] %1\n\t"
 916                                      "sta %%g0, [%0 + %6] %1\n\t"
 917                                      "sta %%g0, [%0 + %7] %1\n\t"
 918                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 919                                      "r" (line),
 920                                      "i" (ASI_M_FLUSH_PAGE),
 921                                      "r" (a), "r" (b), "r" (c), "r" (d),
 922                                      "r" (e), "r" (f), "r" (g));
 923         } while(line != page);
 924 }
 925
 926 /* Cypress is also IO cache coherent. */
 927 static void cypress_flush_page_for_dma(unsigned long page)
 928 {
 929 }
 930
 931 /* Cypress has unified L2 VIPT, from which both instructions and data
 932  * are stored.  It does not have an onboard icache of any sort, therefore
 933  * no flush is necessary.
 934  */
 935 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 936 {
 937 }
 938
 939 static void cypress_flush_tlb_all(void)
 940 {
 941         srmmu_flush_whole_tlb();
 942 }
 943
 944 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 945 {
 946         FLUSH_BEGIN(mm)
 947         __asm__ __volatile__(
 948         "lda    [%0] %3, %%g5\n\t"
 949         "sta    %2, [%0] %3\n\t"
 950         "sta    %%g0, [%1] %4\n\t"
 951         "sta    %%g5, [%0] %3\n"
 952         : /* no outputs */
 953         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 954           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 955         : "g5");
 956         FLUSH_END
 957 }
 958
 959 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 960 {
 961         struct mm_struct *mm = vma->vm_mm;
 962         unsigned long size;
 963
 964         FLUSH_BEGIN(mm)
 965         start &= SRMMU_PGDIR_MASK;
 966         size = SRMMU_PGDIR_ALIGN(end) - start;
 967         __asm__ __volatile__(
 968                 "lda    [%0] %5, %%g5\n\t"
 969                 "sta    %1, [%0] %5\n"
 970                 "1:\n\t"
 971                 "subcc  %3, %4, %3\n\t"
 972                 "bne    1b\n\t"
 973                 " sta   %%g0, [%2 + %3] %6\n\t"
 974                 "sta    %%g5, [%0] %5\n"
 975         : /* no outputs */
 976         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 977           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 978           "i" (ASI_M_FLUSH_PROBE)
 979         : "g5", "cc");
 980         FLUSH_END
 981 }
 982
 983 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 984 {
 985         struct mm_struct *mm = vma->vm_mm;
 986
 987         FLUSH_BEGIN(mm)
 988         __asm__ __volatile__(
 989         "lda    [%0] %3, %%g5\n\t"
 990         "sta    %1, [%0] %3\n\t"
 991         "sta    %%g0, [%2] %4\n\t"
 992         "sta    %%g5, [%0] %3\n"
 993         : /* no outputs */
 994         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 995           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 996         : "g5");
 997         FLUSH_END
 998 }
 999
1000 /* viking.S */
1001 extern void viking_flush_cache_all(void);
1002 extern void viking_flush_cache_mm(struct mm_struct *mm);
1003 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1004                                      unsigned long end);
1005 extern void viking_flush_cache_page(struct vm_area_struct *vma,
1006                                     unsigned long page);
1007 extern void viking_flush_page_to_ram(unsigned long page);
1008 extern void viking_flush_page_for_dma(unsigned long page);
1009 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1010 extern void viking_flush_page(unsigned long page);
1011 extern void viking_mxcc_flush_page(unsigned long page);
1012 extern void viking_flush_tlb_all(void);
1013 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1014 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1015                                    unsigned long end);
1016 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1017                                   unsigned long page);
1018 extern void sun4dsmp_flush_tlb_all(void);
1019 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1020 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1021                                    unsigned long end);
1022 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1023                                   unsigned long page);
1024
1025 /* hypersparc.S */
1026 extern void hypersparc_flush_cache_all(void);
1027 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1028 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1029 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1030 extern void hypersparc_flush_page_to_ram(unsigned long page);
1031 extern void hypersparc_flush_page_for_dma(unsigned long page);
1032 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1033 extern void hypersparc_flush_tlb_all(void);
1034 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1035 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1036 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1037 extern void hypersparc_setup_blockops(void);
1038
1039 /*
1040  * NOTE: All of this startup code assumes the low 16mb (approx.) of
1041  *       kernel mappings are done with one single contiguous chunk of
1042  *       ram.  On small ram machines (classics mainly) we only get
1043  *       around 8mb mapped for us.
1044  */
1045
1046 void __init early_pgtable_allocfail(char *type)
1047 {
1048         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1049         prom_halt();
1050 }
1051
1052 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1053 {
1054         pgd_t *pgdp;
1055         pmd_t *pmdp;
1056         pte_t *ptep;
1057
1058         while(start < end) {
1059                 pgdp = pgd_offset_k(start);
1060                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1061                         pmdp = (pmd_t *) __srmmu_get_nocache(
1062                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1063                         if (pmdp == NULL)
1064                                 early_pgtable_allocfail("pmd");
1065                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1066                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1067                 }
1068                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1069                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1070                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1071                         if (ptep == NULL)
1072                                 early_pgtable_allocfail("pte");
1073                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1074                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1075                 }
1076                 if (start > (0xffffffffUL - PMD_SIZE))
1077                         break;
1078                 start = (start + PMD_SIZE) & PMD_MASK;
1079         }
1080 }
1081
1082 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1083 {
1084         pgd_t *pgdp;
1085         pmd_t *pmdp;
1086         pte_t *ptep;
1087
1088         while(start < end) {
1089                 pgdp = pgd_offset_k(start);
1090                 if(srmmu_pgd_none(*pgdp)) {
1091                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1092                         if (pmdp == NULL)
1093                                 early_pgtable_allocfail("pmd");
1094                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1095                         srmmu_pgd_set(pgdp, pmdp);
1096                 }
1097                 pmdp = srmmu_pmd_offset(pgdp, start);
1098                 if(srmmu_pmd_none(*pmdp)) {
1099                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1100                                                              PTE_SIZE);
1101                         if (ptep == NULL)
1102                                 early_pgtable_allocfail("pte");
1103                         memset(ptep, 0, PTE_SIZE);
1104                         srmmu_pmd_set(pmdp, ptep);
1105                 }
1106                 if (start > (0xffffffffUL - PMD_SIZE))
1107                         break;
1108                 start = (start + PMD_SIZE) & PMD_MASK;
1109         }
1110 }
1111
1112 /*
1113  * This is much cleaner than poking around physical address space
1114  * looking at the prom's page table directly which is what most
1115  * other OS's do.  Yuck... this is much better.
1116  */
1117 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)
1118 {
1119         pgd_t *pgdp;
1120         pmd_t *pmdp;
1121         pte_t *ptep;
1122         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1123         unsigned long prompte;
1124
1125         while(start <= end) {
1126                 if (start == 0)
1127                         break; /* probably wrap around */
1128                 if(start == 0xfef00000)
1129                         start = KADB_DEBUGGER_BEGVM;
1130                 if(!(prompte = srmmu_hwprobe(start))) {
1131                         start += PAGE_SIZE;
1132                         continue;
1133                 }
1134
1135                 /* A red snapper, see what it really is. */
1136                 what = 0;
1137
1138                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1139                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1140                                 what = 1;
1141                 }
1142
1143                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1144                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1145                            prompte)
1146                                 what = 2;
1147                 }
1148
1149                 pgdp = pgd_offset_k(start);
1150                 if(what == 2) {
1151                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1152                         start += SRMMU_PGDIR_SIZE;
1153                         continue;
1154                 }
1155                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1156                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1157                         if (pmdp == NULL)
1158                                 early_pgtable_allocfail("pmd");
1159                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1160                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1161                 }
1162                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1163                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1164                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1165                                                              PTE_SIZE);
1166                         if (ptep == NULL)
1167                                 early_pgtable_allocfail("pte");
1168                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1169                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1170                 }
1171                 if(what == 1) {
1172                         /*
1173                          * We bend the rule where all 16 PTPs in a pmd_t point
1174                          * inside the same PTE page, and we leak a perfectly
1175                          * good hardware PTE piece. Alternatives seem worse.
1176                          */
1177                         unsigned int x; /* Index of HW PMD in soft cluster */
1178                         x = (start >> PMD_SHIFT) & 15;
1179                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1180                         start += SRMMU_REAL_PMD_SIZE;
1181                         continue;
1182                 }
1183                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1184                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1185                 start += PAGE_SIZE;
1186         }
1187 }
1188
1189 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1190
1191 /* Create a third-level SRMMU 16MB page mapping. */
1192 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1193 {
1194         pgd_t *pgdp = pgd_offset_k(vaddr);
1195         unsigned long big_pte;
1196
1197         big_pte = KERNEL_PTE(phys_base >> 4);
1198         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1199 }
1200
1201 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1202 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1203 {
1204         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1205         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1206         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1207         /* Map "low" memory only */
1208         const unsigned long min_vaddr = PAGE_OFFSET;
1209         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1210
1211         if (vstart < min_vaddr || vstart >= max_vaddr)
1212                 return vstart;
1213
1214         if (vend > max_vaddr || vend < min_vaddr)
1215                 vend = max_vaddr;
1216
1217         while(vstart < vend) {
1218                 do_large_mapping(vstart, pstart);
1219                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1220         }
1221         return vstart;
1222 }
1223
1224 static inline void memprobe_error(char *msg)
1225 {
1226         prom_printf(msg);
1227         prom_printf("Halting now...\n");
1228         prom_halt();
1229 }
1230
1231 static inline void map_kernel(void)
1232 {
1233         int i;
1234
1235         if (phys_base > 0) {
1236                 do_large_mapping(PAGE_OFFSET, phys_base);
1237         }
1238
1239         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1240                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1241         }
1242
1243         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1244 }
1245
1246 /* Paging initialization on the Sparc Reference MMU. */
1247 extern void sparc_context_init(int);
1248
1249 void (*poke_srmmu)(void) __initdata = NULL;
1250
1251 extern unsigned long bootmem_init(unsigned long *pages_avail);
1252
1253 void __init srmmu_paging_init(void)
1254 {
1255         int i, cpunode;
1256         char node_str[128];
1257         pgd_t *pgd;
1258         pmd_t *pmd;
1259         pte_t *pte;
1260         unsigned long pages_avail;
1261
1262         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1263
1264         if (sparc_cpu_model == sun4d)
1265                 num_contexts = 65536; /* We know it is Viking */
1266         else {
1267                 /* Find the number of contexts on the srmmu. */
1268                 cpunode = prom_getchild(prom_root_node);
1269                 num_contexts = 0;
1270                 while(cpunode != 0) {
1271                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1272                         if(!strcmp(node_str, "cpu")) {
1273                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1274                                 break;
1275                         }
1276                         cpunode = prom_getsibling(cpunode);
1277                 }
1278         }
1279
1280         if(!num_contexts) {
1281                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1282                 prom_halt();
1283         }
1284
1285         pages_avail = 0;
1286         last_valid_pfn = bootmem_init(&pages_avail);
1287
1288         srmmu_nocache_calcsize();
1289         srmmu_nocache_init();
1290         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1291         map_kernel();
1292
1293         /* ctx table has to be physically aligned to its size */
1294         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1295         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1296
1297         for(i = 0; i < num_contexts; i++)
1298                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1299
1300         flush_cache_all();
1301         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1302         flush_tlb_all();
1303         poke_srmmu();
1304
1305 #ifdef CONFIG_SUN_IO
1306         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1307         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1308 #endif
1309
1310         srmmu_allocate_ptable_skeleton(
1311                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1312         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1313
1314         pgd = pgd_offset_k(PKMAP_BASE);
1315         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1316         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1317         pkmap_page_table = pte;
1318
1319         flush_cache_all();
1320         flush_tlb_all();
1321
1322         sparc_context_init(num_contexts);
1323
1324         kmap_init();
1325
1326         {
1327                 unsigned long zones_size[MAX_NR_ZONES];
1328                 unsigned long zholes_size[MAX_NR_ZONES];
1329                 unsigned long npages;
1330                 int znum;
1331
1332                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1333                         zones_size[znum] = zholes_size[znum] = 0;
1334
1335                 npages = max_low_pfn - pfn_base;
1336
1337                 zones_size[ZONE_DMA] = npages;
1338                 zholes_size[ZONE_DMA] = npages - pages_avail;
1339
1340                 npages = highend_pfn - max_low_pfn;
1341                 zones_size[ZONE_HIGHMEM] = npages;
1342                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1343
1344                 free_area_init_node(0, &contig_page_data, NULL, zones_size,
1345                                     pfn_base, zholes_size);
1346                 mem_map = contig_page_data.node_mem_map;
1347         }
1348 }
1349
1350 static void srmmu_mmu_info(struct seq_file *m)
1351 {
1352         seq_printf(m,
1353                    "MMU type\t: %s\n"
1354                    "contexts\t: %d\n"
1355                    "nocache total\t: %ld\n"
1356                    "nocache used\t: %d\n",
1357                    srmmu_name,
1358                    num_contexts,
1359                    srmmu_nocache_size,
1360                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1361 }
1362
1363 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1364 {
1365 }
1366
1367 static void srmmu_destroy_context(struct mm_struct *mm)
1368 {
1369
1370         if(mm->context != NO_CONTEXT) {
1371                 flush_cache_mm(mm);
1372                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1373                 flush_tlb_mm(mm);
1374                 spin_lock(&srmmu_context_spinlock);
1375                 free_context(mm->context);
1376                 spin_unlock(&srmmu_context_spinlock);
1377                 mm->context = NO_CONTEXT;
1378         }
1379 }
1380
1381 /* Init various srmmu chip types. */
1382 static void __init srmmu_is_bad(void)
1383 {
1384         prom_printf("Could not determine SRMMU chip type.\n");
1385         prom_halt();
1386 }
1387
1388 static void __init init_vac_layout(void)
1389 {
1390         int nd, cache_lines;
1391         char node_str[128];
1392 #ifdef CONFIG_SMP
1393         int cpu = 0;
1394         unsigned long max_size = 0;
1395         unsigned long min_line_size = 0x10000000;
1396 #endif
1397
1398         nd = prom_getchild(prom_root_node);
1399         while((nd = prom_getsibling(nd)) != 0) {
1400                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1401                 if(!strcmp(node_str, "cpu")) {
1402                         vac_line_size = prom_getint(nd, "cache-line-size");
1403                         if (vac_line_size == -1) {
1404                                 prom_printf("can't determine cache-line-size, "
1405                                             "halting.\n");
1406                                 prom_halt();
1407                         }
1408                         cache_lines = prom_getint(nd, "cache-nlines");
1409                         if (cache_lines == -1) {
1410                                 prom_printf("can't determine cache-nlines, halting.\n");
1411                                 prom_halt();
1412                         }
1413
1414                         vac_cache_size = cache_lines * vac_line_size;
1415 #ifdef CONFIG_SMP
1416                         if(vac_cache_size > max_size)
1417                                 max_size = vac_cache_size;
1418                         if(vac_line_size < min_line_size)
1419                                 min_line_size = vac_line_size;
1420                         cpu++;
1421                         if (cpu >= NR_CPUS || !cpu_online(cpu))
1422                                 break;
1423 #else
1424                         break;
1425 #endif
1426                 }
1427         }
1428         if(nd == 0) {
1429                 prom_printf("No CPU nodes found, halting.\n");
1430                 prom_halt();
1431         }
1432 #ifdef CONFIG_SMP
1433         vac_cache_size = max_size;
1434         vac_line_size = min_line_size;
1435 #endif
1436         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1437                (int)vac_cache_size, (int)vac_line_size);
1438 }
1439
1440 static void __init poke_hypersparc(void)
1441 {
1442         volatile unsigned long clear;
1443         unsigned long mreg = srmmu_get_mmureg();
1444
1445         hyper_flush_unconditional_combined();
1446
1447         mreg &= ~(HYPERSPARC_CWENABLE);
1448         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1449         mreg |= (HYPERSPARC_CMODE);
1450
1451         srmmu_set_mmureg(mreg);
1452
1453 #if 0 /* XXX I think this is bad news... -DaveM */
1454         hyper_clear_all_tags();
1455 #endif
1456
1457         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1458         hyper_flush_whole_icache();
1459         clear = srmmu_get_faddr();
1460         clear = srmmu_get_fstatus();
1461 }
1462
1463 static void __init init_hypersparc(void)
1464 {
1465         srmmu_name = "ROSS HyperSparc";
1466
1467         init_vac_layout();
1468
1469         is_hypersparc = 1;
1470
1471         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1472         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1473         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1474         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1475         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1476         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1477         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1478
1479         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1480         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1481         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1482         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1483
1484         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1485         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1486         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1487
1488
1489         poke_srmmu = poke_hypersparc;
1490
1491         hypersparc_setup_blockops();
1492 }
1493
1494 static void __init poke_cypress(void)
1495 {
1496         unsigned long mreg = srmmu_get_mmureg();
1497         unsigned long faddr, tagval;
1498         volatile unsigned long cypress_sucks;
1499         volatile unsigned long clear;
1500
1501         clear = srmmu_get_faddr();
1502         clear = srmmu_get_fstatus();
1503
1504         if (!(mreg & CYPRESS_CENABLE)) {
1505                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1506                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1507                                              "sta %%g0, [%0] %2\n\t" : :
1508                                              "r" (faddr), "r" (0x40000),
1509                                              "i" (ASI_M_DATAC_TAG));
1510                 }
1511         } else {
1512                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1513                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1514                                              "=r" (tagval) :
1515                                              "r" (faddr), "r" (0x40000),
1516                                              "i" (ASI_M_DATAC_TAG));
1517
1518                         /* If modified and valid, kick it. */
1519                         if((tagval & 0x60) == 0x60)
1520                                 cypress_sucks = *(unsigned long *)
1521                                                         (0xf0020000 + faddr);
1522                 }
1523         }
1524
1525         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1526         clear = srmmu_get_faddr();
1527         clear = srmmu_get_fstatus();
1528
1529         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1530         srmmu_set_mmureg(mreg);
1531 }
1532
1533 static void __init init_cypress_common(void)
1534 {
1535         init_vac_layout();
1536
1537         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1538         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1539         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1540         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1541         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1542         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1543         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1544
1545         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1546         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1547         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1548         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1549
1550
1551         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1552         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1553         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1554
1555         poke_srmmu = poke_cypress;
1556 }
1557
1558 static void __init init_cypress_604(void)
1559 {
1560         srmmu_name = "ROSS Cypress-604(UP)";
1561         srmmu_modtype = Cypress;
1562         init_cypress_common();
1563 }
1564
1565 static void __init init_cypress_605(unsigned long mrev)
1566 {
1567         srmmu_name = "ROSS Cypress-605(MP)";
1568         if(mrev == 0xe) {
1569                 srmmu_modtype = Cypress_vE;
1570                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1571         } else {
1572                 if(mrev == 0xd) {
1573                         srmmu_modtype = Cypress_vD;
1574                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1575                 } else {
1576                         srmmu_modtype = Cypress;
1577                 }
1578         }
1579         init_cypress_common();
1580 }
1581
1582 static void __init poke_swift(void)
1583 {
1584         unsigned long mreg;
1585
1586         /* Clear any crap from the cache or else... */
1587         swift_flush_cache_all();
1588
1589         /* Enable I & D caches */
1590         mreg = srmmu_get_mmureg();
1591         mreg |= (SWIFT_IE | SWIFT_DE);
1592         /*
1593          * The Swift branch folding logic is completely broken.  At
1594          * trap time, if things are just right, if can mistakenly
1595          * think that a trap is coming from kernel mode when in fact
1596          * it is coming from user mode (it mis-executes the branch in
1597          * the trap code).  So you see things like crashme completely
1598          * hosing your machine which is completely unacceptable.  Turn
1599          * this shit off... nice job Fujitsu.
1600          */
1601         mreg &= ~(SWIFT_BF);
1602         srmmu_set_mmureg(mreg);
1603 }
1604
1605 #define SWIFT_MASKID_ADDR  0x10003018
1606 static void __init init_swift(void)
1607 {
1608         unsigned long swift_rev;
1609
1610         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1611                              "srl %0, 0x18, %0\n\t" :
1612                              "=r" (swift_rev) :
1613                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1614         srmmu_name = "Fujitsu Swift";
1615         switch(swift_rev) {
1616         case 0x11:
1617         case 0x20:
1618         case 0x23:
1619         case 0x30:
1620                 srmmu_modtype = Swift_lots_o_bugs;
1621                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1622                 /*
1623                  * Gee george, I wonder why Sun is so hush hush about
1624                  * this hardware bug... really braindamage stuff going
1625                  * on here.  However I think we can find a way to avoid
1626                  * all of the workaround overhead under Linux.  Basically,
1627                  * any page fault can cause kernel pages to become user
1628                  * accessible (the mmu gets confused and clears some of
1629                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1630                  * horrible eh?  But wait, after extensive testing it appears
1631                  * that if you use pgd_t level large kernel pte's (like the
1632                  * 4MB pages on the Pentium) the bug does not get tripped
1633                  * at all.  This avoids almost all of the major overhead.
1634                  * Welcome to a world where your vendor tells you to,
1635                  * "apply this kernel patch" instead of "sorry for the
1636                  * broken hardware, send it back and we'll give you
1637                  * properly functioning parts"
1638                  */
1639                 break;
1640         case 0x25:
1641         case 0x31:
1642                 srmmu_modtype = Swift_bad_c;
1643                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1644                 /*
1645                  * You see Sun allude to this hardware bug but never
1646                  * admit things directly, they'll say things like,
1647                  * "the Swift chip cache problems" or similar.
1648                  */
1649                 break;
1650         default:
1651                 srmmu_modtype = Swift_ok;
1652                 break;
1653         };
1654
1655         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1656         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1657         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1658         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1659
1660
1661         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1662         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1663         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1664         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1665
1666         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1667         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1668         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1669
1670         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1671
1672         flush_page_for_dma_global = 0;
1673
1674         /*
1675          * Are you now convinced that the Swift is one of the
1676          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1677          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1678          * you examined the microcode of the Swift you'd find
1679          * XXX's all over the place.
1680          */
1681         poke_srmmu = poke_swift;
1682 }
1683
1684 static void turbosparc_flush_cache_all(void)
1685 {
1686         flush_user_windows();
1687         turbosparc_idflash_clear();
1688 }
1689
1690 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1691 {
1692         FLUSH_BEGIN(mm)
1693         flush_user_windows();
1694         turbosparc_idflash_clear();
1695         FLUSH_END
1696 }
1697
1698 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1699 {
1700         struct mm_struct *mm = vma->vm_mm;
1701
1702         FLUSH_BEGIN(mm)
1703         flush_user_windows();
1704         turbosparc_idflash_clear();
1705         FLUSH_END
1706 }
1707
1708 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1709 {
1710         FLUSH_BEGIN(vma->vm_mm)
1711         flush_user_windows();
1712         if (vma->vm_flags & VM_EXEC)
1713                 turbosparc_flush_icache();
1714         turbosparc_flush_dcache();
1715         FLUSH_END
1716 }
1717
1718 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1719 static void turbosparc_flush_page_to_ram(unsigned long page)
1720 {
1721 #ifdef TURBOSPARC_WRITEBACK
1722         volatile unsigned long clear;
1723
1724         if (srmmu_hwprobe(page))
1725                 turbosparc_flush_page_cache(page);
1726         clear = srmmu_get_fstatus();
1727 #endif
1728 }
1729
1730 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1731 {
1732 }
1733
1734 static void turbosparc_flush_page_for_dma(unsigned long page)
1735 {
1736         turbosparc_flush_dcache();
1737 }
1738
1739 static void turbosparc_flush_tlb_all(void)
1740 {
1741         srmmu_flush_whole_tlb();
1742 }
1743
1744 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1745 {
1746         FLUSH_BEGIN(mm)
1747         srmmu_flush_whole_tlb();
1748         FLUSH_END
1749 }
1750
1751 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1752 {
1753         struct mm_struct *mm = vma->vm_mm;
1754
1755         FLUSH_BEGIN(mm)
1756         srmmu_flush_whole_tlb();
1757         FLUSH_END
1758 }
1759
1760 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1761 {
1762         FLUSH_BEGIN(vma->vm_mm)
1763         srmmu_flush_whole_tlb();
1764         FLUSH_END
1765 }
1766
1767
1768 static void __init poke_turbosparc(void)
1769 {
1770         unsigned long mreg = srmmu_get_mmureg();
1771         unsigned long ccreg;
1772
1773         /* Clear any crap from the cache or else... */
1774         turbosparc_flush_cache_all();
1775         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1776         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1777         srmmu_set_mmureg(mreg);
1778
1779         ccreg = turbosparc_get_ccreg();
1780
1781 #ifdef TURBOSPARC_WRITEBACK
1782         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1783         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1784                         /* Write-back D-cache, emulate VLSI
1785                          * abortion number three, not number one */
1786 #else
1787         /* For now let's play safe, optimize later */
1788         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1789                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1790         ccreg &= ~(TURBOSPARC_uS2);
1791                         /* Emulate VLSI abortion number three, not number one */
1792 #endif
1793
1794         switch (ccreg & 7) {
1795         case 0: /* No SE cache */
1796         case 7: /* Test mode */
1797                 break;
1798         default:
1799                 ccreg |= (TURBOSPARC_SCENABLE);
1800         }
1801         turbosparc_set_ccreg (ccreg);
1802
1803         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1804         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1805         srmmu_set_mmureg(mreg);
1806 }
1807
1808 static void __init init_turbosparc(void)
1809 {
1810         srmmu_name = "Fujitsu TurboSparc";
1811         srmmu_modtype = TurboSparc;
1812
1813         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1814         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1815         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1816         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1817
1818         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1819         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1820         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1821         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1822
1823         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1824
1825         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1826         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1827
1828         poke_srmmu = poke_turbosparc;
1829 }
1830
1831 static void __init poke_tsunami(void)
1832 {
1833         unsigned long mreg = srmmu_get_mmureg();
1834
1835         tsunami_flush_icache();
1836         tsunami_flush_dcache();
1837         mreg &= ~TSUNAMI_ITD;
1838         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1839         srmmu_set_mmureg(mreg);
1840 }
1841
1842 static void __init init_tsunami(void)
1843 {
1844         /*
1845          * Tsunami's pretty sane, Sun and TI actually got it
1846          * somewhat right this time.  Fujitsu should have
1847          * taken some lessons from them.
1848          */
1849
1850         srmmu_name = "TI Tsunami";
1851         srmmu_modtype = Tsunami;
1852
1853         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1854         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1855         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1856         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1857
1858
1859         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1860         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1861         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1862         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1863
1864         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1865         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1866         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1867
1868         poke_srmmu = poke_tsunami;
1869
1870         tsunami_setup_blockops();
1871 }
1872
1873 static void __init poke_viking(void)
1874 {
1875         unsigned long mreg = srmmu_get_mmureg();
1876         static int smp_catch;
1877
1878         if(viking_mxcc_present) {
1879                 unsigned long mxcc_control = mxcc_get_creg();
1880
1881                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1882                 mxcc_control &= ~(MXCC_CTL_RRC);
1883                 mxcc_set_creg(mxcc_control);
1884
1885                 /*
1886                  * We don't need memory parity checks.
1887                  * XXX This is a mess, have to dig out later. ecd.
1888                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1889                  */
1890
1891                 /* We do cache ptables on MXCC. */
1892                 mreg |= VIKING_TCENABLE;
1893         } else {
1894                 unsigned long bpreg;
1895
1896                 mreg &= ~(VIKING_TCENABLE);
1897                 if(smp_catch++) {
1898                         /* Must disable mixed-cmd mode here for other cpu's. */
1899                         bpreg = viking_get_bpreg();
1900                         bpreg &= ~(VIKING_ACTION_MIX);
1901                         viking_set_bpreg(bpreg);
1902
1903                         /* Just in case PROM does something funny. */
1904                         msi_set_sync();
1905                 }
1906         }
1907
1908         mreg |= VIKING_SPENABLE;
1909         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1910         mreg |= VIKING_SBENABLE;
1911         mreg &= ~(VIKING_ACENABLE);
1912         srmmu_set_mmureg(mreg);
1913
1914 #ifdef CONFIG_SMP
1915         /* Avoid unnecessary cross calls. */
1916         BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
1917         BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
1918         BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
1919         BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
1920         BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
1921         BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
1922         BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
1923         btfixup();
1924 #endif
1925 }
1926
1927 static void __init init_viking(void)
1928 {
1929         unsigned long mreg = srmmu_get_mmureg();
1930
1931         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1932         if(mreg & VIKING_MMODE) {
1933                 srmmu_name = "TI Viking";
1934                 viking_mxcc_present = 0;
1935                 msi_set_sync();
1936
1937                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1938                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1939                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1940
1941                 /*
1942                  * We need this to make sure old viking takes no hits
1943                  * on it's cache for dma snoops to workaround the
1944                  * "load from non-cacheable memory" interrupt bug.
1945                  * This is only necessary because of the new way in
1946                  * which we use the IOMMU.
1947                  */
1948                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1949
1950                 flush_page_for_dma_global = 0;
1951         } else {
1952                 srmmu_name = "TI Viking/MXCC";
1953                 viking_mxcc_present = 1;
1954
1955                 srmmu_cache_pagetables = 1;
1956
1957                 /* MXCC vikings lack the DMA snooping bug. */
1958                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1959         }
1960
1961         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1962         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1963         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1964         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1965
1966 #ifdef CONFIG_SMP
1967         if (sparc_cpu_model == sun4d) {
1968                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1969                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1970                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1971                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1972         } else
1973 #endif
1974         {
1975                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1976                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1977                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1978                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1979         }
1980
1981         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1982         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1983
1984         poke_srmmu = poke_viking;
1985 }
1986
1987 /* Probe for the srmmu chip version. */
1988 static void __init get_srmmu_type(void)
1989 {
1990         unsigned long mreg, psr;
1991         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1992
1993         srmmu_modtype = SRMMU_INVAL_MOD;
1994         hwbug_bitmask = 0;
1995
1996         mreg = srmmu_get_mmureg(); psr = get_psr();
1997         mod_typ = (mreg & 0xf0000000) >> 28;
1998         mod_rev = (mreg & 0x0f000000) >> 24;
1999         psr_typ = (psr >> 28) & 0xf;
2000         psr_vers = (psr >> 24) & 0xf;
2001
2002         /* First, check for HyperSparc or Cypress. */
2003         if(mod_typ == 1) {
2004                 switch(mod_rev) {
2005                 case 7:
2006                         /* UP or MP Hypersparc */
2007                         init_hypersparc();
2008                         break;
2009                 case 0:
2010                 case 2:
2011                         /* Uniprocessor Cypress */
2012                         init_cypress_604();
2013                         break;
2014                 case 10:
2015                 case 11:
2016                 case 12:
2017                         /* _REALLY OLD_ Cypress MP chips... */
2018                 case 13:
2019                 case 14:
2020                 case 15:
2021                         /* MP Cypress mmu/cache-controller */
2022                         init_cypress_605(mod_rev);
2023                         break;
2024                 default:
2025                         /* Some other Cypress revision, assume a 605. */
2026                         init_cypress_605(mod_rev);
2027                         break;
2028                 };
2029                 return;
2030         }
2031
2032         /*
2033          * Now Fujitsu TurboSparc. It might happen that it is
2034          * in Swift emulation mode, so we will check later...
2035          */
2036         if (psr_typ == 0 && psr_vers == 5) {
2037                 init_turbosparc();
2038                 return;
2039         }
2040
2041         /* Next check for Fujitsu Swift. */
2042         if(psr_typ == 0 && psr_vers == 4) {
2043                 int cpunode;
2044                 char node_str[128];
2045
2046                 /* Look if it is not a TurboSparc emulating Swift... */
2047                 cpunode = prom_getchild(prom_root_node);
2048                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2049                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2050                         if(!strcmp(node_str, "cpu")) {
2051                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2052                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2053                                         init_turbosparc();
2054                                         return;
2055                                 }
2056                                 break;
2057                         }
2058                 }
2059
2060                 init_swift();
2061                 return;
2062         }
2063
2064         /* Now the Viking family of srmmu. */
2065         if(psr_typ == 4 &&
2066            ((psr_vers == 0) ||
2067             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2068                 init_viking();
2069                 return;
2070         }
2071
2072         /* Finally the Tsunami. */
2073         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2074                 init_tsunami();
2075                 return;
2076         }
2077
2078         /* Oh well */
2079         srmmu_is_bad();
2080 }
2081
2082 /* don't laugh, static pagetables */
2083 static void srmmu_check_pgt_cache(int low, int high)
2084 {
2085 }
2086
2087 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2088         tsetup_mmu_patchme, rtrap_mmu_patchme;
2089
2090 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2091         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2092
2093 extern unsigned long srmmu_fault;
2094
2095 #define PATCH_BRANCH(insn, dest) do { \
2096                 iaddr = &(insn); \
2097                 daddr = &(dest); \
2098                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2099         } while(0)
2100
2101 static void __init patch_window_trap_handlers(void)
2102 {
2103         unsigned long *iaddr, *daddr;
2104
2105         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2106         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2107         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2108         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2109         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2110         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2111         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2112 }
2113
2114 #ifdef CONFIG_SMP
2115 /* Local cross-calls. */
2116 static void smp_flush_page_for_dma(unsigned long page)
2117 {
2118         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2119         local_flush_page_for_dma(page);
2120 }
2121
2122 #endif
2123
2124 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2125 {
2126         return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2127 }
2128
2129 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2130 {
2131         return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2132 }
2133
2134 /* Load up routines and constants for sun4m and sun4d mmu */
2135 void __init ld_mmu_srmmu(void)
2136 {
2137         extern void ld_mmu_iommu(void);
2138         extern void ld_mmu_iounit(void);
2139         extern void ___xchg32_sun4md(void);
2140
2141         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2142         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2143         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2144
2145         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2146         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2147
2148         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2149         BTFIXUPSET_INT(page_shared, pgprot_val(SRMMU_PAGE_SHARED));
2150         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2151         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2152         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2153         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2154         pg_iobits = SRMMU_VALID | SRMMU_WRITE | SRMMU_REF;
2155
2156         /* Functions */
2157 #ifndef CONFIG_SMP
2158         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2159 #endif
2160         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2161
2162         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2163         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2164
2165         BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2166         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2167         BTFIXUPSET_CALL(pgd_page, srmmu_pgd_page, BTFIXUPCALL_NORM);
2168
2169         BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2170
2171         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2172         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2173
2174         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2175         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2176         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2177
2178         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2179         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2180         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2181         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2182
2183         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2184         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2185         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2186         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2187         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2188         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2189
2190         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2191         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2192         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2193
2194         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2195         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2196         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2197         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2198         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2199         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2200         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2201         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2202
2203         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2204         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2205         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2206         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2207         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2208         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2209         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2210         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2211         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2212         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2213         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2214         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2215
2216         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2217         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2218
2219         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2220         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2221         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2222
2223         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2224
2225         BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2226         BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2227
2228         BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2229         BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2230
2231         get_srmmu_type();
2232         patch_window_trap_handlers();
2233
2234 #ifdef CONFIG_SMP
2235         /* El switcheroo... */
2236
2237         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2238         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2239         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2240         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2241         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2242         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2243         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2244         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2245         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2246         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2247         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2248
2249         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2250         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2251         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2252         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2253         if (sparc_cpu_model != sun4d) {
2254                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2255                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2256                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2257                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2258         }
2259         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2260         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2261         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2262 #endif
2263
2264         if (sparc_cpu_model == sun4d)
2265                 ld_mmu_iounit();
2266         else
2267                 ld_mmu_iommu();
2268 #ifdef CONFIG_SMP
2269         if (sparc_cpu_model == sun4d)
2270                 sun4d_init_smp();
2271         else
2272                 sun4m_init_smp();
2273 #endif
2274 }