arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/slab.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/pagemap.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/bitext.h>
  24 #include <asm/page.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/io.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/sbus.h>
  36 #include <asm/asi.h>
  37 #include <asm/msi.h>
  38 #include <asm/a.out.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/io-unit.h>
  41 #include <asm/cacheflush.h>
  42 #include <asm/tlbflush.h>
  43
  44 /* Now the cpu specific definitions. */
  45 #include <asm/viking.h>
  46 #include <asm/mxcc.h>
  47 #include <asm/ross.h>
  48 #include <asm/tsunami.h>
  49 #include <asm/swift.h>
  50 #include <asm/turbosparc.h>
  51
  52 #include <asm/btfixup.h>
  53
  54 enum mbus_module srmmu_modtype;
  55 unsigned int hwbug_bitmask;
  56 int vac_cache_size;
  57 int vac_line_size;
  58
  59 extern struct resource sparc_iomap;
  60
  61 extern unsigned long last_valid_pfn;
  62
  63 extern unsigned long page_kernel;
  64
  65 pgd_t *srmmu_swapper_pg_dir;
  66
  67 #ifdef CONFIG_SMP
  68 #define FLUSH_BEGIN(mm)
  69 #define FLUSH_END
  70 #else
  71 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  72 #define FLUSH_END       }
  73 #endif
  74
  75 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  76 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  77
  78 int flush_page_for_dma_global = 1;
  79
  80 #ifdef CONFIG_SMP
  81 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  82 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  83 #endif
  84
  85 char *srmmu_name;
  86
  87 ctxd_t *srmmu_ctx_table_phys;
  88 ctxd_t *srmmu_context_table;
  89
  90 int viking_mxcc_present;
  91 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  92
  93 int is_hypersparc;
  94
  95 /*
  96  * In general all page table modifications should use the V8 atomic
  97  * swap instruction.  This insures the mmu and the cpu are in sync
  98  * with respect to ref/mod bits in the page tables.
  99  */
 100 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
 101 {
 102         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 103         return value;
 104 }
 105
 106 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 107 {
 108         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 109 }
 110
 111 /* The very generic SRMMU page table operations. */
 112 static inline int srmmu_device_memory(unsigned long x)
 113 {
 114         return ((x & 0xF0000000) != 0);
 115 }
 116
 117 int srmmu_cache_pagetables;
 118
 119 /* these will be initialized in srmmu_nocache_calcsize() */
 120 unsigned long srmmu_nocache_size;
 121 unsigned long srmmu_nocache_end;
 122
 123 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 124 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 125
 126 /* The context table is a nocache user with the biggest alignment needs. */
 127 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 128
 129 void *srmmu_nocache_pool;
 130 void *srmmu_nocache_bitmap;
 131 static struct bit_map srmmu_nocache_map;
 132
 133 static unsigned long srmmu_pte_pfn(pte_t pte)
 134 {
 135         if (srmmu_device_memory(pte_val(pte))) {
 136                 /* Just return something that will cause
 137                  * pfn_valid() to return false.  This makes
 138                  * copy_one_pte() to just directly copy to
 139                  * PTE over.
 140                  */
 141                 return ~0UL;
 142         }
 143         return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
 144 }
 145
 146 static struct page *srmmu_pmd_page(pmd_t pmd)
 147 {
 148
 149         if (srmmu_device_memory(pmd_val(pmd)))
 150                 BUG();
 151         return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
 152 }
 153
 154 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 155 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 156
 157
 158 static inline int srmmu_pte_none(pte_t pte)
 159 { return !(pte_val(pte) & 0xFFFFFFF); }
 160
 161 static inline int srmmu_pte_present(pte_t pte)
 162 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 163
 164 static inline void srmmu_pte_clear(pte_t *ptep)
 165 { srmmu_set_pte(ptep, __pte(0)); }
 166
 167 static inline int srmmu_pmd_none(pmd_t pmd)
 168 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 169
 170 static inline int srmmu_pmd_bad(pmd_t pmd)
 171 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 172
 173 static inline int srmmu_pmd_present(pmd_t pmd)
 174 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 175
 176 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
 177         int i;
 178         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
 179                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
 180 }
 181
 182 static inline int srmmu_pgd_none(pgd_t pgd)
 183 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 184
 185 static inline int srmmu_pgd_bad(pgd_t pgd)
 186 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 187
 188 static inline int srmmu_pgd_present(pgd_t pgd)
 189 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 190
 191 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 192 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 193
 194 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 195 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 196
 197 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 198 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 199
 200 static inline pte_t srmmu_pte_mkold(pte_t pte)
 201 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 202
 203 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 204 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 205
 206 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 207 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 208
 209 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 210 { return __pte(pte_val(pte) | SRMMU_REF);}
 211
 212 /*
 213  * Conversion functions: convert a page and protection to a page entry,
 214  * and a page entry and page directory to the page they refer to.
 215  */
 216 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 217 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 218
 219 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 220 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 221
 222 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 223 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 224
 225 /* XXX should we hyper_flush_whole_icache here - Anton */
 226 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 227 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 228
 229 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 230 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 231
 232 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 233 {
 234         unsigned long ptp;      /* Physical address, shifted right by 4 */
 235         int i;
 236
 237         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 238         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 239                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 240                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 241         }
 242 }
 243
 244 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 245 {
 246         unsigned long ptp;      /* Physical address, shifted right by 4 */
 247         int i;
 248
 249         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 250         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 251                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 252                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 253         }
 254 }
 255
 256 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 257 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 258
 259 /* to find an entry in a top-level page table... */
 260 extern inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 261 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 262
 263 /* Find an entry in the second-level page table.. */
 264 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 265 {
 266         return (pmd_t *) srmmu_pgd_page(*dir) +
 267             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 268 }
 269
 270 /* Find an entry in the third-level page table.. */
 271 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 272 {
 273         void *pte;
 274
 275         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 276         return (pte_t *) pte +
 277             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 278 }
 279
 280 static unsigned long srmmu_swp_type(swp_entry_t entry)
 281 {
 282         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 283 }
 284
 285 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 286 {
 287         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 288 }
 289
 290 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 291 {
 292         return (swp_entry_t) {
 293                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 294                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 295 }
 296
 297 /*
 298  * size: bytes to allocate in the nocache area.
 299  * align: bytes, number to align at.
 300  * Returns the virtual address of the allocated area.
 301  */
 302 static unsigned long __srmmu_get_nocache(int size, int align)
 303 {
 304         int offset;
 305
 306         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 307                 printk("Size 0x%x too small for nocache request\n", size);
 308                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 309         }
 310         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 311                 printk("Size 0x%x unaligned int nocache request\n", size);
 312                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 313         }
 314         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 315
 316         offset = bit_map_string_get(&srmmu_nocache_map,
 317                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 318                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 319         if (offset == -1) {
 320                 printk("srmmu: out of nocache %d: %d/%d\n",
 321                     size, (int) srmmu_nocache_size,
 322                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 323                 return 0;
 324         }
 325
 326         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 327 }
 328
 329 unsigned inline long srmmu_get_nocache(int size, int align)
 330 {
 331         unsigned long tmp;
 332
 333         tmp = __srmmu_get_nocache(size, align);
 334
 335         if (tmp)
 336                 memset((void *)tmp, 0, size);
 337
 338         return tmp;
 339 }
 340
 341 void srmmu_free_nocache(unsigned long vaddr, int size)
 342 {
 343         int offset;
 344
 345         if (vaddr < SRMMU_NOCACHE_VADDR) {
 346                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 347                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 348                 BUG();
 349         }
 350         if (vaddr+size > srmmu_nocache_end) {
 351                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 352                     vaddr, srmmu_nocache_end);
 353                 BUG();
 354         }
 355         if (size & (size-1)) {
 356                 printk("Size 0x%x is not a power of 2\n", size);
 357                 BUG();
 358         }
 359         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 360                 printk("Size 0x%x is too small\n", size);
 361                 BUG();
 362         }
 363         if (vaddr & (size-1)) {
 364                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 365                 BUG();
 366         }
 367
 368         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 369         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 370
 371         bit_map_clear(&srmmu_nocache_map, offset, size);
 372 }
 373
 374 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);
 375
 376 extern unsigned long probe_memory(void);        /* in fault.c */
 377
 378 /*
 379  * Reserve nocache dynamically proportionally to the amount of
 380  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 381  */
 382 void srmmu_nocache_calcsize(void)
 383 {
 384         unsigned long sysmemavail = probe_memory() / 1024;
 385         int srmmu_nocache_npages;
 386
 387         srmmu_nocache_npages =
 388                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 389
 390  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 391         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 392         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 393                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 394
 395         /* anything above 1280 blows up */
 396         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 397                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 398
 399         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 400         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 401 }
 402
 403 void srmmu_nocache_init(void)
 404 {
 405         unsigned int bitmap_bits;
 406         pgd_t *pgd;
 407         pmd_t *pmd;
 408         pte_t *pte;
 409         unsigned long paddr, vaddr;
 410         unsigned long pteval;
 411
 412         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 413
 414         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 415                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 416         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 417
 418         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 419         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 420
 421         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 422         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 423         init_mm.pgd = srmmu_swapper_pg_dir;
 424
 425         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 426
 427         paddr = __pa((unsigned long)srmmu_nocache_pool);
 428         vaddr = SRMMU_NOCACHE_VADDR;
 429
 430         while (vaddr < srmmu_nocache_end) {
 431                 pgd = pgd_offset_k(vaddr);
 432                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 433                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 434
 435                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 436
 437                 if (srmmu_cache_pagetables)
 438                         pteval |= SRMMU_CACHE;
 439
 440                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 441
 442                 vaddr += PAGE_SIZE;
 443                 paddr += PAGE_SIZE;
 444         }
 445
 446         flush_cache_all();
 447         flush_tlb_all();
 448 }
 449
 450 static inline pgd_t *srmmu_get_pgd_fast(void)
 451 {
 452         pgd_t *pgd = NULL;
 453
 454         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 455         if (pgd) {
 456                 pgd_t *init = pgd_offset_k(0);
 457                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 458                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 459                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 460         }
 461
 462         return pgd;
 463 }
 464
 465 static void srmmu_free_pgd_fast(pgd_t *pgd)
 466 {
 467         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 468 }
 469
 470 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 471 {
 472         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 473 }
 474
 475 static void srmmu_pmd_free(pmd_t * pmd)
 476 {
 477         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 478 }
 479
 480 /*
 481  * Hardware needs alignment to 256 only, but we align to whole page size
 482  * to reduce fragmentation problems due to the buddy principle.
 483  * XXX Provide actual fragmentation statistics in /proc.
 484  *
 485  * Alignments up to the page size are the same for physical and virtual
 486  * addresses of the nocache area.
 487  */
 488 static pte_t *
 489 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 490 {
 491         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 492 }
 493
 494 static struct page *
 495 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 496 {
 497         unsigned long pte;
 498
 499         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 500                 return NULL;
 501         return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 502 }
 503
 504 static void srmmu_free_pte_fast(pte_t *pte)
 505 {
 506         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 507 }
 508
 509 static void srmmu_pte_free(struct page *pte)
 510 {
 511         unsigned long p;
 512
 513         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 514         if (p == 0)
 515                 BUG();
 516         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 517         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 518         srmmu_free_nocache(p, PTE_SIZE);
 519 }
 520
 521 /*
 522  */
 523 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 524 {
 525         struct ctx_list *ctxp;
 526
 527         ctxp = ctx_free.next;
 528         if(ctxp != &ctx_free) {
 529                 remove_from_ctx_list(ctxp);
 530                 add_to_used_ctxlist(ctxp);
 531                 mm->context = ctxp->ctx_number;
 532                 ctxp->ctx_mm = mm;
 533                 return;
 534         }
 535         ctxp = ctx_used.next;
 536         if(ctxp->ctx_mm == old_mm)
 537                 ctxp = ctxp->next;
 538         if(ctxp == &ctx_used)
 539                 panic("out of mmu contexts");
 540         flush_cache_mm(ctxp->ctx_mm);
 541         flush_tlb_mm(ctxp->ctx_mm);
 542         remove_from_ctx_list(ctxp);
 543         add_to_used_ctxlist(ctxp);
 544         ctxp->ctx_mm->context = NO_CONTEXT;
 545         ctxp->ctx_mm = mm;
 546         mm->context = ctxp->ctx_number;
 547 }
 548
 549 static inline void free_context(int context)
 550 {
 551         struct ctx_list *ctx_old;
 552
 553         ctx_old = ctx_list_pool + context;
 554         remove_from_ctx_list(ctx_old);
 555         add_to_free_ctxlist(ctx_old);
 556 }
 557
 558
 559 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 560     struct task_struct *tsk, int cpu)
 561 {
 562         if(mm->context == NO_CONTEXT) {
 563                 spin_lock(&srmmu_context_spinlock);
 564                 alloc_context(old_mm, mm);
 565                 spin_unlock(&srmmu_context_spinlock);
 566                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 567         }
 568
 569         if (is_hypersparc)
 570                 hyper_flush_whole_icache();
 571
 572         srmmu_set_context(mm->context);
 573 }
 574
 575 /* Low level IO area allocation on the SRMMU. */
 576 static inline void srmmu_mapioaddr(unsigned long physaddr,
 577     unsigned long virt_addr, int bus_type)
 578 {
 579         pgd_t *pgdp;
 580         pmd_t *pmdp;
 581         pte_t *ptep;
 582         unsigned long tmp;
 583
 584         physaddr &= PAGE_MASK;
 585         pgdp = pgd_offset_k(virt_addr);
 586         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 587         ptep = srmmu_pte_offset(pmdp, virt_addr);
 588         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 589
 590         /*
 591          * I need to test whether this is consistent over all
 592          * sun4m's.  The bus_type represents the upper 4 bits of
 593          * 36-bit physical address on the I/O space lines...
 594          */
 595         tmp |= (bus_type << 28);
 596         tmp |= SRMMU_PRIV;
 597         __flush_page_to_ram(virt_addr);
 598         srmmu_set_pte(ptep, __pte(tmp));
 599 }
 600
 601 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 602     unsigned long xva, unsigned int len)
 603 {
 604         while (len != 0) {
 605                 len -= PAGE_SIZE;
 606                 srmmu_mapioaddr(xpa, xva, bus);
 607                 xva += PAGE_SIZE;
 608                 xpa += PAGE_SIZE;
 609         }
 610         flush_tlb_all();
 611 }
 612
 613 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 614 {
 615         pgd_t *pgdp;
 616         pmd_t *pmdp;
 617         pte_t *ptep;
 618
 619         pgdp = pgd_offset_k(virt_addr);
 620         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 621         ptep = srmmu_pte_offset(pmdp, virt_addr);
 622
 623         /* No need to flush uncacheable page. */
 624         srmmu_pte_clear(ptep);
 625 }
 626
 627 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 628 {
 629         while (len != 0) {
 630                 len -= PAGE_SIZE;
 631                 srmmu_unmapioaddr(virt_addr);
 632                 virt_addr += PAGE_SIZE;
 633         }
 634         flush_tlb_all();
 635 }
 636
 637 /*
 638  * On the SRMMU we do not have the problems with limited tlb entries
 639  * for mapping kernel pages, so we just take things from the free page
 640  * pool.  As a side effect we are putting a little too much pressure
 641  * on the gfp() subsystem.  This setup also makes the logic of the
 642  * iommu mapping code a lot easier as we can transparently handle
 643  * mappings on the kernel stack without any special code as we did
 644  * need on the sun4c.
 645  */
 646 struct thread_info *srmmu_alloc_thread_info(void)
 647 {
 648         struct thread_info *ret;
 649
 650         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 651                                                      THREAD_INFO_ORDER);
 652 #ifdef CONFIG_DEBUG_STACK_USAGE
 653         if (ret)
 654                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 655 #endif /* DEBUG_STACK_USAGE */
 656
 657         return ret;
 658 }
 659
 660 static void srmmu_free_thread_info(struct thread_info *ti)
 661 {
 662         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 663 }
 664
 665 /* tsunami.S */
 666 extern void tsunami_flush_cache_all(void);
 667 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 668 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 669 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 670 extern void tsunami_flush_page_to_ram(unsigned long page);
 671 extern void tsunami_flush_page_for_dma(unsigned long page);
 672 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 673 extern void tsunami_flush_tlb_all(void);
 674 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 675 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 676 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 677 extern void tsunami_setup_blockops(void);
 678
 679 /*
 680  * Workaround, until we find what's going on with Swift. When low on memory,
 681  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 682  * out it is already in page tables/ fault again on the same instruction.
 683  * I really don't understand it, have checked it and contexts
 684  * are right, flush_tlb_all is done as well, and it faults again...
 685  * Strange. -jj
 686  *
 687  * The following code is a deadwood that may be necessary when
 688  * we start to make precise page flushes again. --zaitcev
 689  */
 690 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 691 {
 692 #if 0
 693         static unsigned long last;
 694         unsigned int val;
 695         /* unsigned int n; */
 696
 697         if (address == last) {
 698                 val = srmmu_hwprobe(address);
 699                 if (val != 0 && pte_val(pte) != val) {
 700                         printk("swift_update_mmu_cache: "
 701                             "addr %lx put %08x probed %08x from %p\n",
 702                             address, pte_val(pte), val,
 703                             __builtin_return_address(0));
 704                         srmmu_flush_whole_tlb();
 705                 }
 706         }
 707         last = address;
 708 #endif
 709 }
 710
 711 /* swift.S */
 712 extern void swift_flush_cache_all(void);
 713 extern void swift_flush_cache_mm(struct mm_struct *mm);
 714 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 715                                     unsigned long start, unsigned long end);
 716 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 717 extern void swift_flush_page_to_ram(unsigned long page);
 718 extern void swift_flush_page_for_dma(unsigned long page);
 719 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 720 extern void swift_flush_tlb_all(void);
 721 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 722 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 723                                   unsigned long start, unsigned long end);
 724 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 725
 726 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 727 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 728 {
 729         int cctx, ctx1;
 730
 731         page &= PAGE_MASK;
 732         if ((ctx1 = vma->vm_mm->context) != -1) {
 733                 cctx = srmmu_get_context();
 734 /* Is context # ever different from current context? P3 */
 735                 if (cctx != ctx1) {
 736                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 737                         srmmu_set_context(ctx1);
 738                         swift_flush_page(page);
 739                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 740                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 741                         srmmu_set_context(cctx);
 742                 } else {
 743                          /* Rm. prot. bits from virt. c. */
 744                         /* swift_flush_cache_all(); */
 745                         /* swift_flush_cache_page(vma, page); */
 746                         swift_flush_page(page);
 747
 748                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 749                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 750                         /* same as above: srmmu_flush_tlb_page() */
 751                 }
 752         }
 753 }
 754 #endif
 755
 756 /*
 757  * The following are all MBUS based SRMMU modules, and therefore could
 758  * be found in a multiprocessor configuration.  On the whole, these
 759  * chips seems to be much more touchy about DVMA and page tables
 760  * with respect to cache coherency.
 761  */
 762
 763 /* Cypress flushes. */
 764 static void cypress_flush_cache_all(void)
 765 {
 766         volatile unsigned long cypress_sucks;
 767         unsigned long faddr, tagval;
 768
 769         flush_user_windows();
 770         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 771                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 772                                      "=r" (tagval) :
 773                                      "r" (faddr), "r" (0x40000),
 774                                      "i" (ASI_M_DATAC_TAG));
 775
 776                 /* If modified and valid, kick it. */
 777                 if((tagval & 0x60) == 0x60)
 778                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 779         }
 780 }
 781
 782 static void cypress_flush_cache_mm(struct mm_struct *mm)
 783 {
 784         register unsigned long a, b, c, d, e, f, g;
 785         unsigned long flags, faddr;
 786         int octx;
 787
 788         FLUSH_BEGIN(mm)
 789         flush_user_windows();
 790         local_irq_save(flags);
 791         octx = srmmu_get_context();
 792         srmmu_set_context(mm->context);
 793         a = 0x20; b = 0x40; c = 0x60;
 794         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 795
 796         faddr = (0x10000 - 0x100);
 797         goto inside;
 798         do {
 799                 faddr -= 0x100;
 800         inside:
 801                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 802                                      "sta %%g0, [%0 + %2] %1\n\t"
 803                                      "sta %%g0, [%0 + %3] %1\n\t"
 804                                      "sta %%g0, [%0 + %4] %1\n\t"
 805                                      "sta %%g0, [%0 + %5] %1\n\t"
 806                                      "sta %%g0, [%0 + %6] %1\n\t"
 807                                      "sta %%g0, [%0 + %7] %1\n\t"
 808                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 809                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 810                                      "r" (a), "r" (b), "r" (c), "r" (d),
 811                                      "r" (e), "r" (f), "r" (g));
 812         } while(faddr);
 813         srmmu_set_context(octx);
 814         local_irq_restore(flags);
 815         FLUSH_END
 816 }
 817
 818 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 819 {
 820         struct mm_struct *mm = vma->vm_mm;
 821         register unsigned long a, b, c, d, e, f, g;
 822         unsigned long flags, faddr;
 823         int octx;
 824
 825         FLUSH_BEGIN(mm)
 826         flush_user_windows();
 827         local_irq_save(flags);
 828         octx = srmmu_get_context();
 829         srmmu_set_context(mm->context);
 830         a = 0x20; b = 0x40; c = 0x60;
 831         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 832
 833         start &= SRMMU_REAL_PMD_MASK;
 834         while(start < end) {
 835                 faddr = (start + (0x10000 - 0x100));
 836                 goto inside;
 837                 do {
 838                         faddr -= 0x100;
 839                 inside:
 840                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 841                                              "sta %%g0, [%0 + %2] %1\n\t"
 842                                              "sta %%g0, [%0 + %3] %1\n\t"
 843                                              "sta %%g0, [%0 + %4] %1\n\t"
 844                                              "sta %%g0, [%0 + %5] %1\n\t"
 845                                              "sta %%g0, [%0 + %6] %1\n\t"
 846                                              "sta %%g0, [%0 + %7] %1\n\t"
 847                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 848                                              "r" (faddr),
 849                                              "i" (ASI_M_FLUSH_SEG),
 850                                              "r" (a), "r" (b), "r" (c), "r" (d),
 851                                              "r" (e), "r" (f), "r" (g));
 852                 } while (faddr != start);
 853                 start += SRMMU_REAL_PMD_SIZE;
 854         }
 855         srmmu_set_context(octx);
 856         local_irq_restore(flags);
 857         FLUSH_END
 858 }
 859
 860 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 861 {
 862         register unsigned long a, b, c, d, e, f, g;
 863         struct mm_struct *mm = vma->vm_mm;
 864         unsigned long flags, line;
 865         int octx;
 866
 867         FLUSH_BEGIN(mm)
 868         flush_user_windows();
 869         local_irq_save(flags);
 870         octx = srmmu_get_context();
 871         srmmu_set_context(mm->context);
 872         a = 0x20; b = 0x40; c = 0x60;
 873         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 874
 875         page &= PAGE_MASK;
 876         line = (page + PAGE_SIZE) - 0x100;
 877         goto inside;
 878         do {
 879                 line -= 0x100;
 880         inside:
 881                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 882                                              "sta %%g0, [%0 + %2] %1\n\t"
 883                                              "sta %%g0, [%0 + %3] %1\n\t"
 884                                              "sta %%g0, [%0 + %4] %1\n\t"
 885                                              "sta %%g0, [%0 + %5] %1\n\t"
 886                                              "sta %%g0, [%0 + %6] %1\n\t"
 887                                              "sta %%g0, [%0 + %7] %1\n\t"
 888                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 889                                              "r" (line),
 890                                              "i" (ASI_M_FLUSH_PAGE),
 891                                              "r" (a), "r" (b), "r" (c), "r" (d),
 892                                              "r" (e), "r" (f), "r" (g));
 893         } while(line != page);
 894         srmmu_set_context(octx);
 895         local_irq_restore(flags);
 896         FLUSH_END
 897 }
 898
 899 /* Cypress is copy-back, at least that is how we configure it. */
 900 static void cypress_flush_page_to_ram(unsigned long page)
 901 {
 902         register unsigned long a, b, c, d, e, f, g;
 903         unsigned long line;
 904
 905         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 906         page &= PAGE_MASK;
 907         line = (page + PAGE_SIZE) - 0x100;
 908         goto inside;
 909         do {
 910                 line -= 0x100;
 911         inside:
 912                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 913                                      "sta %%g0, [%0 + %2] %1\n\t"
 914                                      "sta %%g0, [%0 + %3] %1\n\t"
 915                                      "sta %%g0, [%0 + %4] %1\n\t"
 916                                      "sta %%g0, [%0 + %5] %1\n\t"
 917                                      "sta %%g0, [%0 + %6] %1\n\t"
 918                                      "sta %%g0, [%0 + %7] %1\n\t"
 919                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 920                                      "r" (line),
 921                                      "i" (ASI_M_FLUSH_PAGE),
 922                                      "r" (a), "r" (b), "r" (c), "r" (d),
 923                                      "r" (e), "r" (f), "r" (g));
 924         } while(line != page);
 925 }
 926
 927 /* Cypress is also IO cache coherent. */
 928 static void cypress_flush_page_for_dma(unsigned long page)
 929 {
 930 }
 931
 932 /* Cypress has unified L2 VIPT, from which both instructions and data
 933  * are stored.  It does not have an onboard icache of any sort, therefore
 934  * no flush is necessary.
 935  */
 936 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 937 {
 938 }
 939
 940 static void cypress_flush_tlb_all(void)
 941 {
 942         srmmu_flush_whole_tlb();
 943 }
 944
 945 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 946 {
 947         FLUSH_BEGIN(mm)
 948         __asm__ __volatile__(
 949         "lda    [%0] %3, %%g5\n\t"
 950         "sta    %2, [%0] %3\n\t"
 951         "sta    %%g0, [%1] %4\n\t"
 952         "sta    %%g5, [%0] %3\n"
 953         : /* no outputs */
 954         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 955           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 956         : "g5");
 957         FLUSH_END
 958 }
 959
 960 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 961 {
 962         struct mm_struct *mm = vma->vm_mm;
 963         unsigned long size;
 964
 965         FLUSH_BEGIN(mm)
 966         start &= SRMMU_PGDIR_MASK;
 967         size = SRMMU_PGDIR_ALIGN(end) - start;
 968         __asm__ __volatile__(
 969                 "lda    [%0] %5, %%g5\n\t"
 970                 "sta    %1, [%0] %5\n"
 971                 "1:\n\t"
 972                 "subcc  %3, %4, %3\n\t"
 973                 "bne    1b\n\t"
 974                 " sta   %%g0, [%2 + %3] %6\n\t"
 975                 "sta    %%g5, [%0] %5\n"
 976         : /* no outputs */
 977         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 978           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 979           "i" (ASI_M_FLUSH_PROBE)
 980         : "g5", "cc");
 981         FLUSH_END
 982 }
 983
 984 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 985 {
 986         struct mm_struct *mm = vma->vm_mm;
 987
 988         FLUSH_BEGIN(mm)
 989         __asm__ __volatile__(
 990         "lda    [%0] %3, %%g5\n\t"
 991         "sta    %1, [%0] %3\n\t"
 992         "sta    %%g0, [%2] %4\n\t"
 993         "sta    %%g5, [%0] %3\n"
 994         : /* no outputs */
 995         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 996           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 997         : "g5");
 998         FLUSH_END
 999 }
1000
1001 /* viking.S */
1002 extern void viking_flush_cache_all(void);
1003 extern void viking_flush_cache_mm(struct mm_struct *mm);
1004 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1005                                      unsigned long end);
1006 extern void viking_flush_cache_page(struct vm_area_struct *vma,
1007                                     unsigned long page);
1008 extern void viking_flush_page_to_ram(unsigned long page);
1009 extern void viking_flush_page_for_dma(unsigned long page);
1010 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1011 extern void viking_flush_page(unsigned long page);
1012 extern void viking_mxcc_flush_page(unsigned long page);
1013 extern void viking_flush_tlb_all(void);
1014 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1015 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1016                                    unsigned long end);
1017 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1018                                   unsigned long page);
1019 extern void sun4dsmp_flush_tlb_all(void);
1020 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1021 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1022                                    unsigned long end);
1023 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1024                                   unsigned long page);
1025
1026 /* hypersparc.S */
1027 extern void hypersparc_flush_cache_all(void);
1028 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1029 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1030 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1031 extern void hypersparc_flush_page_to_ram(unsigned long page);
1032 extern void hypersparc_flush_page_for_dma(unsigned long page);
1033 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1034 extern void hypersparc_flush_tlb_all(void);
1035 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1036 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1037 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1038 extern void hypersparc_setup_blockops(void);
1039
1040 /*
1041  * NOTE: All of this startup code assumes the low 16mb (approx.) of
1042  *       kernel mappings are done with one single contiguous chunk of
1043  *       ram.  On small ram machines (classics mainly) we only get
1044  *       around 8mb mapped for us.
1045  */
1046
1047 void __init early_pgtable_allocfail(char *type)
1048 {
1049         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1050         prom_halt();
1051 }
1052
1053 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1054 {
1055         pgd_t *pgdp;
1056         pmd_t *pmdp;
1057         pte_t *ptep;
1058
1059         while(start < end) {
1060                 pgdp = pgd_offset_k(start);
1061                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1062                         pmdp = (pmd_t *) __srmmu_get_nocache(
1063                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1064                         if (pmdp == NULL)
1065                                 early_pgtable_allocfail("pmd");
1066                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1067                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1068                 }
1069                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1070                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1071                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1072                         if (ptep == NULL)
1073                                 early_pgtable_allocfail("pte");
1074                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1075                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1076                 }
1077                 if (start > (0xffffffffUL - PMD_SIZE))
1078                         break;
1079                 start = (start + PMD_SIZE) & PMD_MASK;
1080         }
1081 }
1082
1083 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1084 {
1085         pgd_t *pgdp;
1086         pmd_t *pmdp;
1087         pte_t *ptep;
1088
1089         while(start < end) {
1090                 pgdp = pgd_offset_k(start);
1091                 if(srmmu_pgd_none(*pgdp)) {
1092                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1093                         if (pmdp == NULL)
1094                                 early_pgtable_allocfail("pmd");
1095                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1096                         srmmu_pgd_set(pgdp, pmdp);
1097                 }
1098                 pmdp = srmmu_pmd_offset(pgdp, start);
1099                 if(srmmu_pmd_none(*pmdp)) {
1100                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1101                                                              PTE_SIZE);
1102                         if (ptep == NULL)
1103                                 early_pgtable_allocfail("pte");
1104                         memset(ptep, 0, PTE_SIZE);
1105                         srmmu_pmd_set(pmdp, ptep);
1106                 }
1107                 if (start > (0xffffffffUL - PMD_SIZE))
1108                         break;
1109                 start = (start + PMD_SIZE) & PMD_MASK;
1110         }
1111 }
1112
1113 /*
1114  * This is much cleaner than poking around physical address space
1115  * looking at the prom's page table directly which is what most
1116  * other OS's do.  Yuck... this is much better.
1117  */
1118 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)
1119 {
1120         pgd_t *pgdp;
1121         pmd_t *pmdp;
1122         pte_t *ptep;
1123         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1124         unsigned long prompte;
1125
1126         while(start <= end) {
1127                 if (start == 0)
1128                         break; /* probably wrap around */
1129                 if(start == 0xfef00000)
1130                         start = KADB_DEBUGGER_BEGVM;
1131                 if(!(prompte = srmmu_hwprobe(start))) {
1132                         start += PAGE_SIZE;
1133                         continue;
1134                 }
1135
1136                 /* A red snapper, see what it really is. */
1137                 what = 0;
1138
1139                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1140                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1141                                 what = 1;
1142                 }
1143
1144                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1145                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1146                            prompte)
1147                                 what = 2;
1148                 }
1149
1150                 pgdp = pgd_offset_k(start);
1151                 if(what == 2) {
1152                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1153                         start += SRMMU_PGDIR_SIZE;
1154                         continue;
1155                 }
1156                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1157                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1158                         if (pmdp == NULL)
1159                                 early_pgtable_allocfail("pmd");
1160                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1161                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1162                 }
1163                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1164                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1165                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1166                                                              PTE_SIZE);
1167                         if (ptep == NULL)
1168                                 early_pgtable_allocfail("pte");
1169                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1170                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1171                 }
1172                 if(what == 1) {
1173                         /*
1174                          * We bend the rule where all 16 PTPs in a pmd_t point
1175                          * inside the same PTE page, and we leak a perfectly
1176                          * good hardware PTE piece. Alternatives seem worse.
1177                          */
1178                         unsigned int x; /* Index of HW PMD in soft cluster */
1179                         x = (start >> PMD_SHIFT) & 15;
1180                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1181                         start += SRMMU_REAL_PMD_SIZE;
1182                         continue;
1183                 }
1184                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1185                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1186                 start += PAGE_SIZE;
1187         }
1188 }
1189
1190 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1191
1192 /* Create a third-level SRMMU 16MB page mapping. */
1193 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1194 {
1195         pgd_t *pgdp = pgd_offset_k(vaddr);
1196         unsigned long big_pte;
1197
1198         big_pte = KERNEL_PTE(phys_base >> 4);
1199         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1200 }
1201
1202 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1203 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1204 {
1205         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1206         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1207         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1208         /* Map "low" memory only */
1209         const unsigned long min_vaddr = PAGE_OFFSET;
1210         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1211
1212         if (vstart < min_vaddr || vstart >= max_vaddr)
1213                 return vstart;
1214
1215         if (vend > max_vaddr || vend < min_vaddr)
1216                 vend = max_vaddr;
1217
1218         while(vstart < vend) {
1219                 do_large_mapping(vstart, pstart);
1220                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1221         }
1222         return vstart;
1223 }
1224
1225 static inline void memprobe_error(char *msg)
1226 {
1227         prom_printf(msg);
1228         prom_printf("Halting now...\n");
1229         prom_halt();
1230 }
1231
1232 static inline void map_kernel(void)
1233 {
1234         int i;
1235
1236         if (phys_base > 0) {
1237                 do_large_mapping(PAGE_OFFSET, phys_base);
1238         }
1239
1240         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1241                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1242         }
1243
1244         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1245 }
1246
1247 /* Paging initialization on the Sparc Reference MMU. */
1248 extern void sparc_context_init(int);
1249
1250 void (*poke_srmmu)(void) __initdata = NULL;
1251
1252 extern unsigned long bootmem_init(unsigned long *pages_avail);
1253
1254 void __init srmmu_paging_init(void)
1255 {
1256         int i, cpunode;
1257         char node_str[128];
1258         pgd_t *pgd;
1259         pmd_t *pmd;
1260         pte_t *pte;
1261         unsigned long pages_avail;
1262
1263         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1264
1265         if (sparc_cpu_model == sun4d)
1266                 num_contexts = 65536; /* We know it is Viking */
1267         else {
1268                 /* Find the number of contexts on the srmmu. */
1269                 cpunode = prom_getchild(prom_root_node);
1270                 num_contexts = 0;
1271                 while(cpunode != 0) {
1272                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1273                         if(!strcmp(node_str, "cpu")) {
1274                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1275                                 break;
1276                         }
1277                         cpunode = prom_getsibling(cpunode);
1278                 }
1279         }
1280
1281         if(!num_contexts) {
1282                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1283                 prom_halt();
1284         }
1285
1286         pages_avail = 0;
1287         last_valid_pfn = bootmem_init(&pages_avail);
1288
1289         srmmu_nocache_calcsize();
1290         srmmu_nocache_init();
1291         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1292         map_kernel();
1293
1294         /* ctx table has to be physically aligned to its size */
1295         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1296         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1297
1298         for(i = 0; i < num_contexts; i++)
1299                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1300
1301         flush_cache_all();
1302         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1303         flush_tlb_all();
1304         poke_srmmu();
1305
1306 #ifdef CONFIG_SUN_IO
1307         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1308         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1309 #endif
1310
1311         srmmu_allocate_ptable_skeleton(
1312                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1313         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1314
1315         pgd = pgd_offset_k(PKMAP_BASE);
1316         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1317         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1318         pkmap_page_table = pte;
1319
1320         flush_cache_all();
1321         flush_tlb_all();
1322
1323         sparc_context_init(num_contexts);
1324
1325         kmap_init();
1326
1327         {
1328                 unsigned long zones_size[MAX_NR_ZONES];
1329                 unsigned long zholes_size[MAX_NR_ZONES];
1330                 unsigned long npages;
1331                 int znum;
1332
1333                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1334                         zones_size[znum] = zholes_size[znum] = 0;
1335
1336                 npages = max_low_pfn - pfn_base;
1337
1338                 zones_size[ZONE_DMA] = npages;
1339                 zholes_size[ZONE_DMA] = npages - pages_avail;
1340
1341                 npages = highend_pfn - max_low_pfn;
1342                 zones_size[ZONE_HIGHMEM] = npages;
1343                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1344
1345                 free_area_init_node(0, &contig_page_data, zones_size,
1346                                     pfn_base, zholes_size);
1347                 mem_map = contig_page_data.node_mem_map;
1348         }
1349 }
1350
1351 static void srmmu_mmu_info(struct seq_file *m)
1352 {
1353         seq_printf(m,
1354                    "MMU type\t: %s\n"
1355                    "contexts\t: %d\n"
1356                    "nocache total\t: %ld\n"
1357                    "nocache used\t: %d\n",
1358                    srmmu_name,
1359                    num_contexts,
1360                    srmmu_nocache_size,
1361                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1362 }
1363
1364 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1365 {
1366 }
1367
1368 static void srmmu_destroy_context(struct mm_struct *mm)
1369 {
1370
1371         if(mm->context != NO_CONTEXT) {
1372                 flush_cache_mm(mm);
1373                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1374                 flush_tlb_mm(mm);
1375                 spin_lock(&srmmu_context_spinlock);
1376                 free_context(mm->context);
1377                 spin_unlock(&srmmu_context_spinlock);
1378                 mm->context = NO_CONTEXT;
1379         }
1380 }
1381
1382 /* Init various srmmu chip types. */
1383 static void __init srmmu_is_bad(void)
1384 {
1385         prom_printf("Could not determine SRMMU chip type.\n");
1386         prom_halt();
1387 }
1388
1389 static void __init init_vac_layout(void)
1390 {
1391         int nd, cache_lines;
1392         char node_str[128];
1393 #ifdef CONFIG_SMP
1394         int cpu = 0;
1395         unsigned long max_size = 0;
1396         unsigned long min_line_size = 0x10000000;
1397 #endif
1398
1399         nd = prom_getchild(prom_root_node);
1400         while((nd = prom_getsibling(nd)) != 0) {
1401                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1402                 if(!strcmp(node_str, "cpu")) {
1403                         vac_line_size = prom_getint(nd, "cache-line-size");
1404                         if (vac_line_size == -1) {
1405                                 prom_printf("can't determine cache-line-size, "
1406                                             "halting.\n");
1407                                 prom_halt();
1408                         }
1409                         cache_lines = prom_getint(nd, "cache-nlines");
1410                         if (cache_lines == -1) {
1411                                 prom_printf("can't determine cache-nlines, halting.\n");
1412                                 prom_halt();
1413                         }
1414
1415                         vac_cache_size = cache_lines * vac_line_size;
1416 #ifdef CONFIG_SMP
1417                         if(vac_cache_size > max_size)
1418                                 max_size = vac_cache_size;
1419                         if(vac_line_size < min_line_size)
1420                                 min_line_size = vac_line_size;
1421                         cpu++;
1422                         if (cpu >= NR_CPUS || !cpu_online(cpu))
1423                                 break;
1424 #else
1425                         break;
1426 #endif
1427                 }
1428         }
1429         if(nd == 0) {
1430                 prom_printf("No CPU nodes found, halting.\n");
1431                 prom_halt();
1432         }
1433 #ifdef CONFIG_SMP
1434         vac_cache_size = max_size;
1435         vac_line_size = min_line_size;
1436 #endif
1437         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1438                (int)vac_cache_size, (int)vac_line_size);
1439 }
1440
1441 static void __init poke_hypersparc(void)
1442 {
1443         volatile unsigned long clear;
1444         unsigned long mreg = srmmu_get_mmureg();
1445
1446         hyper_flush_unconditional_combined();
1447
1448         mreg &= ~(HYPERSPARC_CWENABLE);
1449         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1450         mreg |= (HYPERSPARC_CMODE);
1451
1452         srmmu_set_mmureg(mreg);
1453
1454 #if 0 /* XXX I think this is bad news... -DaveM */
1455         hyper_clear_all_tags();
1456 #endif
1457
1458         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1459         hyper_flush_whole_icache();
1460         clear = srmmu_get_faddr();
1461         clear = srmmu_get_fstatus();
1462 }
1463
1464 static void __init init_hypersparc(void)
1465 {
1466         srmmu_name = "ROSS HyperSparc";
1467         srmmu_modtype = HyperSparc;
1468
1469         init_vac_layout();
1470
1471         is_hypersparc = 1;
1472
1473         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1474         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1475         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1476         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1477         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1478         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1479         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1480
1481         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1482         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1483         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1484         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1485
1486         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1487         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1488         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1489
1490
1491         poke_srmmu = poke_hypersparc;
1492
1493         hypersparc_setup_blockops();
1494 }
1495
1496 static void __init poke_cypress(void)
1497 {
1498         unsigned long mreg = srmmu_get_mmureg();
1499         unsigned long faddr, tagval;
1500         volatile unsigned long cypress_sucks;
1501         volatile unsigned long clear;
1502
1503         clear = srmmu_get_faddr();
1504         clear = srmmu_get_fstatus();
1505
1506         if (!(mreg & CYPRESS_CENABLE)) {
1507                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1508                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1509                                              "sta %%g0, [%0] %2\n\t" : :
1510                                              "r" (faddr), "r" (0x40000),
1511                                              "i" (ASI_M_DATAC_TAG));
1512                 }
1513         } else {
1514                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1515                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1516                                              "=r" (tagval) :
1517                                              "r" (faddr), "r" (0x40000),
1518                                              "i" (ASI_M_DATAC_TAG));
1519
1520                         /* If modified and valid, kick it. */
1521                         if((tagval & 0x60) == 0x60)
1522                                 cypress_sucks = *(unsigned long *)
1523                                                         (0xf0020000 + faddr);
1524                 }
1525         }
1526
1527         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1528         clear = srmmu_get_faddr();
1529         clear = srmmu_get_fstatus();
1530
1531         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1532         srmmu_set_mmureg(mreg);
1533 }
1534
1535 static void __init init_cypress_common(void)
1536 {
1537         init_vac_layout();
1538
1539         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1540         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1541         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1542         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1543         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1544         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1545         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1546
1547         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1548         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1549         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1550         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1551
1552
1553         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1554         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1555         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1556
1557         poke_srmmu = poke_cypress;
1558 }
1559
1560 static void __init init_cypress_604(void)
1561 {
1562         srmmu_name = "ROSS Cypress-604(UP)";
1563         srmmu_modtype = Cypress;
1564         init_cypress_common();
1565 }
1566
1567 static void __init init_cypress_605(unsigned long mrev)
1568 {
1569         srmmu_name = "ROSS Cypress-605(MP)";
1570         if(mrev == 0xe) {
1571                 srmmu_modtype = Cypress_vE;
1572                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1573         } else {
1574                 if(mrev == 0xd) {
1575                         srmmu_modtype = Cypress_vD;
1576                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1577                 } else {
1578                         srmmu_modtype = Cypress;
1579                 }
1580         }
1581         init_cypress_common();
1582 }
1583
1584 static void __init poke_swift(void)
1585 {
1586         unsigned long mreg;
1587
1588         /* Clear any crap from the cache or else... */
1589         swift_flush_cache_all();
1590
1591         /* Enable I & D caches */
1592         mreg = srmmu_get_mmureg();
1593         mreg |= (SWIFT_IE | SWIFT_DE);
1594         /*
1595          * The Swift branch folding logic is completely broken.  At
1596          * trap time, if things are just right, if can mistakenly
1597          * think that a trap is coming from kernel mode when in fact
1598          * it is coming from user mode (it mis-executes the branch in
1599          * the trap code).  So you see things like crashme completely
1600          * hosing your machine which is completely unacceptable.  Turn
1601          * this shit off... nice job Fujitsu.
1602          */
1603         mreg &= ~(SWIFT_BF);
1604         srmmu_set_mmureg(mreg);
1605 }
1606
1607 #define SWIFT_MASKID_ADDR  0x10003018
1608 static void __init init_swift(void)
1609 {
1610         unsigned long swift_rev;
1611
1612         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1613                              "srl %0, 0x18, %0\n\t" :
1614                              "=r" (swift_rev) :
1615                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1616         srmmu_name = "Fujitsu Swift";
1617         switch(swift_rev) {
1618         case 0x11:
1619         case 0x20:
1620         case 0x23:
1621         case 0x30:
1622                 srmmu_modtype = Swift_lots_o_bugs;
1623                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1624                 /*
1625                  * Gee george, I wonder why Sun is so hush hush about
1626                  * this hardware bug... really braindamage stuff going
1627                  * on here.  However I think we can find a way to avoid
1628                  * all of the workaround overhead under Linux.  Basically,
1629                  * any page fault can cause kernel pages to become user
1630                  * accessible (the mmu gets confused and clears some of
1631                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1632                  * horrible eh?  But wait, after extensive testing it appears
1633                  * that if you use pgd_t level large kernel pte's (like the
1634                  * 4MB pages on the Pentium) the bug does not get tripped
1635                  * at all.  This avoids almost all of the major overhead.
1636                  * Welcome to a world where your vendor tells you to,
1637                  * "apply this kernel patch" instead of "sorry for the
1638                  * broken hardware, send it back and we'll give you
1639                  * properly functioning parts"
1640                  */
1641                 break;
1642         case 0x25:
1643         case 0x31:
1644                 srmmu_modtype = Swift_bad_c;
1645                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1646                 /*
1647                  * You see Sun allude to this hardware bug but never
1648                  * admit things directly, they'll say things like,
1649                  * "the Swift chip cache problems" or similar.
1650                  */
1651                 break;
1652         default:
1653                 srmmu_modtype = Swift_ok;
1654                 break;
1655         };
1656
1657         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1658         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1659         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1660         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1661
1662
1663         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1664         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1665         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1666         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1667
1668         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1669         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1670         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1671
1672         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1673
1674         flush_page_for_dma_global = 0;
1675
1676         /*
1677          * Are you now convinced that the Swift is one of the
1678          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1679          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1680          * you examined the microcode of the Swift you'd find
1681          * XXX's all over the place.
1682          */
1683         poke_srmmu = poke_swift;
1684 }
1685
1686 static void turbosparc_flush_cache_all(void)
1687 {
1688         flush_user_windows();
1689         turbosparc_idflash_clear();
1690 }
1691
1692 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1693 {
1694         FLUSH_BEGIN(mm)
1695         flush_user_windows();
1696         turbosparc_idflash_clear();
1697         FLUSH_END
1698 }
1699
1700 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1701 {
1702         FLUSH_BEGIN(vma->vm_mm)
1703         flush_user_windows();
1704         turbosparc_idflash_clear();
1705         FLUSH_END
1706 }
1707
1708 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1709 {
1710         FLUSH_BEGIN(vma->vm_mm)
1711         flush_user_windows();
1712         if (vma->vm_flags & VM_EXEC)
1713                 turbosparc_flush_icache();
1714         turbosparc_flush_dcache();
1715         FLUSH_END
1716 }
1717
1718 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1719 static void turbosparc_flush_page_to_ram(unsigned long page)
1720 {
1721 #ifdef TURBOSPARC_WRITEBACK
1722         volatile unsigned long clear;
1723
1724         if (srmmu_hwprobe(page))
1725                 turbosparc_flush_page_cache(page);
1726         clear = srmmu_get_fstatus();
1727 #endif
1728 }
1729
1730 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1731 {
1732 }
1733
1734 static void turbosparc_flush_page_for_dma(unsigned long page)
1735 {
1736         turbosparc_flush_dcache();
1737 }
1738
1739 static void turbosparc_flush_tlb_all(void)
1740 {
1741         srmmu_flush_whole_tlb();
1742 }
1743
1744 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1745 {
1746         FLUSH_BEGIN(mm)
1747         srmmu_flush_whole_tlb();
1748         FLUSH_END
1749 }
1750
1751 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1752 {
1753         FLUSH_BEGIN(vma->vm_mm)
1754         srmmu_flush_whole_tlb();
1755         FLUSH_END
1756 }
1757
1758 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1759 {
1760         FLUSH_BEGIN(vma->vm_mm)
1761         srmmu_flush_whole_tlb();
1762         FLUSH_END
1763 }
1764
1765
1766 static void __init poke_turbosparc(void)
1767 {
1768         unsigned long mreg = srmmu_get_mmureg();
1769         unsigned long ccreg;
1770
1771         /* Clear any crap from the cache or else... */
1772         turbosparc_flush_cache_all();
1773         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1774         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1775         srmmu_set_mmureg(mreg);
1776
1777         ccreg = turbosparc_get_ccreg();
1778
1779 #ifdef TURBOSPARC_WRITEBACK
1780         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1781         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1782                         /* Write-back D-cache, emulate VLSI
1783                          * abortion number three, not number one */
1784 #else
1785         /* For now let's play safe, optimize later */
1786         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1787                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1788         ccreg &= ~(TURBOSPARC_uS2);
1789                         /* Emulate VLSI abortion number three, not number one */
1790 #endif
1791
1792         switch (ccreg & 7) {
1793         case 0: /* No SE cache */
1794         case 7: /* Test mode */
1795                 break;
1796         default:
1797                 ccreg |= (TURBOSPARC_SCENABLE);
1798         }
1799         turbosparc_set_ccreg (ccreg);
1800
1801         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1802         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1803         srmmu_set_mmureg(mreg);
1804 }
1805
1806 static void __init init_turbosparc(void)
1807 {
1808         srmmu_name = "Fujitsu TurboSparc";
1809         srmmu_modtype = TurboSparc;
1810
1811         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1812         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1813         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1814         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1815
1816         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1817         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1818         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1819         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1820
1821         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1822
1823         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1824         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1825
1826         poke_srmmu = poke_turbosparc;
1827 }
1828
1829 static void __init poke_tsunami(void)
1830 {
1831         unsigned long mreg = srmmu_get_mmureg();
1832
1833         tsunami_flush_icache();
1834         tsunami_flush_dcache();
1835         mreg &= ~TSUNAMI_ITD;
1836         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1837         srmmu_set_mmureg(mreg);
1838 }
1839
1840 static void __init init_tsunami(void)
1841 {
1842         /*
1843          * Tsunami's pretty sane, Sun and TI actually got it
1844          * somewhat right this time.  Fujitsu should have
1845          * taken some lessons from them.
1846          */
1847
1848         srmmu_name = "TI Tsunami";
1849         srmmu_modtype = Tsunami;
1850
1851         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1852         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1853         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1854         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1855
1856
1857         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1858         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1859         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1860         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1861
1862         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1863         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1864         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1865
1866         poke_srmmu = poke_tsunami;
1867
1868         tsunami_setup_blockops();
1869 }
1870
1871 static void __init poke_viking(void)
1872 {
1873         unsigned long mreg = srmmu_get_mmureg();
1874         static int smp_catch;
1875
1876         if(viking_mxcc_present) {
1877                 unsigned long mxcc_control = mxcc_get_creg();
1878
1879                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1880                 mxcc_control &= ~(MXCC_CTL_RRC);
1881                 mxcc_set_creg(mxcc_control);
1882
1883                 /*
1884                  * We don't need memory parity checks.
1885                  * XXX This is a mess, have to dig out later. ecd.
1886                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1887                  */
1888
1889                 /* We do cache ptables on MXCC. */
1890                 mreg |= VIKING_TCENABLE;
1891         } else {
1892                 unsigned long bpreg;
1893
1894                 mreg &= ~(VIKING_TCENABLE);
1895                 if(smp_catch++) {
1896                         /* Must disable mixed-cmd mode here for other cpu's. */
1897                         bpreg = viking_get_bpreg();
1898                         bpreg &= ~(VIKING_ACTION_MIX);
1899                         viking_set_bpreg(bpreg);
1900
1901                         /* Just in case PROM does something funny. */
1902                         msi_set_sync();
1903                 }
1904         }
1905
1906         mreg |= VIKING_SPENABLE;
1907         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1908         mreg |= VIKING_SBENABLE;
1909         mreg &= ~(VIKING_ACENABLE);
1910         srmmu_set_mmureg(mreg);
1911
1912 #ifdef CONFIG_SMP
1913         /* Avoid unnecessary cross calls. */
1914         BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
1915         BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
1916         BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
1917         BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
1918         BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
1919         BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
1920         BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
1921         btfixup();
1922 #endif
1923 }
1924
1925 static void __init init_viking(void)
1926 {
1927         unsigned long mreg = srmmu_get_mmureg();
1928
1929         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1930         if(mreg & VIKING_MMODE) {
1931                 srmmu_name = "TI Viking";
1932                 viking_mxcc_present = 0;
1933                 msi_set_sync();
1934
1935                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1936                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1937                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1938
1939                 /*
1940                  * We need this to make sure old viking takes no hits
1941                  * on it's cache for dma snoops to workaround the
1942                  * "load from non-cacheable memory" interrupt bug.
1943                  * This is only necessary because of the new way in
1944                  * which we use the IOMMU.
1945                  */
1946                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1947
1948                 flush_page_for_dma_global = 0;
1949         } else {
1950                 srmmu_name = "TI Viking/MXCC";
1951                 viking_mxcc_present = 1;
1952
1953                 srmmu_cache_pagetables = 1;
1954
1955                 /* MXCC vikings lack the DMA snooping bug. */
1956                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1957         }
1958
1959         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1960         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1961         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1962         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1963
1964 #ifdef CONFIG_SMP
1965         if (sparc_cpu_model == sun4d) {
1966                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1967                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1968                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1969                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1970         } else
1971 #endif
1972         {
1973                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1974                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1975                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1976                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1977         }
1978
1979         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1980         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1981
1982         poke_srmmu = poke_viking;
1983 }
1984
1985 /* Probe for the srmmu chip version. */
1986 static void __init get_srmmu_type(void)
1987 {
1988         unsigned long mreg, psr;
1989         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1990
1991         srmmu_modtype = SRMMU_INVAL_MOD;
1992         hwbug_bitmask = 0;
1993
1994         mreg = srmmu_get_mmureg(); psr = get_psr();
1995         mod_typ = (mreg & 0xf0000000) >> 28;
1996         mod_rev = (mreg & 0x0f000000) >> 24;
1997         psr_typ = (psr >> 28) & 0xf;
1998         psr_vers = (psr >> 24) & 0xf;
1999
2000         /* First, check for HyperSparc or Cypress. */
2001         if(mod_typ == 1) {
2002                 switch(mod_rev) {
2003                 case 7:
2004                         /* UP or MP Hypersparc */
2005                         init_hypersparc();
2006                         break;
2007                 case 0:
2008                 case 2:
2009                         /* Uniprocessor Cypress */
2010                         init_cypress_604();
2011                         break;
2012                 case 10:
2013                 case 11:
2014                 case 12:
2015                         /* _REALLY OLD_ Cypress MP chips... */
2016                 case 13:
2017                 case 14:
2018                 case 15:
2019                         /* MP Cypress mmu/cache-controller */
2020                         init_cypress_605(mod_rev);
2021                         break;
2022                 default:
2023                         /* Some other Cypress revision, assume a 605. */
2024                         init_cypress_605(mod_rev);
2025                         break;
2026                 };
2027                 return;
2028         }
2029
2030         /*
2031          * Now Fujitsu TurboSparc. It might happen that it is
2032          * in Swift emulation mode, so we will check later...
2033          */
2034         if (psr_typ == 0 && psr_vers == 5) {
2035                 init_turbosparc();
2036                 return;
2037         }
2038
2039         /* Next check for Fujitsu Swift. */
2040         if(psr_typ == 0 && psr_vers == 4) {
2041                 int cpunode;
2042                 char node_str[128];
2043
2044                 /* Look if it is not a TurboSparc emulating Swift... */
2045                 cpunode = prom_getchild(prom_root_node);
2046                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2047                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2048                         if(!strcmp(node_str, "cpu")) {
2049                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2050                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2051                                         init_turbosparc();
2052                                         return;
2053                                 }
2054                                 break;
2055                         }
2056                 }
2057
2058                 init_swift();
2059                 return;
2060         }
2061
2062         /* Now the Viking family of srmmu. */
2063         if(psr_typ == 4 &&
2064            ((psr_vers == 0) ||
2065             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2066                 init_viking();
2067                 return;
2068         }
2069
2070         /* Finally the Tsunami. */
2071         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2072                 init_tsunami();
2073                 return;
2074         }
2075
2076         /* Oh well */
2077         srmmu_is_bad();
2078 }
2079
2080 /* don't laugh, static pagetables */
2081 static void srmmu_check_pgt_cache(int low, int high)
2082 {
2083 }
2084
2085 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2086         tsetup_mmu_patchme, rtrap_mmu_patchme;
2087
2088 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2089         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2090
2091 extern unsigned long srmmu_fault;
2092
2093 #define PATCH_BRANCH(insn, dest) do { \
2094                 iaddr = &(insn); \
2095                 daddr = &(dest); \
2096                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2097         } while(0)
2098
2099 static void __init patch_window_trap_handlers(void)
2100 {
2101         unsigned long *iaddr, *daddr;
2102
2103         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2104         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2105         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2106         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2107         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2108         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2109         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2110 }
2111
2112 #ifdef CONFIG_SMP
2113 /* Local cross-calls. */
2114 static void smp_flush_page_for_dma(unsigned long page)
2115 {
2116         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2117         local_flush_page_for_dma(page);
2118 }
2119
2120 #endif
2121
2122 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2123 {
2124         return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2125 }
2126
2127 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2128 {
2129         return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2130 }
2131
2132 /* Load up routines and constants for sun4m and sun4d mmu */
2133 void __init ld_mmu_srmmu(void)
2134 {
2135         extern void ld_mmu_iommu(void);
2136         extern void ld_mmu_iounit(void);
2137         extern void ___xchg32_sun4md(void);
2138
2139         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2140         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2141         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2142
2143         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2144         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2145
2146         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2147         BTFIXUPSET_INT(page_shared, pgprot_val(SRMMU_PAGE_SHARED));
2148         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2149         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2150         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2151         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2152         pg_iobits = SRMMU_VALID | SRMMU_WRITE | SRMMU_REF;
2153
2154         /* Functions */
2155 #ifndef CONFIG_SMP
2156         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2157 #endif
2158         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2159
2160         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2161         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2162
2163         BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2164         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2165         BTFIXUPSET_CALL(pgd_page, srmmu_pgd_page, BTFIXUPCALL_NORM);
2166
2167         BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2168
2169         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2170         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2171
2172         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2173         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2174         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2175
2176         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2177         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2178         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2179         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2180
2181         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2182         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2183         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2184         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2185         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2186         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2187
2188         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2189         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2190         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2191
2192         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2193         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2194         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2195         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2196         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2197         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2198         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2199         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2200
2201         BTFIXUPSET_HALF(pte_readi, SRMMU_NOREAD);
2202         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2203         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2204         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2205         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2206         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2207         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2208         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2209         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2210         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2211         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2212         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2213         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2214
2215         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2216         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2217
2218         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2219         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2220         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2221
2222         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2223
2224         BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2225         BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2226
2227         BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2228         BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2229
2230         get_srmmu_type();
2231         patch_window_trap_handlers();
2232
2233 #ifdef CONFIG_SMP
2234         /* El switcheroo... */
2235
2236         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2237         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2238         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2239         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2240         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2241         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2242         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2243         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2244         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2245         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2246         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2247
2248         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2249         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2250         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2251         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2252         if (sparc_cpu_model != sun4d) {
2253                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2254                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2255                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2256                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2257         }
2258         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2259         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2260         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2261 #endif
2262
2263         if (sparc_cpu_model == sun4d)
2264                 ld_mmu_iounit();
2265         else
2266                 ld_mmu_iommu();
2267 #ifdef CONFIG_SMP
2268         if (sparc_cpu_model == sun4d)
2269                 sun4d_init_smp();
2270         else
2271                 sun4m_init_smp();
2272 #endif
2273 }