1 /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
2 * pci.c: UltraSparc PCI controller support.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/sched.h>
14 #include <linux/capability.h>
15 #include <linux/errno.h>
16 #include <linux/smp_lock.h>
17 #include <linux/init.h>
19 #include <asm/uaccess.h>
25 unsigned long pci_memspace_mask = 0xffffffffUL;
28 /* A "nop" PCI implementation. */
29 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
30 unsigned long off, unsigned long len,
35 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
36 unsigned long off, unsigned long len,
43 /* List of all PCI controllers found in the system. */
44 spinlock_t pci_controller_lock = SPIN_LOCK_UNLOCKED;
45 struct pci_controller_info *pci_controller_root = NULL;
47 /* Each PCI controller found gets a unique index. */
48 int pci_num_controllers = 0;
50 /* At boot time the user can give the kernel a command
51 * line option which controls if and how PCI devices
52 * are reordered at PCI bus probing time.
54 int pci_device_reorder = 0;
56 volatile int pci_poke_in_progress;
57 volatile int pci_poke_cpu = -1;
58 volatile int pci_poke_faulted;
60 static spinlock_t pci_poke_lock = SPIN_LOCK_UNLOCKED;
62 void pci_config_read8(u8 *addr, u8 *ret)
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
77 pci_poke_in_progress = 0;
79 if (!pci_poke_faulted)
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
84 void pci_config_read16(u16 *addr, u16 *ret)
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
99 pci_poke_in_progress = 0;
101 if (!pci_poke_faulted)
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
106 void pci_config_read32(u32 *addr, u32 *ret)
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
121 pci_poke_in_progress = 0;
123 if (!pci_poke_faulted)
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
128 void pci_config_write8(u8 *addr, u8 val)
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 pci_poke_in_progress = 0;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
147 void pci_config_write16(u16 *addr, u16 val)
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 pci_poke_in_progress = 0;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
166 void pci_config_write32(u32 *addr, u32 val)
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
180 pci_poke_in_progress = 0;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
185 /* Probe for all PCI controllers in the system. */
186 extern void sabre_init(int, char *);
187 extern void psycho_init(int, char *);
188 extern void schizo_init(int, char *);
189 extern void schizo_plus_init(int, char *);
190 extern void tomatillo_init(int, char *);
194 void (*init)(int, char *);
195 } pci_controller_table[] __initdata = {
196 { "SUNW,sabre", sabre_init },
197 { "pci108e,a000", sabre_init },
198 { "pci108e,a001", sabre_init },
199 { "SUNW,psycho", psycho_init },
200 { "pci108e,8000", psycho_init },
201 { "SUNW,schizo", schizo_init },
202 { "pci108e,8001", schizo_init },
203 { "SUNW,schizo+", schizo_plus_init },
204 { "pci108e,8002", schizo_plus_init },
205 { "SUNW,tomatillo", tomatillo_init },
206 { "pci108e,a801", tomatillo_init },
208 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
209 sizeof(pci_controller_table[0]))
211 static int __init pci_controller_init(char *model_name, int namelen, int node)
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
219 pci_controller_table[i].init(node, model_name);
223 printk("PCI: Warning unknown controller, model name [%s]\n",
225 printk("PCI: Ignoring controller...\n");
230 static int __init pci_is_controller(char *model_name, int namelen, int node)
234 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
235 if (!strncmp(model_name,
236 pci_controller_table[i].model_name,
244 static int __init pci_controller_scan(int (*handler)(char *, int, int))
250 node = prom_getchild(prom_root_node);
251 while ((node = prom_searchsiblings(node, "pci")) != 0) {
254 if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 ||
255 (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) {
258 /* Our value may be a multi-valued string in the
259 * case of some compatible properties. For sanity,
260 * only try the first one. */
262 while (namebuf[item_len] && len) {
267 if (handler(namebuf, item_len, node))
271 node = prom_getsibling(node);
280 /* Is there some PCI controller in the system? */
281 int __init pcic_present(void)
283 return pci_controller_scan(pci_is_controller);
286 /* Find each controller in the system, attach and initialize
287 * software state structure for each and link into the
288 * pci_controller_root. Setup the controller enough such
289 * that bus scanning can be done.
291 static void __init pci_controller_probe(void)
293 printk("PCI: Probing for controllers.\n");
295 pci_controller_scan(pci_controller_init);
298 static void __init pci_scan_each_controller_bus(void)
300 struct pci_controller_info *p;
303 spin_lock_irqsave(&pci_controller_lock, flags);
304 for (p = pci_controller_root; p; p = p->next)
306 spin_unlock_irqrestore(&pci_controller_lock, flags);
309 /* Reorder the pci_dev chain, so that onboard devices come first
310 * and then come the pluggable cards.
312 static void __init pci_reorder_devs(void)
314 struct list_head *pci_onboard = &pci_devices;
315 struct list_head *walk = pci_onboard->next;
317 while (walk != pci_onboard) {
318 struct pci_dev *pdev = pci_dev_g(walk);
319 struct list_head *walk_next = walk->next;
321 if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
323 list_add(walk, pci_onboard);
330 extern void clock_probe(void);
331 extern void power_init(void);
333 static int __init pcibios_init(void)
335 pci_controller_probe();
336 if (pci_controller_root == NULL)
339 pci_scan_each_controller_bus();
341 if (pci_device_reorder)
352 subsys_initcall(pcibios_init);
354 struct pci_fixup pcibios_fixups[] = {
358 void pcibios_fixup_bus(struct pci_bus *pbus)
360 struct pci_pbm_info *pbm = pbus->sysdata;
362 /* Generic PCI bus probing sets these to point at
363 * &io{port,mem}_resouce which is wrong for us.
365 pbus->resource[0] = &pbm->io_space;
366 pbus->resource[1] = &pbm->mem_space;
369 int pci_claim_resource(struct pci_dev *pdev, int resource)
371 struct pci_pbm_info *pbm = pdev->bus->sysdata;
372 struct resource *res = &pdev->resource[resource];
373 struct resource *root;
378 if (res->flags & IORESOURCE_IO)
379 root = &pbm->io_space;
381 root = &pbm->mem_space;
383 pbm->parent->resource_adjust(pdev, res, root);
385 return request_resource(root, res);
389 * Given the PCI bus a device resides on, try to
390 * find an acceptable resource allocation for a
391 * specific device resource..
393 static int pci_assign_bus_resource(const struct pci_bus *bus,
395 struct resource *res,
400 unsigned int type_mask;
403 type_mask = IORESOURCE_IO | IORESOURCE_MEM;
404 for (i = 0 ; i < 4; i++) {
405 struct resource *r = bus->resource[i];
409 /* type_mask must match */
410 if ((res->flags ^ r->flags) & type_mask)
413 /* Ok, try it out.. */
414 if (allocate_resource(r, res, size, min, -1, size, NULL, NULL) < 0)
417 /* PCI config space updated by caller. */
423 int pci_assign_resource(struct pci_dev *pdev, int resource)
425 struct pcidev_cookie *pcp = pdev->sysdata;
426 struct pci_pbm_info *pbm = pcp->pbm;
427 struct resource *res = &pdev->resource[resource];
428 unsigned long min, size;
431 if (res->flags & IORESOURCE_IO)
432 min = pbm->io_space.start + 0x400UL;
434 min = pbm->mem_space.start;
436 size = res->end - res->start + 1;
438 err = pci_assign_bus_resource(pdev->bus, pdev, res, size, min, resource);
441 printk("PCI: Failed to allocate resource %d for %s\n",
442 resource, pci_name(pdev));
444 /* Update PCI config space. */
445 pbm->parent->base_address_update(pdev, resource);
451 /* Sort resources by alignment */
452 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
456 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
458 struct resource_list *list, *tmp;
459 unsigned long r_align;
461 r = &dev->resource[i];
462 r_align = r->end - r->start;
464 if (!(r->flags) || r->parent)
467 printk(KERN_WARNING "PCI: Ignore bogus resource %d "
469 i, r->start, r->end, pci_name(dev));
472 r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
473 for (list = head; ; list = list->next) {
474 unsigned long align = 0;
475 struct resource_list *ln = list->next;
479 idx = ln->res - &ln->dev->resource[0];
480 align = (idx < PCI_BRIDGE_RESOURCES) ?
481 ln->res->end - ln->res->start + 1 :
484 if (r_align > align) {
485 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
487 panic("pdev_sort_resources(): "
488 "kmalloc() failed!\n");
499 void pcibios_update_irq(struct pci_dev *pdev, int irq)
503 void pcibios_align_resource(void *data, struct resource *res,
504 unsigned long size, unsigned long align)
508 int pcibios_enable_device(struct pci_dev *pdev, int mask)
513 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
514 struct resource *res)
516 struct pci_pbm_info *pbm = pdev->bus->sysdata;
517 struct resource zero_res, *root;
521 zero_res.flags = res->flags;
523 if (res->flags & IORESOURCE_IO)
524 root = &pbm->io_space;
526 root = &pbm->mem_space;
528 pbm->parent->resource_adjust(pdev, &zero_res, root);
530 region->start = res->start - zero_res.start;
531 region->end = res->end - zero_res.start;
534 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
535 struct pci_bus_region *region)
537 struct pci_pbm_info *pbm = pdev->bus->sysdata;
538 struct resource *root;
540 res->start = region->start;
541 res->end = region->end;
543 if (res->flags & IORESOURCE_IO)
544 root = &pbm->io_space;
546 root = &pbm->mem_space;
548 pbm->parent->resource_adjust(pdev, res, root);
551 char * __init pcibios_setup(char *str)
553 if (!strcmp(str, "onboardfirst")) {
554 pci_device_reorder = 1;
557 if (!strcmp(str, "noreorder")) {
558 pci_device_reorder = 0;
564 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
566 /* If the user uses a host-bridge as the PCI device, he may use
567 * this to perform a raw mmap() of the I/O or MEM space behind
570 * This can be useful for execution of x86 PCI bios initialization code
571 * on a PCI card, like the xfree86 int10 stuff does.
573 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
574 enum pci_mmap_state mmap_state)
576 struct pcidev_cookie *pcp = pdev->sysdata;
577 struct pci_pbm_info *pbm;
578 struct pci_controller_info *p;
579 unsigned long space_size, user_offset, user_size;
588 if (p->pbms_same_domain) {
589 unsigned long lowest, highest;
591 lowest = ~0UL; highest = 0UL;
592 if (mmap_state == pci_mmap_io) {
593 if (p->pbm_A.io_space.flags) {
594 lowest = p->pbm_A.io_space.start;
595 highest = p->pbm_A.io_space.end + 1;
597 if (p->pbm_B.io_space.flags) {
598 if (lowest > p->pbm_B.io_space.start)
599 lowest = p->pbm_B.io_space.start;
600 if (highest < p->pbm_B.io_space.end + 1)
601 highest = p->pbm_B.io_space.end + 1;
603 space_size = highest - lowest;
605 if (p->pbm_A.mem_space.flags) {
606 lowest = p->pbm_A.mem_space.start;
607 highest = p->pbm_A.mem_space.end + 1;
609 if (p->pbm_B.mem_space.flags) {
610 if (lowest > p->pbm_B.mem_space.start)
611 lowest = p->pbm_B.mem_space.start;
612 if (highest < p->pbm_B.mem_space.end + 1)
613 highest = p->pbm_B.mem_space.end + 1;
615 space_size = highest - lowest;
618 if (mmap_state == pci_mmap_io) {
619 space_size = (pbm->io_space.end -
620 pbm->io_space.start) + 1;
622 space_size = (pbm->mem_space.end -
623 pbm->mem_space.start) + 1;
627 /* Make sure the request is in range. */
628 user_offset = vma->vm_pgoff << PAGE_SHIFT;
629 user_size = vma->vm_end - vma->vm_start;
631 if (user_offset >= space_size ||
632 (user_offset + user_size) > space_size)
635 if (p->pbms_same_domain) {
636 unsigned long lowest = ~0UL;
638 if (mmap_state == pci_mmap_io) {
639 if (p->pbm_A.io_space.flags)
640 lowest = p->pbm_A.io_space.start;
641 if (p->pbm_B.io_space.flags &&
642 lowest > p->pbm_B.io_space.start)
643 lowest = p->pbm_B.io_space.start;
645 if (p->pbm_A.mem_space.flags)
646 lowest = p->pbm_A.mem_space.start;
647 if (p->pbm_B.mem_space.flags &&
648 lowest > p->pbm_B.mem_space.start)
649 lowest = p->pbm_B.mem_space.start;
651 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
653 if (mmap_state == pci_mmap_io) {
654 vma->vm_pgoff = (pbm->io_space.start +
655 user_offset) >> PAGE_SHIFT;
657 vma->vm_pgoff = (pbm->mem_space.start +
658 user_offset) >> PAGE_SHIFT;
665 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
666 * to the 32-bit pci bus offset for DEV requested by the user.
668 * Basically, the user finds the base address for his device which he wishes
669 * to mmap. They read the 32-bit value from the config space base register,
670 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
671 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
673 * Returns negative error code on failure, zero on success.
675 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
676 enum pci_mmap_state mmap_state)
678 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
679 unsigned long user32 = user_offset & pci_memspace_mask;
680 unsigned long largest_base, this_base, addr32;
683 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
684 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
686 /* Figure out which base address this is for. */
688 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
689 struct resource *rp = &dev->resource[i];
696 if (i == PCI_ROM_RESOURCE) {
697 if (mmap_state != pci_mmap_mem)
700 if ((mmap_state == pci_mmap_io &&
701 (rp->flags & IORESOURCE_IO) == 0) ||
702 (mmap_state == pci_mmap_mem &&
703 (rp->flags & IORESOURCE_MEM) == 0))
707 this_base = rp->start;
709 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
711 if (mmap_state == pci_mmap_io)
714 if (addr32 <= user32 && this_base > largest_base)
715 largest_base = this_base;
718 if (largest_base == 0UL)
721 /* Now construct the final physical address. */
722 if (mmap_state == pci_mmap_io)
723 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
725 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
730 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
733 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
734 enum pci_mmap_state mmap_state)
736 vma->vm_flags |= (VM_SHM | VM_LOCKED);
739 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
742 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
743 enum pci_mmap_state mmap_state)
745 /* Our io_remap_page_range takes care of this, do nothing. */
748 extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, unsigned long offset,
749 unsigned long size, pgprot_t prot, int space);
751 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
752 * for this architecture. The region in the process to map is described by vm_start
753 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
754 * The pci device structure is provided so that architectures may make mapping
755 * decisions on a per-device or per-bus basis.
757 * Returns a negative error code on failure, zero on success.
759 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
760 enum pci_mmap_state mmap_state,
765 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
769 __pci_mmap_set_flags(dev, vma, mmap_state);
770 __pci_mmap_set_pgprot(dev, vma, mmap_state);
772 ret = io_remap_page_range(vma, vma->vm_start,
773 (vma->vm_pgoff << PAGE_SHIFT |
774 (write_combine ? 0x1UL : 0x0UL)),
775 vma->vm_end - vma->vm_start, vma->vm_page_prot, 0);
779 vma->vm_flags |= VM_IO;
783 /* Return the domain nuber for this pci bus */
785 int pci_domain_nr(struct pci_bus *pbus)
787 struct pci_pbm_info *pbm = pbus->sysdata;
790 if (pbm == NULL || pbm->parent == NULL) {
793 struct pci_controller_info *p = pbm->parent;
796 if (p->pbms_same_domain == 0)
798 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
803 EXPORT_SYMBOL(pci_domain_nr);
805 int pci_name_bus(char *name, struct pci_bus *bus)
807 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
811 int pcibios_prep_mwi(struct pci_dev *dev)
813 /* We set correct PCI_CACHE_LINE_SIZE register values for every
814 * device probed on this platform. So there is nothing to check
815 * and this always succeeds.
820 #endif /* !(CONFIG_PCI) */