1 /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
2 * pci.c: UltraSparc PCI controller support.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/sched.h>
14 #include <linux/capability.h>
15 #include <linux/errno.h>
16 #include <linux/smp_lock.h>
17 #include <linux/init.h>
19 #include <asm/uaccess.h>
25 unsigned long pci_memspace_mask = 0xffffffffUL;
28 /* A "nop" PCI implementation. */
29 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
30 unsigned long off, unsigned long len,
35 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
36 unsigned long off, unsigned long len,
43 /* List of all PCI controllers found in the system. */
44 struct pci_controller_info *pci_controller_root = NULL;
46 /* Each PCI controller found gets a unique index. */
47 int pci_num_controllers = 0;
49 /* At boot time the user can give the kernel a command
50 * line option which controls if and how PCI devices
51 * are reordered at PCI bus probing time.
53 int pci_device_reorder = 0;
55 volatile int pci_poke_in_progress;
56 volatile int pci_poke_cpu = -1;
57 volatile int pci_poke_faulted;
59 static spinlock_t pci_poke_lock = SPIN_LOCK_UNLOCKED;
61 void pci_config_read8(u8 *addr, u8 *ret)
66 spin_lock_irqsave(&pci_poke_lock, flags);
67 pci_poke_cpu = smp_processor_id();
68 pci_poke_in_progress = 1;
70 __asm__ __volatile__("membar #Sync\n\t"
71 "lduba [%1] %2, %0\n\t"
74 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
76 pci_poke_in_progress = 0;
78 if (!pci_poke_faulted)
80 spin_unlock_irqrestore(&pci_poke_lock, flags);
83 void pci_config_read16(u16 *addr, u16 *ret)
88 spin_lock_irqsave(&pci_poke_lock, flags);
89 pci_poke_cpu = smp_processor_id();
90 pci_poke_in_progress = 1;
92 __asm__ __volatile__("membar #Sync\n\t"
93 "lduha [%1] %2, %0\n\t"
96 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
98 pci_poke_in_progress = 0;
100 if (!pci_poke_faulted)
102 spin_unlock_irqrestore(&pci_poke_lock, flags);
105 void pci_config_read32(u32 *addr, u32 *ret)
110 spin_lock_irqsave(&pci_poke_lock, flags);
111 pci_poke_cpu = smp_processor_id();
112 pci_poke_in_progress = 1;
113 pci_poke_faulted = 0;
114 __asm__ __volatile__("membar #Sync\n\t"
115 "lduwa [%1] %2, %0\n\t"
118 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
120 pci_poke_in_progress = 0;
122 if (!pci_poke_faulted)
124 spin_unlock_irqrestore(&pci_poke_lock, flags);
127 void pci_config_write8(u8 *addr, u8 val)
131 spin_lock_irqsave(&pci_poke_lock, flags);
132 pci_poke_cpu = smp_processor_id();
133 pci_poke_in_progress = 1;
134 pci_poke_faulted = 0;
135 __asm__ __volatile__("membar #Sync\n\t"
136 "stba %0, [%1] %2\n\t"
139 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
141 pci_poke_in_progress = 0;
143 spin_unlock_irqrestore(&pci_poke_lock, flags);
146 void pci_config_write16(u16 *addr, u16 val)
150 spin_lock_irqsave(&pci_poke_lock, flags);
151 pci_poke_cpu = smp_processor_id();
152 pci_poke_in_progress = 1;
153 pci_poke_faulted = 0;
154 __asm__ __volatile__("membar #Sync\n\t"
155 "stha %0, [%1] %2\n\t"
158 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
160 pci_poke_in_progress = 0;
162 spin_unlock_irqrestore(&pci_poke_lock, flags);
165 void pci_config_write32(u32 *addr, u32 val)
169 spin_lock_irqsave(&pci_poke_lock, flags);
170 pci_poke_cpu = smp_processor_id();
171 pci_poke_in_progress = 1;
172 pci_poke_faulted = 0;
173 __asm__ __volatile__("membar #Sync\n\t"
174 "stwa %0, [%1] %2\n\t"
177 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
179 pci_poke_in_progress = 0;
181 spin_unlock_irqrestore(&pci_poke_lock, flags);
184 /* Probe for all PCI controllers in the system. */
185 extern void sabre_init(int, char *);
186 extern void psycho_init(int, char *);
187 extern void schizo_init(int, char *);
188 extern void schizo_plus_init(int, char *);
189 extern void tomatillo_init(int, char *);
193 void (*init)(int, char *);
194 } pci_controller_table[] __initdata = {
195 { "SUNW,sabre", sabre_init },
196 { "pci108e,a000", sabre_init },
197 { "pci108e,a001", sabre_init },
198 { "SUNW,psycho", psycho_init },
199 { "pci108e,8000", psycho_init },
200 { "SUNW,schizo", schizo_init },
201 { "pci108e,8001", schizo_init },
202 { "SUNW,schizo+", schizo_plus_init },
203 { "pci108e,8002", schizo_plus_init },
204 { "SUNW,tomatillo", tomatillo_init },
205 { "pci108e,a801", tomatillo_init },
207 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
208 sizeof(pci_controller_table[0]))
210 static int __init pci_controller_init(char *model_name, int namelen, int node)
214 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
215 if (!strncmp(model_name,
216 pci_controller_table[i].model_name,
218 pci_controller_table[i].init(node, model_name);
222 printk("PCI: Warning unknown controller, model name [%s]\n",
224 printk("PCI: Ignoring controller...\n");
229 static int __init pci_is_controller(char *model_name, int namelen, int node)
233 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
234 if (!strncmp(model_name,
235 pci_controller_table[i].model_name,
243 static int __init pci_controller_scan(int (*handler)(char *, int, int))
249 node = prom_getchild(prom_root_node);
250 while ((node = prom_searchsiblings(node, "pci")) != 0) {
253 if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 ||
254 (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) {
257 /* Our value may be a multi-valued string in the
258 * case of some compatible properties. For sanity,
259 * only try the first one. */
261 while (namebuf[item_len] && len) {
266 if (handler(namebuf, item_len, node))
270 node = prom_getsibling(node);
279 /* Is there some PCI controller in the system? */
280 int __init pcic_present(void)
282 return pci_controller_scan(pci_is_controller);
285 /* Find each controller in the system, attach and initialize
286 * software state structure for each and link into the
287 * pci_controller_root. Setup the controller enough such
288 * that bus scanning can be done.
290 static void __init pci_controller_probe(void)
292 printk("PCI: Probing for controllers.\n");
294 pci_controller_scan(pci_controller_init);
297 static void __init pci_scan_each_controller_bus(void)
299 struct pci_controller_info *p;
301 for (p = pci_controller_root; p; p = p->next)
305 /* Reorder the pci_dev chain, so that onboard devices come first
306 * and then come the pluggable cards.
308 static void __init pci_reorder_devs(void)
310 struct list_head *pci_onboard = &pci_devices;
311 struct list_head *walk = pci_onboard->next;
313 while (walk != pci_onboard) {
314 struct pci_dev *pdev = pci_dev_g(walk);
315 struct list_head *walk_next = walk->next;
317 if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
319 list_add(walk, pci_onboard);
326 extern void clock_probe(void);
327 extern void power_init(void);
329 static int __init pcibios_init(void)
331 pci_controller_probe();
332 if (pci_controller_root == NULL)
335 pci_scan_each_controller_bus();
337 if (pci_device_reorder)
348 subsys_initcall(pcibios_init);
350 void pcibios_fixup_bus(struct pci_bus *pbus)
352 struct pci_pbm_info *pbm = pbus->sysdata;
354 /* Generic PCI bus probing sets these to point at
355 * &io{port,mem}_resouce which is wrong for us.
357 pbus->resource[0] = &pbm->io_space;
358 pbus->resource[1] = &pbm->mem_space;
361 int pci_claim_resource(struct pci_dev *pdev, int resource)
363 struct pci_pbm_info *pbm = pdev->bus->sysdata;
364 struct resource *res = &pdev->resource[resource];
365 struct resource *root;
370 if (res->flags & IORESOURCE_IO)
371 root = &pbm->io_space;
373 root = &pbm->mem_space;
375 pbm->parent->resource_adjust(pdev, res, root);
377 return request_resource(root, res);
381 * Given the PCI bus a device resides on, try to
382 * find an acceptable resource allocation for a
383 * specific device resource..
385 static int pci_assign_bus_resource(const struct pci_bus *bus,
387 struct resource *res,
392 unsigned int type_mask;
395 type_mask = IORESOURCE_IO | IORESOURCE_MEM;
396 for (i = 0 ; i < 4; i++) {
397 struct resource *r = bus->resource[i];
401 /* type_mask must match */
402 if ((res->flags ^ r->flags) & type_mask)
405 /* Ok, try it out.. */
406 if (allocate_resource(r, res, size, min, -1, size, NULL, NULL) < 0)
409 /* PCI config space updated by caller. */
415 int pci_assign_resource(struct pci_dev *pdev, int resource)
417 struct pcidev_cookie *pcp = pdev->sysdata;
418 struct pci_pbm_info *pbm = pcp->pbm;
419 struct resource *res = &pdev->resource[resource];
420 unsigned long min, size;
423 if (res->flags & IORESOURCE_IO)
424 min = pbm->io_space.start + 0x400UL;
426 min = pbm->mem_space.start;
428 size = res->end - res->start + 1;
430 err = pci_assign_bus_resource(pdev->bus, pdev, res, size, min, resource);
433 printk("PCI: Failed to allocate resource %d for %s\n",
434 resource, pci_name(pdev));
436 /* Update PCI config space. */
437 pbm->parent->base_address_update(pdev, resource);
443 /* Sort resources by alignment */
444 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
448 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
450 struct resource_list *list, *tmp;
451 unsigned long r_align;
453 r = &dev->resource[i];
454 r_align = r->end - r->start;
456 if (!(r->flags) || r->parent)
459 printk(KERN_WARNING "PCI: Ignore bogus resource %d "
461 i, r->start, r->end, pci_name(dev));
464 r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
465 for (list = head; ; list = list->next) {
466 unsigned long align = 0;
467 struct resource_list *ln = list->next;
471 idx = ln->res - &ln->dev->resource[0];
472 align = (idx < PCI_BRIDGE_RESOURCES) ?
473 ln->res->end - ln->res->start + 1 :
476 if (r_align > align) {
477 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
479 panic("pdev_sort_resources(): "
480 "kmalloc() failed!\n");
491 void pcibios_update_irq(struct pci_dev *pdev, int irq)
495 void pcibios_align_resource(void *data, struct resource *res,
496 unsigned long size, unsigned long align)
500 int pcibios_enable_device(struct pci_dev *pdev, int mask)
505 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
506 struct resource *res)
508 struct pci_pbm_info *pbm = pdev->bus->sysdata;
509 struct resource zero_res, *root;
513 zero_res.flags = res->flags;
515 if (res->flags & IORESOURCE_IO)
516 root = &pbm->io_space;
518 root = &pbm->mem_space;
520 pbm->parent->resource_adjust(pdev, &zero_res, root);
522 region->start = res->start - zero_res.start;
523 region->end = res->end - zero_res.start;
526 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
527 struct pci_bus_region *region)
529 struct pci_pbm_info *pbm = pdev->bus->sysdata;
530 struct resource *root;
532 res->start = region->start;
533 res->end = region->end;
535 if (res->flags & IORESOURCE_IO)
536 root = &pbm->io_space;
538 root = &pbm->mem_space;
540 pbm->parent->resource_adjust(pdev, res, root);
543 char * __init pcibios_setup(char *str)
545 if (!strcmp(str, "onboardfirst")) {
546 pci_device_reorder = 1;
549 if (!strcmp(str, "noreorder")) {
550 pci_device_reorder = 0;
556 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
558 /* If the user uses a host-bridge as the PCI device, he may use
559 * this to perform a raw mmap() of the I/O or MEM space behind
562 * This can be useful for execution of x86 PCI bios initialization code
563 * on a PCI card, like the xfree86 int10 stuff does.
565 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
566 enum pci_mmap_state mmap_state)
568 struct pcidev_cookie *pcp = pdev->sysdata;
569 struct pci_pbm_info *pbm;
570 struct pci_controller_info *p;
571 unsigned long space_size, user_offset, user_size;
580 if (p->pbms_same_domain) {
581 unsigned long lowest, highest;
583 lowest = ~0UL; highest = 0UL;
584 if (mmap_state == pci_mmap_io) {
585 if (p->pbm_A.io_space.flags) {
586 lowest = p->pbm_A.io_space.start;
587 highest = p->pbm_A.io_space.end + 1;
589 if (p->pbm_B.io_space.flags) {
590 if (lowest > p->pbm_B.io_space.start)
591 lowest = p->pbm_B.io_space.start;
592 if (highest < p->pbm_B.io_space.end + 1)
593 highest = p->pbm_B.io_space.end + 1;
595 space_size = highest - lowest;
597 if (p->pbm_A.mem_space.flags) {
598 lowest = p->pbm_A.mem_space.start;
599 highest = p->pbm_A.mem_space.end + 1;
601 if (p->pbm_B.mem_space.flags) {
602 if (lowest > p->pbm_B.mem_space.start)
603 lowest = p->pbm_B.mem_space.start;
604 if (highest < p->pbm_B.mem_space.end + 1)
605 highest = p->pbm_B.mem_space.end + 1;
607 space_size = highest - lowest;
610 if (mmap_state == pci_mmap_io) {
611 space_size = (pbm->io_space.end -
612 pbm->io_space.start) + 1;
614 space_size = (pbm->mem_space.end -
615 pbm->mem_space.start) + 1;
619 /* Make sure the request is in range. */
620 user_offset = vma->vm_pgoff << PAGE_SHIFT;
621 user_size = vma->vm_end - vma->vm_start;
623 if (user_offset >= space_size ||
624 (user_offset + user_size) > space_size)
627 if (p->pbms_same_domain) {
628 unsigned long lowest = ~0UL;
630 if (mmap_state == pci_mmap_io) {
631 if (p->pbm_A.io_space.flags)
632 lowest = p->pbm_A.io_space.start;
633 if (p->pbm_B.io_space.flags &&
634 lowest > p->pbm_B.io_space.start)
635 lowest = p->pbm_B.io_space.start;
637 if (p->pbm_A.mem_space.flags)
638 lowest = p->pbm_A.mem_space.start;
639 if (p->pbm_B.mem_space.flags &&
640 lowest > p->pbm_B.mem_space.start)
641 lowest = p->pbm_B.mem_space.start;
643 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
645 if (mmap_state == pci_mmap_io) {
646 vma->vm_pgoff = (pbm->io_space.start +
647 user_offset) >> PAGE_SHIFT;
649 vma->vm_pgoff = (pbm->mem_space.start +
650 user_offset) >> PAGE_SHIFT;
657 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
658 * to the 32-bit pci bus offset for DEV requested by the user.
660 * Basically, the user finds the base address for his device which he wishes
661 * to mmap. They read the 32-bit value from the config space base register,
662 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
663 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
665 * Returns negative error code on failure, zero on success.
667 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
668 enum pci_mmap_state mmap_state)
670 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
671 unsigned long user32 = user_offset & pci_memspace_mask;
672 unsigned long largest_base, this_base, addr32;
675 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
676 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
678 /* Figure out which base address this is for. */
680 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
681 struct resource *rp = &dev->resource[i];
688 if (i == PCI_ROM_RESOURCE) {
689 if (mmap_state != pci_mmap_mem)
692 if ((mmap_state == pci_mmap_io &&
693 (rp->flags & IORESOURCE_IO) == 0) ||
694 (mmap_state == pci_mmap_mem &&
695 (rp->flags & IORESOURCE_MEM) == 0))
699 this_base = rp->start;
701 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
703 if (mmap_state == pci_mmap_io)
706 if (addr32 <= user32 && this_base > largest_base)
707 largest_base = this_base;
710 if (largest_base == 0UL)
713 /* Now construct the final physical address. */
714 if (mmap_state == pci_mmap_io)
715 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
717 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
722 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
725 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
726 enum pci_mmap_state mmap_state)
728 vma->vm_flags |= (VM_SHM | VM_LOCKED);
731 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
734 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
735 enum pci_mmap_state mmap_state)
737 /* Our io_remap_page_range takes care of this, do nothing. */
740 extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, unsigned long offset,
741 unsigned long size, pgprot_t prot, int space);
743 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
744 * for this architecture. The region in the process to map is described by vm_start
745 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
746 * The pci device structure is provided so that architectures may make mapping
747 * decisions on a per-device or per-bus basis.
749 * Returns a negative error code on failure, zero on success.
751 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
752 enum pci_mmap_state mmap_state,
757 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
761 __pci_mmap_set_flags(dev, vma, mmap_state);
762 __pci_mmap_set_pgprot(dev, vma, mmap_state);
764 ret = io_remap_page_range(vma, vma->vm_start,
765 (vma->vm_pgoff << PAGE_SHIFT |
766 (write_combine ? 0x1UL : 0x0UL)),
767 vma->vm_end - vma->vm_start, vma->vm_page_prot, 0);
771 vma->vm_flags |= VM_IO;
775 /* Return the domain nuber for this pci bus */
777 int pci_domain_nr(struct pci_bus *pbus)
779 struct pci_pbm_info *pbm = pbus->sysdata;
782 if (pbm == NULL || pbm->parent == NULL) {
785 struct pci_controller_info *p = pbm->parent;
788 if (p->pbms_same_domain == 0)
790 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
795 EXPORT_SYMBOL(pci_domain_nr);
797 int pci_name_bus(char *name, struct pci_bus *bus)
799 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
803 int pcibios_prep_mwi(struct pci_dev *dev)
805 /* We set correct PCI_CACHE_LINE_SIZE register values for every
806 * device probed on this platform. So there is nothing to check
807 * and this always succeeds.
812 #endif /* !(CONFIG_PCI) */