1 /* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
2 * trampoline.S: Jump start slave processors on sparc64.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
12 #include <asm/pstate.h>
14 #include <asm/pgtable.h>
15 #include <asm/spitfire.h>
16 #include <asm/processor.h>
17 #include <asm/thread_info.h>
25 .asciz "SUNW,itlb-load"
28 .asciz "SUNW,dtlb-load"
32 .globl sparc64_cpu_startup, sparc64_cpu_startup_end
36 BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_startup)
37 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_startup)
39 ba,pt %xcc, spitfire_startup
43 /* Preserve OBP chosen DCU and DCR register settings. */
44 ba,pt %xcc, cheetah_generic_startup
48 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
51 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
52 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
54 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
55 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
58 cheetah_generic_startup:
59 mov TSB_EXTENSION_P, %g3
60 stxa %g0, [%g3] ASI_DMMU
61 stxa %g0, [%g3] ASI_IMMU
64 mov TSB_EXTENSION_S, %g3
65 stxa %g0, [%g3] ASI_DMMU
68 mov TSB_EXTENSION_N, %g3
69 stxa %g0, [%g3] ASI_DMMU
70 stxa %g0, [%g3] ASI_IMMU
73 /* Disable STICK_INT interrupts. */
74 sethi %hi(0x80000000), %g5
78 ba,pt %xcc, startup_continue
82 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
83 stxa %g1, [%g0] ASI_LSU_CONTROL
89 sethi %hi(0x80000000), %g2
93 /* Call OBP by hand to lock KERNBASE into i/d tlbs.
94 * We lock 2 consequetive entries if we are 'bigkernel'.
98 sethi %hi(prom_entry_lock), %g2
99 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
101 membar #StoreLoad | #StoreStore
103 sethi %hi(p1275buf), %g2
104 or %g2, %lo(p1275buf), %g2
105 ldx [%g2 + 0x10], %l2
107 add %l2, -(192 + 128), %sp
110 sethi %hi(call_method), %g2
111 or %g2, %lo(call_method), %g2
112 stx %g2, [%sp + 2047 + 128 + 0x00]
114 stx %g2, [%sp + 2047 + 128 + 0x08]
116 stx %g2, [%sp + 2047 + 128 + 0x10]
117 sethi %hi(itlb_load), %g2
118 or %g2, %lo(itlb_load), %g2
119 stx %g2, [%sp + 2047 + 128 + 0x18]
120 sethi %hi(mmu_ihandle_cache), %g2
121 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2
122 stx %g2, [%sp + 2047 + 128 + 0x20]
123 sethi %hi(KERNBASE), %g2
124 stx %g2, [%sp + 2047 + 128 + 0x28]
125 sethi %hi(kern_locked_tte_data), %g2
126 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
127 stx %g2, [%sp + 2047 + 128 + 0x30]
130 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
134 stx %g2, [%sp + 2047 + 128 + 0x38]
135 sethi %hi(p1275buf), %g2
136 or %g2, %lo(p1275buf), %g2
137 ldx [%g2 + 0x08], %o1
139 add %sp, (2047 + 128), %o0
141 sethi %hi(bigkernel), %g2
142 lduw [%g2 + %lo(bigkernel)], %g2
147 sethi %hi(call_method), %g2
148 or %g2, %lo(call_method), %g2
149 stx %g2, [%sp + 2047 + 128 + 0x00]
151 stx %g2, [%sp + 2047 + 128 + 0x08]
153 stx %g2, [%sp + 2047 + 128 + 0x10]
154 sethi %hi(itlb_load), %g2
155 or %g2, %lo(itlb_load), %g2
156 stx %g2, [%sp + 2047 + 128 + 0x18]
157 sethi %hi(mmu_ihandle_cache), %g2
158 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2
159 stx %g2, [%sp + 2047 + 128 + 0x20]
160 sethi %hi(KERNBASE + 0x400000), %g2
161 stx %g2, [%sp + 2047 + 128 + 0x28]
162 sethi %hi(kern_locked_tte_data), %g2
163 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
164 sethi %hi(0x400000), %g1
166 stx %g2, [%sp + 2047 + 128 + 0x30]
169 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
173 stx %g2, [%sp + 2047 + 128 + 0x38]
174 sethi %hi(p1275buf), %g2
175 or %g2, %lo(p1275buf), %g2
176 ldx [%g2 + 0x08], %o1
178 add %sp, (2047 + 128), %o0
181 sethi %hi(call_method), %g2
182 or %g2, %lo(call_method), %g2
183 stx %g2, [%sp + 2047 + 128 + 0x00]
185 stx %g2, [%sp + 2047 + 128 + 0x08]
187 stx %g2, [%sp + 2047 + 128 + 0x10]
188 sethi %hi(dtlb_load), %g2
189 or %g2, %lo(dtlb_load), %g2
190 stx %g2, [%sp + 2047 + 128 + 0x18]
191 sethi %hi(mmu_ihandle_cache), %g2
192 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2
193 stx %g2, [%sp + 2047 + 128 + 0x20]
194 sethi %hi(KERNBASE), %g2
195 stx %g2, [%sp + 2047 + 128 + 0x28]
196 sethi %hi(kern_locked_tte_data), %g2
197 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
198 stx %g2, [%sp + 2047 + 128 + 0x30]
201 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
206 stx %g2, [%sp + 2047 + 128 + 0x38]
207 sethi %hi(p1275buf), %g2
208 or %g2, %lo(p1275buf), %g2
209 ldx [%g2 + 0x08], %o1
211 add %sp, (2047 + 128), %o0
213 sethi %hi(bigkernel), %g2
214 lduw [%g2 + %lo(bigkernel)], %g2
216 be,pt %icc, do_unlock
219 sethi %hi(call_method), %g2
220 or %g2, %lo(call_method), %g2
221 stx %g2, [%sp + 2047 + 128 + 0x00]
223 stx %g2, [%sp + 2047 + 128 + 0x08]
225 stx %g2, [%sp + 2047 + 128 + 0x10]
226 sethi %hi(dtlb_load), %g2
227 or %g2, %lo(dtlb_load), %g2
228 stx %g2, [%sp + 2047 + 128 + 0x18]
229 sethi %hi(mmu_ihandle_cache), %g2
230 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2
231 stx %g2, [%sp + 2047 + 128 + 0x20]
232 sethi %hi(KERNBASE + 0x400000), %g2
233 stx %g2, [%sp + 2047 + 128 + 0x28]
234 sethi %hi(kern_locked_tte_data), %g2
235 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
236 sethi %hi(0x400000), %g1
238 stx %g2, [%sp + 2047 + 128 + 0x30]
241 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
246 stx %g2, [%sp + 2047 + 128 + 0x38]
247 sethi %hi(p1275buf), %g2
248 or %g2, %lo(p1275buf), %g2
249 ldx [%g2 + 0x08], %o1
251 add %sp, (2047 + 128), %o0
254 sethi %hi(prom_entry_lock), %g2
255 stb %g0, [%g2 + %lo(prom_entry_lock)]
256 membar #StoreStore | #StoreLoad
263 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
266 /* XXX Buggy PROM... */
272 mov PRIMARY_CONTEXT, %g7
273 stxa %g0, [%g7] ASI_DMMU
275 mov SECONDARY_CONTEXT, %g7
276 stxa %g0, [%g7] ASI_DMMU
280 sllx %g5, THREAD_SHIFT, %g5
281 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
288 /* Setup the trap globals, then we can resurface. */
291 wrpr %o1, PSTATE_AG, %pstate
292 sethi %hi(sparc64_ttable_tl0), %g5
296 wrpr %o1, PSTATE_MG, %pstate
297 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
298 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
301 stxa %g0, [%g1] ASI_DMMU
304 sethi %uhi(KERN_HIGHBITS), %g2
305 or %g2, %ulo(KERN_HIGHBITS), %g2
307 or %g2, KERN_LOWBITS, %g2
309 BRANCH_IF_ANY_CHEETAH(g3,g7,9f)
315 sethi %uhi(VPTE_BASE_CHEETAH), %g3
316 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
320 sethi %uhi(VPTE_BASE_SPITFIRE), %g3
321 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
329 wrpr %o1, 0x0, %pstate
330 ldx [%g6 + TI_TASK], %g4
334 call init_irqwork_curcpu
338 or %o1, PSTATE_IE, %o1
341 call prom_set_trap_table
342 sethi %hi(sparc64_ttable_tl0), %o0
353 sparc64_cpu_startup_end: