1 /* clear_page.S: UltraSparc optimized copy page.
3 * Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com)
7 #include <asm/visasm.h>
8 #include <asm/thread_info.h>
10 #include <asm/pgtable.h>
11 #include <asm/spitfire.h>
14 /* What we used to do was lock a TLB entry into a specific
15 * TLB slot, clear the page with interrupts disabled, then
16 * restore the original TLB entry. This was great for
17 * disturbing the TLB as little as possible, but it meant
18 * we had to keep interrupts disabled for a long time.
20 * Now, we simply use the normal TLB loading mechanism,
21 * and this makes the cpu choose a slot all by itself.
22 * Then we do a normal TLB flush on exit. We need only
23 * disable preemption during the clear.
26 #define TTE_BITS_TOP (_PAGE_VALID | _PAGE_SZBITS)
27 #define TTE_BITS_BOTTOM (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W)
28 #define DCACHE_SIZE (PAGE_SIZE * 2)
30 #if (PAGE_SHIFT == 13) || (PAGE_SHIFT == 19)
31 #define PAGE_SIZE_REM 0x80
32 #elif (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)
33 #define PAGE_SIZE_REM 0x100
35 #error Wrong PAGE_SHIFT specified
38 #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \
39 fmovd %reg0, %f48; fmovd %reg1, %f50; \
40 fmovd %reg2, %f52; fmovd %reg3, %f54; \
41 fmovd %reg4, %f56; fmovd %reg5, %f58; \
42 fmovd %reg6, %f60; fmovd %reg7, %f62;
48 copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
49 lduw [%g6 + TI_PRE_COUNT], %o4
50 sethi %uhi(PAGE_OFFSET), %g2
51 sethi %hi(PAGE_SIZE), %o3
54 sethi %uhi(TTE_BITS_TOP), %g3
57 sub %o0, %g2, %g1 ! dest paddr
59 sub %o1, %g2, %g2 ! src paddr
60 or %g3, TTE_BITS_BOTTOM, %g3
62 and %o2, %o3, %o0 ! vaddr D-cache alias bit
63 or %g1, %g3, %g1 ! dest TTE data
65 or %g2, %g3, %g2 ! src TTE data
66 sethi %hi(TLBTEMP_BASE), %o3
68 sethi %hi(DCACHE_SIZE), %o1
69 add %o0, %o3, %o0 ! dest TTE vaddr
72 add %o0, %o1, %o1 ! src TTE vaddr
74 /* Disable preemption. */
75 mov TLB_TAG_ACCESS, %g3
76 stw %o2, [%g6 + TI_PRE_COUNT]
78 /* Load TLB entries. */
80 wrpr %o2, PSTATE_IE, %pstate
81 stxa %o0, [%g3] ASI_DMMU
82 stxa %g1, [%g0] ASI_DTLB_DATA_IN
84 stxa %o1, [%g3] ASI_DMMU
85 stxa %g2, [%g0] ASI_DTLB_DATA_IN
87 wrpr %o2, 0x0, %pstate
89 BRANCH_IF_ANY_CHEETAH(g3,o2,1f)
95 membar #StoreLoad | #StoreStore | #LoadStore
96 sethi %hi((PAGE_SIZE/64)-2), %o2
98 prefetch [%o1 + 0x000], #one_read
99 or %o2, %lo((PAGE_SIZE/64)-2), %o2
100 prefetch [%o1 + 0x040], #one_read
101 prefetch [%o1 + 0x080], #one_read
102 prefetch [%o1 + 0x0c0], #one_read
103 ldd [%o1 + 0x000], %f0
104 prefetch [%o1 + 0x100], #one_read
105 ldd [%o1 + 0x008], %f2
106 prefetch [%o1 + 0x140], #one_read
107 ldd [%o1 + 0x010], %f4
108 prefetch [%o1 + 0x180], #one_read
110 ldd [%o1 + 0x018], %f6
112 ldd [%o1 + 0x020], %f8
114 ldd [%o1 + 0x028], %f10
116 ldd [%o1 + 0x030], %f12
118 ldd [%o1 + 0x038], %f14
120 ldd [%o1 + 0x040], %f0
121 1: ldd [%o1 + 0x048], %f2
123 ldd [%o1 + 0x050], %f4
125 stda %f16, [%o0] ASI_BLK_P
126 ldd [%o1 + 0x058], %f6
128 ldd [%o1 + 0x060], %f8
130 ldd [%o1 + 0x068], %f10
132 ldd [%o1 + 0x070], %f12
134 ldd [%o1 + 0x078], %f14
136 ldd [%o1 + 0x080], %f0
137 prefetch [%o1 + 0x180], #one_read
144 ldd [%o1 + 0x048], %f2
146 ldd [%o1 + 0x050], %f4
148 stda %f16, [%o0] ASI_BLK_P
149 ldd [%o1 + 0x058], %f6
151 ldd [%o1 + 0x060], %f8
153 ldd [%o1 + 0x068], %f10
155 ldd [%o1 + 0x070], %f12
158 ldd [%o1 + 0x078], %f14
163 stda %f16, [%o0] ASI_BLK_P
171 ldub [%g6 + TI_FAULT_CODE], %g3
176 wr %g0, ASI_BLK_P, %asi
177 wr %g0, ASI_BLK_COMMIT_P, %asi
178 1: ldda [%o1] ASI_BLK_P, %f0
180 ldda [%o1] ASI_BLK_P, %f16
182 sethi %hi(PAGE_SIZE), %o2
183 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
184 ldda [%o1] ASI_BLK_P, %f32
185 stda %f48, [%o0] %asi
189 TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
190 ldda [%o1] ASI_BLK_P, %f0
191 stda %f48, [%o0] %asi
195 TOUCH(f32, f34, f36, f38, f40, f42, f44, f46)
196 ldda [%o1] ASI_BLK_P, %f16
197 stda %f48, [%o0] %asi
200 cmp %o2, PAGE_SIZE_REM
203 #if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)
204 TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
205 ldda [%o1] ASI_BLK_P, %f32
206 stda %f48, [%o0] %asi
210 TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
211 ldda [%o1] ASI_BLK_P, %f0
212 stda %f48, [%o0] %asi
217 stda %f32, [%o0] %asi
224 stda %f16, [%o0] %asi
231 stxa %g0, [%g1] ASI_DMMU_DEMAP
234 sethi %hi(DCACHE_SIZE), %g2
235 stxa %g0, [%g1 + %g2] ASI_DMMU_DEMAP
239 stw %o4, [%g6 + TI_PRE_COUNT]