arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/head.h>
  24 #include <asm/system.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/oplib.h>
  29 #include <asm/iommu.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/dma.h>
  35 #include <asm/starfire.h>
  36 #include <asm/tlb.h>
  37 #include <asm/spitfire.h>
  38 #include <asm/sections.h>
  39
  40 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  41
  42 extern void device_scan(void);
  43
  44 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
  45
  46 unsigned long *sparc64_valid_addr_bitmap;
  47
  48 /* Ugly, but necessary... -DaveM */
  49 unsigned long phys_base;
  50 unsigned long kern_base;
  51 unsigned long kern_size;
  52 unsigned long pfn_base;
  53
  54 /* This is even uglier. We have a problem where the kernel may not be
  55  * located at phys_base. However, initial __alloc_bootmem() calls need to
  56  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
  57  * those page mappings wont work. Things are ok after inherit_prom_mappings
  58  * is called though. Dave says he'll clean this up some other time.
  59  * -- BenC
  60  */
  61 static unsigned long bootmap_base;
  62
  63 /* get_new_mmu_context() uses "cache + 1".  */
  64 spinlock_t ctx_alloc_lock = SPIN_LOCK_UNLOCKED;
  65 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
  66 #define CTX_BMAP_SLOTS (1UL << (CTX_VERSION_SHIFT - 6))
  67 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
  68
  69 /* References to special section boundaries */
  70 extern char  _start[], _end[];
  71
  72 /* Initial ramdisk setup */
  73 extern unsigned int sparc_ramdisk_image;
  74 extern unsigned int sparc_ramdisk_size;
  75
  76 struct page *mem_map_zero;
  77
  78 int bigkernel = 0;
  79
  80 /* XXX Tune this... */
  81 #define PGT_CACHE_LOW   25
  82 #define PGT_CACHE_HIGH  50
  83
  84 void check_pgt_cache(void)
  85 {
  86         preempt_disable();
  87         if (pgtable_cache_size > PGT_CACHE_HIGH) {
  88                 do {
  89 #ifdef CONFIG_SMP
  90                         if (pgd_quicklist)
  91                                 free_pgd_slow(get_pgd_fast());
  92 #endif
  93                         if (pte_quicklist[0])
  94                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
  95                         if (pte_quicklist[1])
  96                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
  97                 } while (pgtable_cache_size > PGT_CACHE_LOW);
  98         }
  99 #ifndef CONFIG_SMP
 100         if (pgd_cache_size > PGT_CACHE_HIGH / 4) {
 101                 struct page *page, *page2;
 102                 for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) {
 103                         if ((unsigned long)page->lru.prev == 3) {
 104                                 if (page2)
 105                                         page2->lru.next = page->lru.next;
 106                                 else
 107                                         pgd_quicklist = (void *) page->lru.next;
 108                                 pgd_cache_size -= 2;
 109                                 __free_page(page);
 110                                 if (page2)
 111                                         page = (struct page *)page2->lru.next;
 112                                 else
 113                                         page = (struct page *)pgd_quicklist;
 114                                 if (pgd_cache_size <= PGT_CACHE_LOW / 4)
 115                                         break;
 116                                 continue;
 117                         }
 118                         page2 = page;
 119                         page = (struct page *)page->lru.next;
 120                 }
 121         }
 122 #endif
 123         preempt_enable();
 124 }
 125
 126 #ifdef CONFIG_DEBUG_DCFLUSH
 127 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 128 #ifdef CONFIG_SMP
 129 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 130 #endif
 131 #endif
 132
 133 __inline__ void flush_dcache_page_impl(struct page *page)
 134 {
 135 #ifdef CONFIG_DEBUG_DCFLUSH
 136         atomic_inc(&dcpage_flushes);
 137 #endif
 138
 139 #if (L1DCACHE_SIZE > PAGE_SIZE)
 140         __flush_dcache_page(page->virtual,
 141                             ((tlb_type == spitfire) &&
 142                              page_mapping(page) != NULL));
 143 #else
 144         if (page_mapping(page) != NULL &&
 145             tlb_type == spitfire)
 146                 __flush_icache_page(__pa(page->virtual));
 147 #endif
 148 }
 149
 150 #define PG_dcache_dirty         PG_arch_1
 151
 152 #define dcache_dirty_cpu(page) \
 153         (((page)->flags >> 24) & (NR_CPUS - 1UL))
 154
 155 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 156 {
 157         unsigned long mask = this_cpu;
 158         unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 159         mask = (mask << 24) | (1UL << PG_dcache_dirty);
 160         __asm__ __volatile__("1:\n\t"
 161                              "ldx       [%2], %%g7\n\t"
 162                              "and       %%g7, %1, %%g5\n\t"
 163                              "or        %%g5, %0, %%g5\n\t"
 164                              "casx      [%2], %%g7, %%g5\n\t"
 165                              "cmp       %%g7, %%g5\n\t"
 166                              "bne,pn    %%xcc, 1b\n\t"
 167                              " membar   #StoreLoad | #StoreStore"
 168                              : /* no outputs */
 169                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 170                              : "g5", "g7");
 171 }
 172
 173 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 174 {
 175         unsigned long mask = (1UL << PG_dcache_dirty);
 176
 177         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 178                              "1:\n\t"
 179                              "ldx       [%2], %%g7\n\t"
 180                              "srlx      %%g7, 24, %%g5\n\t"
 181                              "and       %%g5, %3, %%g5\n\t"
 182                              "cmp       %%g5, %0\n\t"
 183                              "bne,pn    %%icc, 2f\n\t"
 184                              " andn     %%g7, %1, %%g5\n\t"
 185                              "casx      [%2], %%g7, %%g5\n\t"
 186                              "cmp       %%g7, %%g5\n\t"
 187                              "bne,pn    %%xcc, 1b\n\t"
 188                              " membar   #StoreLoad | #StoreStore\n"
 189                              "2:"
 190                              : /* no outputs */
 191                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 192                                "i" (NR_CPUS - 1UL)
 193                              : "g5", "g7");
 194 }
 195
 196 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
 197
 198 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 199 {
 200         struct page *page;
 201         unsigned long pfn;
 202         unsigned long pg_flags;
 203
 204         pfn = pte_pfn(pte);
 205         if (pfn_valid(pfn) &&
 206             (page = pfn_to_page(pfn), page_mapping(page)) &&
 207             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 208                 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 209                 int this_cpu = get_cpu();
 210
 211                 /* This is just to optimize away some function calls
 212                  * in the SMP case.
 213                  */
 214                 if (cpu == this_cpu)
 215                         flush_dcache_page_impl(page);
 216                 else
 217                         smp_flush_dcache_page_impl(page, cpu);
 218
 219                 clear_dcache_dirty_cpu(page, cpu);
 220
 221                 put_cpu();
 222         }
 223         if (get_thread_fault_code())
 224                 __update_mmu_cache(vma->vm_mm->context & TAG_CONTEXT_BITS,
 225                                    address, pte, get_thread_fault_code());
 226 }
 227
 228 void flush_dcache_page(struct page *page)
 229 {
 230         struct address_space *mapping = page_mapping(page);
 231         int dirty = test_bit(PG_dcache_dirty, &page->flags);
 232         int dirty_cpu = dcache_dirty_cpu(page);
 233         int this_cpu = get_cpu();
 234
 235         if (mapping && !mapping_mapped(mapping)) {
 236                 if (dirty) {
 237                         if (dirty_cpu == this_cpu)
 238                                 goto out;
 239                         smp_flush_dcache_page_impl(page, dirty_cpu);
 240                 }
 241                 set_dcache_dirty(page, this_cpu);
 242         } else {
 243                 /* We could delay the flush for the !page_mapping
 244                  * case too.  But that case is for exec env/arg
 245                  * pages and those are %99 certainly going to get
 246                  * faulted into the tlb (and thus flushed) anyways.
 247                  */
 248                 flush_dcache_page_impl(page);
 249         }
 250
 251 out:
 252         put_cpu();
 253 }
 254
 255 /* When shared+writable mmaps of files go away, we lose all dirty
 256  * page state, so we have to deal with D-cache aliasing here.
 257  *
 258  * This code relies on the fact that flush_cache_range() is always
 259  * called for an area composed by a single VMA.  It also assumes that
 260  * the MM's page_table_lock is held.
 261  */
 262 static inline void flush_cache_pte_range(struct mm_struct *mm, pmd_t *pmd, unsigned long address, unsigned long size)
 263 {
 264         unsigned long offset;
 265         pte_t *ptep;
 266
 267         if (pmd_none(*pmd))
 268                 return;
 269         ptep = pte_offset_map(pmd, address);
 270         offset = address & ~PMD_MASK;
 271         if (offset + size > PMD_SIZE)
 272                 size = PMD_SIZE - offset;
 273         size &= PAGE_MASK;
 274         for (offset = 0; offset < size; ptep++, offset += PAGE_SIZE) {
 275                 pte_t pte = *ptep;
 276
 277                 if (pte_none(pte))
 278                         continue;
 279
 280                 if (pte_present(pte) && pte_dirty(pte)) {
 281                         struct page *page;
 282                         unsigned long pgaddr, uaddr;
 283                         unsigned long pfn = pte_pfn(pte);
 284
 285                         if (!pfn_valid(pfn))
 286                                 continue;
 287                         page = pfn_to_page(pfn);
 288                         if (PageReserved(page) || !page_mapping(page))
 289                                 continue;
 290                         pgaddr = (unsigned long) page_address(page);
 291                         uaddr = address + offset;
 292                         if ((pgaddr ^ uaddr) & (1 << 13))
 293                                 flush_dcache_page_all(mm, page);
 294                 }
 295         }
 296         pte_unmap(ptep - 1);
 297 }
 298
 299 static inline void flush_cache_pmd_range(struct mm_struct *mm, pgd_t *dir, unsigned long address, unsigned long size)
 300 {
 301         pmd_t *pmd;
 302         unsigned long end;
 303
 304         if (pgd_none(*dir))
 305                 return;
 306         pmd = pmd_offset(dir, address);
 307         end = address + size;
 308         if (end > ((address + PGDIR_SIZE) & PGDIR_MASK))
 309                 end = ((address + PGDIR_SIZE) & PGDIR_MASK);
 310         do {
 311                 flush_cache_pte_range(mm, pmd, address, end - address);
 312                 address = (address + PMD_SIZE) & PMD_MASK;
 313                 pmd++;
 314         } while (address < end);
 315 }
 316
 317 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 318 {
 319         struct mm_struct *mm = vma->vm_mm;
 320         pgd_t *dir = pgd_offset(mm, start);
 321
 322         if (mm == current->mm)
 323                 flushw_user();
 324
 325         if (vma->vm_file == NULL ||
 326             ((vma->vm_flags & (VM_SHARED|VM_WRITE)) != (VM_SHARED|VM_WRITE)))
 327                 return;
 328
 329         do {
 330                 flush_cache_pmd_range(mm, dir, start, end - start);
 331                 start = (start + PGDIR_SIZE) & PGDIR_MASK;
 332                 dir++;
 333         } while (start && (start < end));
 334 }
 335
 336 void flush_icache_range(unsigned long start, unsigned long end)
 337 {
 338         /* Cheetah has coherent I-cache. */
 339         if (tlb_type == spitfire) {
 340                 unsigned long kaddr;
 341
 342                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 343                         __flush_icache_page(__get_phys(kaddr));
 344         }
 345 }
 346
 347 void show_mem(void)
 348 {
 349         printk("Mem-info:\n");
 350         show_free_areas();
 351         printk("Free swap:       %6dkB\n",
 352                nr_swap_pages << (PAGE_SHIFT-10));
 353         printk("%ld pages of RAM\n", num_physpages);
 354         printk("%d free pages\n", nr_free_pages());
 355         printk("%d pages in page table cache\n",pgtable_cache_size);
 356 #ifndef CONFIG_SMP
 357         printk("%d entries in page dir cache\n",pgd_cache_size);
 358 #endif
 359 }
 360
 361 void mmu_info(struct seq_file *m)
 362 {
 363         if (tlb_type == cheetah)
 364                 seq_printf(m, "MMU Type\t: Cheetah\n");
 365         else if (tlb_type == cheetah_plus)
 366                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 367         else if (tlb_type == spitfire)
 368                 seq_printf(m, "MMU Type\t: Spitfire\n");
 369         else
 370                 seq_printf(m, "MMU Type\t: ???\n");
 371
 372 #ifdef CONFIG_DEBUG_DCFLUSH
 373         seq_printf(m, "DCPageFlushes\t: %d\n",
 374                    atomic_read(&dcpage_flushes));
 375 #ifdef CONFIG_SMP
 376         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 377                    atomic_read(&dcpage_flushes_xcall));
 378 #endif /* CONFIG_SMP */
 379 #endif /* CONFIG_DEBUG_DCFLUSH */
 380 }
 381
 382 struct linux_prom_translation {
 383         unsigned long virt;
 384         unsigned long size;
 385         unsigned long data;
 386 };
 387
 388 extern unsigned long prom_boot_page;
 389 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 390 extern int prom_get_mmu_ihandle(void);
 391 extern void register_prom_callbacks(void);
 392
 393 /* Exported for SMP bootup purposes. */
 394 unsigned long kern_locked_tte_data;
 395
 396 void __init early_pgtable_allocfail(char *type)
 397 {
 398         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 399         prom_halt();
 400 }
 401
 402 #define BASE_PAGE_SIZE 8192
 403 static pmd_t *prompmd;
 404
 405 /*
 406  * Translate PROM's mapping we capture at boot time into physical address.
 407  * The second parameter is only set from prom_callback() invocations.
 408  */
 409 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 410 {
 411         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 412         pte_t *ptep;
 413         unsigned long base;
 414
 415         if (pmd_none(*pmdp)) {
 416                 if (error)
 417                         *error = 1;
 418                 return(0);
 419         }
 420         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 421         if (!pte_present(*ptep)) {
 422                 if (error)
 423                         *error = 1;
 424                 return(0);
 425         }
 426         if (error) {
 427                 *error = 0;
 428                 return(pte_val(*ptep));
 429         }
 430         base = pte_val(*ptep) & _PAGE_PADDR;
 431         return(base + (promva & (BASE_PAGE_SIZE - 1)));
 432 }
 433
 434 static void inherit_prom_mappings(void)
 435 {
 436         struct linux_prom_translation *trans;
 437         unsigned long phys_page, tte_vaddr, tte_data;
 438         void (*remap_func)(unsigned long, unsigned long, int);
 439         pmd_t *pmdp;
 440         pte_t *ptep;
 441         int node, n, i, tsz;
 442         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
 443
 444         node = prom_finddevice("/virtual-memory");
 445         n = prom_getproplen(node, "translations");
 446         if (n == 0 || n == -1) {
 447                 prom_printf("Couldn't get translation property\n");
 448                 prom_halt();
 449         }
 450         n += 5 * sizeof(struct linux_prom_translation);
 451         for (tsz = 1; tsz < n; tsz <<= 1)
 452                 /* empty */;
 453         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
 454         if (trans == NULL) {
 455                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
 456                 prom_halt();
 457         }
 458         memset(trans, 0, tsz);
 459
 460         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 461                 prom_printf("Couldn't get translation property\n");
 462                 prom_halt();
 463         }
 464         n = n / sizeof(*trans);
 465
 466         /*
 467          * The obp translations are saved based on 8k pagesize, since obp can use
 468          * a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000, ie obp
 469          * range, are handled in entry.S and do not use the vpte scheme (see rant
 470          * in inherit_locked_prom_mappings()).
 471          */
 472 #define OBP_PMD_SIZE 2048
 473         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
 474         if (prompmd == NULL)
 475                 early_pgtable_allocfail("pmd");
 476         memset(prompmd, 0, OBP_PMD_SIZE);
 477         for (i = 0; i < n; i++) {
 478                 unsigned long vaddr;
 479
 480                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
 481                         for (vaddr = trans[i].virt;
 482                              ((vaddr < trans[i].virt + trans[i].size) &&
 483                              (vaddr < HI_OBP_ADDRESS));
 484                              vaddr += BASE_PAGE_SIZE) {
 485                                 unsigned long val;
 486
 487                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
 488                                 if (pmd_none(*pmdp)) {
 489                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
 490                                                                BASE_PAGE_SIZE,
 491                                                                bootmap_base);
 492                                         if (ptep == NULL)
 493                                                 early_pgtable_allocfail("pte");
 494                                         memset(ptep, 0, BASE_PAGE_SIZE);
 495                                         pmd_set(pmdp, ptep);
 496                                 }
 497                                 ptep = (pte_t *)__pmd_page(*pmdp) +
 498                                                 ((vaddr >> 13) & 0x3ff);
 499
 500                                 val = trans[i].data;
 501
 502                                 /* Clear diag TTE bits. */
 503                                 if (tlb_type == spitfire)
 504                                         val &= ~0x0003fe0000000000UL;
 505
 506                                 set_pte (ptep, __pte(val | _PAGE_MODIFIED));
 507                                 trans[i].data += BASE_PAGE_SIZE;
 508                         }
 509                 }
 510         }
 511         phys_page = __pa(prompmd);
 512         obp_iaddr_patch[0] |= (phys_page >> 10);
 513         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
 514         flushi((long)&obp_iaddr_patch[0]);
 515         obp_daddr_patch[0] |= (phys_page >> 10);
 516         obp_daddr_patch[1] |= (phys_page & 0x3ff);
 517         flushi((long)&obp_daddr_patch[0]);
 518
 519         /* Now fixup OBP's idea about where we really are mapped. */
 520         prom_printf("Remapping the kernel... ");
 521
 522         /* Spitfire Errata #32 workaround */
 523         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 524                              "flush     %%g6"
 525                              : /* No outputs */
 526                              : "r" (0),
 527                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 528
 529         switch (tlb_type) {
 530         default:
 531         case spitfire:
 532                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 533                 break;
 534
 535         case cheetah:
 536         case cheetah_plus:
 537                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
 538                 break;
 539         };
 540
 541         phys_page &= _PAGE_PADDR;
 542         phys_page += ((unsigned long)&prom_boot_page -
 543                       (unsigned long)KERNBASE);
 544
 545         if (tlb_type == spitfire) {
 546                 /* Lock this into i/d tlb entry 59 */
 547                 __asm__ __volatile__(
 548                         "stxa   %%g0, [%2] %3\n\t"
 549                         "stxa   %0, [%1] %4\n\t"
 550                         "membar #Sync\n\t"
 551                         "flush  %%g6\n\t"
 552                         "stxa   %%g0, [%2] %5\n\t"
 553                         "stxa   %0, [%1] %6\n\t"
 554                         "membar #Sync\n\t"
 555                         "flush  %%g6"
 556                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 557                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 558                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
 559                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 560                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 561                         : "memory");
 562         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 563                 /* Lock this into i/d tlb-0 entry 11 */
 564                 __asm__ __volatile__(
 565                         "stxa   %%g0, [%2] %3\n\t"
 566                         "stxa   %0, [%1] %4\n\t"
 567                         "membar #Sync\n\t"
 568                         "flush  %%g6\n\t"
 569                         "stxa   %%g0, [%2] %5\n\t"
 570                         "stxa   %0, [%1] %6\n\t"
 571                         "membar #Sync\n\t"
 572                         "flush  %%g6"
 573                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 574                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 575                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
 576                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 577                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 578                         : "memory");
 579         } else {
 580                 /* Implement me :-) */
 581                 BUG();
 582         }
 583
 584         tte_vaddr = (unsigned long) KERNBASE;
 585
 586         /* Spitfire Errata #32 workaround */
 587         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 588                              "flush     %%g6"
 589                              : /* No outputs */
 590                              : "r" (0),
 591                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 592
 593         if (tlb_type == spitfire)
 594                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 595         else
 596                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
 597
 598         kern_locked_tte_data = tte_data;
 599
 600         remap_func = (void *)  ((unsigned long) &prom_remap -
 601                                 (unsigned long) &prom_boot_page);
 602
 603
 604         /* Spitfire Errata #32 workaround */
 605         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 606                              "flush     %%g6"
 607                              : /* No outputs */
 608                              : "r" (0),
 609                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 610
 611         remap_func((tlb_type == spitfire ?
 612                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
 613                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
 614                    (unsigned long) KERNBASE,
 615                    prom_get_mmu_ihandle());
 616
 617         if (bigkernel)
 618                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
 619                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
 620
 621         /* Flush out that temporary mapping. */
 622         spitfire_flush_dtlb_nucleus_page(0x0);
 623         spitfire_flush_itlb_nucleus_page(0x0);
 624
 625         /* Now lock us back into the TLBs via OBP. */
 626         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 627         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 628         if (bigkernel) {
 629                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 630                                                                 tte_vaddr + 0x400000);
 631                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 632                                                                 tte_vaddr + 0x400000);
 633         }
 634
 635         /* Re-read translations property. */
 636         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 637                 prom_printf("Couldn't get translation property\n");
 638                 prom_halt();
 639         }
 640         n = n / sizeof(*trans);
 641
 642         for (i = 0; i < n; i++) {
 643                 unsigned long vaddr = trans[i].virt;
 644                 unsigned long size = trans[i].size;
 645
 646                 if (vaddr < 0xf0000000UL) {
 647                         unsigned long avoid_start = (unsigned long) KERNBASE;
 648                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
 649
 650                         if (bigkernel)
 651                                 avoid_end += (4 * 1024 * 1024);
 652                         if (vaddr < avoid_start) {
 653                                 unsigned long top = vaddr + size;
 654
 655                                 if (top > avoid_start)
 656                                         top = avoid_start;
 657                                 prom_unmap(top - vaddr, vaddr);
 658                         }
 659                         if ((vaddr + size) > avoid_end) {
 660                                 unsigned long bottom = vaddr;
 661
 662                                 if (bottom < avoid_end)
 663                                         bottom = avoid_end;
 664                                 prom_unmap((vaddr + size) - bottom, bottom);
 665                         }
 666                 }
 667         }
 668
 669         prom_printf("done.\n");
 670
 671         register_prom_callbacks();
 672 }
 673
 674 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 675  * upwards as reserved for use by the firmware (I wonder if this
 676  * will be the same on Cheetah...).  We use this virtual address
 677  * range for the VPTE table mappings of the nucleus so we need
 678  * to zap them when we enter the PROM.  -DaveM
 679  */
 680 static void __flush_nucleus_vptes(void)
 681 {
 682         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 683         int i;
 684
 685         /* Only DTLB must be checked for VPTE entries. */
 686         if (tlb_type == spitfire) {
 687                 for (i = 0; i < 63; i++) {
 688                         unsigned long tag;
 689
 690                         /* Spitfire Errata #32 workaround */
 691                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 692                                              "flush     %%g6"
 693                                              : /* No outputs */
 694                                              : "r" (0),
 695                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 696
 697                         tag = spitfire_get_dtlb_tag(i);
 698                         if (((tag & ~(PAGE_MASK)) == 0) &&
 699                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 700                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 701                                                      "membar #Sync"
 702                                                      : /* no outputs */
 703                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 704                                 spitfire_put_dtlb_data(i, 0x0UL);
 705                         }
 706                 }
 707         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 708                 for (i = 0; i < 512; i++) {
 709                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 710
 711                         if ((tag & ~PAGE_MASK) == 0 &&
 712                             (tag & PAGE_MASK) >= prom_reserved_base) {
 713                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 714                                                      "membar #Sync"
 715                                                      : /* no outputs */
 716                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 717                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 718                         }
 719
 720                         if (tlb_type != cheetah_plus)
 721                                 continue;
 722
 723                         tag = cheetah_get_dtlb_tag(i, 3);
 724
 725                         if ((tag & ~PAGE_MASK) == 0 &&
 726                             (tag & PAGE_MASK) >= prom_reserved_base) {
 727                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 728                                                      "membar #Sync"
 729                                                      : /* no outputs */
 730                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 731                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 732                         }
 733                 }
 734         } else {
 735                 /* Implement me :-) */
 736                 BUG();
 737         }
 738 }
 739
 740 static int prom_ditlb_set;
 741 struct prom_tlb_entry {
 742         int             tlb_ent;
 743         unsigned long   tlb_tag;
 744         unsigned long   tlb_data;
 745 };
 746 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 747
 748 void prom_world(int enter)
 749 {
 750         unsigned long pstate;
 751         int i;
 752
 753         if (!enter)
 754                 set_fs((mm_segment_t) { get_thread_current_ds() });
 755
 756         if (!prom_ditlb_set)
 757                 return;
 758
 759         /* Make sure the following runs atomically. */
 760         __asm__ __volatile__("flushw\n\t"
 761                              "rdpr      %%pstate, %0\n\t"
 762                              "wrpr      %0, %1, %%pstate"
 763                              : "=r" (pstate)
 764                              : "i" (PSTATE_IE));
 765
 766         if (enter) {
 767                 /* Kick out nucleus VPTEs. */
 768                 __flush_nucleus_vptes();
 769
 770                 /* Install PROM world. */
 771                 for (i = 0; i < 16; i++) {
 772                         if (prom_dtlb[i].tlb_ent != -1) {
 773                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 774                                                      "membar #Sync"
 775                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 776                                         "i" (ASI_DMMU));
 777                                 if (tlb_type == spitfire)
 778                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 779                                                                prom_dtlb[i].tlb_data);
 780                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 781                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 782                                                                prom_dtlb[i].tlb_data);
 783                         }
 784                         if (prom_itlb[i].tlb_ent != -1) {
 785                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 786                                                      "membar #Sync"
 787                                                      : : "r" (prom_itlb[i].tlb_tag),
 788                                                      "r" (TLB_TAG_ACCESS),
 789                                                      "i" (ASI_IMMU));
 790                                 if (tlb_type == spitfire)
 791                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 792                                                                prom_itlb[i].tlb_data);
 793                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 794                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 795                                                                prom_itlb[i].tlb_data);
 796                         }
 797                 }
 798         } else {
 799                 for (i = 0; i < 16; i++) {
 800                         if (prom_dtlb[i].tlb_ent != -1) {
 801                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 802                                                      "membar #Sync"
 803                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 804                                 if (tlb_type == spitfire)
 805                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 806                                 else
 807                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 808                         }
 809                         if (prom_itlb[i].tlb_ent != -1) {
 810                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 811                                                      "membar #Sync"
 812                                                      : : "r" (TLB_TAG_ACCESS),
 813                                                      "i" (ASI_IMMU));
 814                                 if (tlb_type == spitfire)
 815                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 816                                 else
 817                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 818                         }
 819                 }
 820         }
 821         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 822                              : : "r" (pstate));
 823 }
 824
 825 void inherit_locked_prom_mappings(int save_p)
 826 {
 827         int i;
 828         int dtlb_seen = 0;
 829         int itlb_seen = 0;
 830
 831         /* Fucking losing PROM has more mappings in the TLB, but
 832          * it (conveniently) fails to mention any of these in the
 833          * translations property.  The only ones that matter are
 834          * the locked PROM tlb entries, so we impose the following
 835          * irrecovable rule on the PROM, it is allowed 8 locked
 836          * entries in the ITLB and 8 in the DTLB.
 837          *
 838          * Supposedly the upper 16GB of the address space is
 839          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 840          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 841          * used between the client program and the firmware on sun5
 842          * systems to coordinate mmu mappings is also COMPLETELY
 843          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 844          */
 845         if (save_p) {
 846                 for (i = 0; i < 16; i++) {
 847                         prom_itlb[i].tlb_ent = -1;
 848                         prom_dtlb[i].tlb_ent = -1;
 849                 }
 850         }
 851         if (tlb_type == spitfire) {
 852                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
 853                 for (i = 0; i < high; i++) {
 854                         unsigned long data;
 855
 856                         /* Spitfire Errata #32 workaround */
 857                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 858                                              "flush     %%g6"
 859                                              : /* No outputs */
 860                                              : "r" (0),
 861                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 862
 863                         data = spitfire_get_dtlb_data(i);
 864                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 865                                 unsigned long tag;
 866
 867                                 /* Spitfire Errata #32 workaround */
 868                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 869                                                      "flush     %%g6"
 870                                                      : /* No outputs */
 871                                                      : "r" (0),
 872                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 873
 874                                 tag = spitfire_get_dtlb_tag(i);
 875                                 if (save_p) {
 876                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 877                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 878                                         prom_dtlb[dtlb_seen].tlb_data = data;
 879                                 }
 880                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 881                                                      "membar #Sync"
 882                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 883                                 spitfire_put_dtlb_data(i, 0x0UL);
 884
 885                                 dtlb_seen++;
 886                                 if (dtlb_seen > 15)
 887                                         break;
 888                         }
 889                 }
 890
 891                 for (i = 0; i < high; i++) {
 892                         unsigned long data;
 893
 894                         /* Spitfire Errata #32 workaround */
 895                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 896                                              "flush     %%g6"
 897                                              : /* No outputs */
 898                                              : "r" (0),
 899                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 900
 901                         data = spitfire_get_itlb_data(i);
 902                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 903                                 unsigned long tag;
 904
 905                                 /* Spitfire Errata #32 workaround */
 906                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 907                                                      "flush     %%g6"
 908                                                      : /* No outputs */
 909                                                      : "r" (0),
 910                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 911
 912                                 tag = spitfire_get_itlb_tag(i);
 913                                 if (save_p) {
 914                                         prom_itlb[itlb_seen].tlb_ent = i;
 915                                         prom_itlb[itlb_seen].tlb_tag = tag;
 916                                         prom_itlb[itlb_seen].tlb_data = data;
 917                                 }
 918                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 919                                                      "membar #Sync"
 920                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 921                                 spitfire_put_itlb_data(i, 0x0UL);
 922
 923                                 itlb_seen++;
 924                                 if (itlb_seen > 15)
 925                                         break;
 926                         }
 927                 }
 928         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 929                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
 930
 931                 for (i = 0; i < high; i++) {
 932                         unsigned long data;
 933
 934                         data = cheetah_get_ldtlb_data(i);
 935                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 936                                 unsigned long tag;
 937
 938                                 tag = cheetah_get_ldtlb_tag(i);
 939                                 if (save_p) {
 940                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 941                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 942                                         prom_dtlb[dtlb_seen].tlb_data = data;
 943                                 }
 944                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 945                                                      "membar #Sync"
 946                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 947                                 cheetah_put_ldtlb_data(i, 0x0UL);
 948
 949                                 dtlb_seen++;
 950                                 if (dtlb_seen > 15)
 951                                         break;
 952                         }
 953                 }
 954
 955                 for (i = 0; i < high; i++) {
 956                         unsigned long data;
 957
 958                         data = cheetah_get_litlb_data(i);
 959                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 960                                 unsigned long tag;
 961
 962                                 tag = cheetah_get_litlb_tag(i);
 963                                 if (save_p) {
 964                                         prom_itlb[itlb_seen].tlb_ent = i;
 965                                         prom_itlb[itlb_seen].tlb_tag = tag;
 966                                         prom_itlb[itlb_seen].tlb_data = data;
 967                                 }
 968                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 969                                                      "membar #Sync"
 970                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 971                                 cheetah_put_litlb_data(i, 0x0UL);
 972
 973                                 itlb_seen++;
 974                                 if (itlb_seen > 15)
 975                                         break;
 976                         }
 977                 }
 978         } else {
 979                 /* Implement me :-) */
 980                 BUG();
 981         }
 982         if (save_p)
 983                 prom_ditlb_set = 1;
 984 }
 985
 986 /* Give PROM back his world, done during reboots... */
 987 void prom_reload_locked(void)
 988 {
 989         int i;
 990
 991         for (i = 0; i < 16; i++) {
 992                 if (prom_dtlb[i].tlb_ent != -1) {
 993                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 994                                              "membar #Sync"
 995                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 996                                 "i" (ASI_DMMU));
 997                         if (tlb_type == spitfire)
 998                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 999                                                        prom_dtlb[i].tlb_data);
1000                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1001                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
1002                                                       prom_dtlb[i].tlb_data);
1003                 }
1004
1005                 if (prom_itlb[i].tlb_ent != -1) {
1006                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1007                                              "membar #Sync"
1008                                              : : "r" (prom_itlb[i].tlb_tag),
1009                                              "r" (TLB_TAG_ACCESS),
1010                                              "i" (ASI_IMMU));
1011                         if (tlb_type == spitfire)
1012                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
1013                                                        prom_itlb[i].tlb_data);
1014                         else
1015                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
1016                                                        prom_itlb[i].tlb_data);
1017                 }
1018         }
1019 }
1020
1021 void __flush_dcache_range(unsigned long start, unsigned long end)
1022 {
1023         unsigned long va;
1024
1025         if (tlb_type == spitfire) {
1026                 int n = 0;
1027
1028                 for (va = start; va < end; va += 32) {
1029                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
1030                         if (++n >= 512)
1031                                 break;
1032                 }
1033         } else {
1034                 start = __pa(start);
1035                 end = __pa(end);
1036                 for (va = start; va < end; va += 32)
1037                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1038                                              "membar #Sync"
1039                                              : /* no outputs */
1040                                              : "r" (va),
1041                                                "i" (ASI_DCACHE_INVALIDATE));
1042         }
1043 }
1044
1045 /* If not locked, zap it. */
1046 void __flush_tlb_all(void)
1047 {
1048         unsigned long pstate;
1049         int i;
1050
1051         __asm__ __volatile__("flushw\n\t"
1052                              "rdpr      %%pstate, %0\n\t"
1053                              "wrpr      %0, %1, %%pstate"
1054                              : "=r" (pstate)
1055                              : "i" (PSTATE_IE));
1056         if (tlb_type == spitfire) {
1057                 for (i = 0; i < 64; i++) {
1058                         /* Spitfire Errata #32 workaround */
1059                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1060                                              "flush     %%g6"
1061                                              : /* No outputs */
1062                                              : "r" (0),
1063                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1064
1065                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1066                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1067                                                      "membar #Sync"
1068                                                      : /* no outputs */
1069                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1070                                 spitfire_put_dtlb_data(i, 0x0UL);
1071                         }
1072
1073                         /* Spitfire Errata #32 workaround */
1074                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1075                                              "flush     %%g6"
1076                                              : /* No outputs */
1077                                              : "r" (0),
1078                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1079
1080                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1081                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1082                                                      "membar #Sync"
1083                                                      : /* no outputs */
1084                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1085                                 spitfire_put_itlb_data(i, 0x0UL);
1086                         }
1087                 }
1088         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1089                 cheetah_flush_dtlb_all();
1090                 cheetah_flush_itlb_all();
1091         }
1092         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1093                              : : "r" (pstate));
1094 }
1095
1096 /* Caller does TLB context flushing on local CPU if necessary.
1097  * The caller also ensures that CTX_VALID(mm->context) is false.
1098  *
1099  * We must be careful about boundary cases so that we never
1100  * let the user have CTX 0 (nucleus) or we ever use a CTX
1101  * version of zero (and thus NO_CONTEXT would not be caught
1102  * by version mis-match tests in mmu_context.h).
1103  */
1104 void get_new_mmu_context(struct mm_struct *mm)
1105 {
1106         unsigned long ctx, new_ctx;
1107
1108         spin_lock(&ctx_alloc_lock);
1109         ctx = CTX_HWBITS(tlb_context_cache + 1);
1110         new_ctx = find_next_zero_bit(mmu_context_bmap, 1UL << CTX_VERSION_SHIFT, ctx);
1111         if (new_ctx >= (1UL << CTX_VERSION_SHIFT)) {
1112                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1113                 if (new_ctx >= ctx) {
1114                         int i;
1115                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1116                                 CTX_FIRST_VERSION;
1117                         if (new_ctx == 1)
1118                                 new_ctx = CTX_FIRST_VERSION;
1119
1120                         /* Don't call memset, for 16 entries that's just
1121                          * plain silly...
1122                          */
1123                         mmu_context_bmap[0] = 3;
1124                         mmu_context_bmap[1] = 0;
1125                         mmu_context_bmap[2] = 0;
1126                         mmu_context_bmap[3] = 0;
1127                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1128                                 mmu_context_bmap[i + 0] = 0;
1129                                 mmu_context_bmap[i + 1] = 0;
1130                                 mmu_context_bmap[i + 2] = 0;
1131                                 mmu_context_bmap[i + 3] = 0;
1132                         }
1133                         goto out;
1134                 }
1135         }
1136         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1137         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1138 out:
1139         tlb_context_cache = new_ctx;
1140         spin_unlock(&ctx_alloc_lock);
1141
1142         mm->context = new_ctx;
1143 }
1144
1145 #ifndef CONFIG_SMP
1146 struct pgtable_cache_struct pgt_quicklists;
1147 #endif
1148
1149 /* OK, we have to color these pages. The page tables are accessed
1150  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1151  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1152  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1153  * fast handlers do not get data from old/garbage dcache lines that
1154  * correspond to an old/stale virtual address (user/kernel) that
1155  * previously mapped the pagetable page while accessing vpte range
1156  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1157  * color is the same, then when the kernel initializes the pagetable
1158  * using the later address range, accesses with the first address
1159  * range will see the newly initialized data rather than the garbage.
1160  */
1161 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1162 #define DC_ALIAS_SHIFT  1
1163 #else
1164 #define DC_ALIAS_SHIFT  0
1165 #endif
1166 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1167 {
1168         struct page *page;
1169         unsigned long color;
1170
1171         {
1172                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1173
1174                 if (ptep)
1175                         return ptep;
1176         }
1177
1178         color = VPTE_COLOR(address);
1179         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1180         if (page) {
1181                 unsigned long *to_free;
1182                 unsigned long paddr;
1183                 pte_t *pte;
1184
1185 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1186                 set_page_count(page, 1);
1187                 ClearPageCompound(page);
1188
1189                 set_page_count((page + 1), 1);
1190                 ClearPageCompound(page + 1);
1191 #endif
1192                 paddr = (unsigned long) page_address(page);
1193                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1194
1195                 if (!color) {
1196                         pte = (pte_t *) paddr;
1197                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1198                 } else {
1199                         pte = (pte_t *) (paddr + PAGE_SIZE);
1200                         to_free = (unsigned long *) paddr;
1201                 }
1202
1203 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1204                 /* Now free the other one up, adjust cache size. */
1205                 preempt_disable();
1206                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1207                 pte_quicklist[color ^ 0x1] = to_free;
1208                 pgtable_cache_size++;
1209                 preempt_enable();
1210 #endif
1211
1212                 return pte;
1213         }
1214         return NULL;
1215 }
1216
1217 void sparc_ultra_dump_itlb(void)
1218 {
1219         int slot;
1220
1221         if (tlb_type == spitfire) {
1222                 printk ("Contents of itlb: ");
1223                 for (slot = 0; slot < 14; slot++) printk ("    ");
1224                 printk ("%2x:%016lx,%016lx\n",
1225                         0,
1226                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1227                 for (slot = 1; slot < 64; slot+=3) {
1228                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1229                                 slot,
1230                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1231                                 slot+1,
1232                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1233                                 slot+2,
1234                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1235                 }
1236         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1237                 printk ("Contents of itlb0:\n");
1238                 for (slot = 0; slot < 16; slot+=2) {
1239                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1240                                 slot,
1241                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1242                                 slot+1,
1243                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1244                 }
1245                 printk ("Contents of itlb2:\n");
1246                 for (slot = 0; slot < 128; slot+=2) {
1247                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1248                                 slot,
1249                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1250                                 slot+1,
1251                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1252                 }
1253         }
1254 }
1255
1256 void sparc_ultra_dump_dtlb(void)
1257 {
1258         int slot;
1259
1260         if (tlb_type == spitfire) {
1261                 printk ("Contents of dtlb: ");
1262                 for (slot = 0; slot < 14; slot++) printk ("    ");
1263                 printk ("%2x:%016lx,%016lx\n", 0,
1264                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1265                 for (slot = 1; slot < 64; slot+=3) {
1266                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1267                                 slot,
1268                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1269                                 slot+1,
1270                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1271                                 slot+2,
1272                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1273                 }
1274         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1275                 printk ("Contents of dtlb0:\n");
1276                 for (slot = 0; slot < 16; slot+=2) {
1277                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1278                                 slot,
1279                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1280                                 slot+1,
1281                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1282                 }
1283                 printk ("Contents of dtlb2:\n");
1284                 for (slot = 0; slot < 512; slot+=2) {
1285                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1286                                 slot,
1287                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1288                                 slot+1,
1289                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1290                 }
1291                 if (tlb_type == cheetah_plus) {
1292                         printk ("Contents of dtlb3:\n");
1293                         for (slot = 0; slot < 512; slot+=2) {
1294                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1295                                         slot,
1296                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1297                                         slot+1,
1298                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1299                         }
1300                 }
1301         }
1302 }
1303
1304 extern unsigned long cmdline_memory_size;
1305
1306 unsigned long __init bootmem_init(unsigned long *pages_avail)
1307 {
1308         unsigned long bootmap_size, start_pfn, end_pfn;
1309         unsigned long end_of_phys_memory = 0UL;
1310         unsigned long bootmap_pfn, bytes_avail, size;
1311         int i;
1312
1313 #ifdef CONFIG_DEBUG_BOOTMEM
1314         prom_printf("bootmem_init: Scan sp_banks, ");
1315 #endif
1316
1317         bytes_avail = 0UL;
1318         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1319                 end_of_phys_memory = sp_banks[i].base_addr +
1320                         sp_banks[i].num_bytes;
1321                 bytes_avail += sp_banks[i].num_bytes;
1322                 if (cmdline_memory_size) {
1323                         if (bytes_avail > cmdline_memory_size) {
1324                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1325
1326                                 bytes_avail -= slack;
1327                                 end_of_phys_memory -= slack;
1328
1329                                 sp_banks[i].num_bytes -= slack;
1330                                 if (sp_banks[i].num_bytes == 0) {
1331                                         sp_banks[i].base_addr = 0xdeadbeef;
1332                                 } else {
1333                                         sp_banks[i+1].num_bytes = 0;
1334                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1335                                 }
1336                                 break;
1337                         }
1338                 }
1339         }
1340
1341         *pages_avail = bytes_avail >> PAGE_SHIFT;
1342
1343         /* Start with page aligned address of last symbol in kernel
1344          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1345          * 4MB locked TLB translation.
1346          */
1347         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1348
1349         bootmap_pfn = start_pfn;
1350
1351         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1352
1353 #ifdef CONFIG_BLK_DEV_INITRD
1354         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1355         if (sparc_ramdisk_image) {
1356                 if (sparc_ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1357                         sparc_ramdisk_image -= KERNBASE;
1358                 initrd_start = sparc_ramdisk_image + phys_base;
1359                 initrd_end = initrd_start + sparc_ramdisk_size;
1360                 if (initrd_end > end_of_phys_memory) {
1361                         printk(KERN_CRIT "initrd extends beyond end of memory "
1362                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1363                                initrd_end, end_of_phys_memory);
1364                         initrd_start = 0;
1365                 }
1366                 if (initrd_start) {
1367                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1368                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1369                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1370                 }
1371         }
1372 #endif
1373         /* Initialize the boot-time allocator. */
1374         max_pfn = max_low_pfn = end_pfn;
1375         min_low_pfn = pfn_base;
1376
1377 #ifdef CONFIG_DEBUG_BOOTMEM
1378         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1379                     min_low_pfn, bootmap_pfn, max_low_pfn);
1380 #endif
1381         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1382
1383         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1384
1385         /* Now register the available physical memory with the
1386          * allocator.
1387          */
1388         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1389 #ifdef CONFIG_DEBUG_BOOTMEM
1390                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1391                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1392 #endif
1393                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1394         }
1395
1396 #ifdef CONFIG_BLK_DEV_INITRD
1397         if (initrd_start) {
1398                 size = initrd_end - initrd_start;
1399
1400                 /* Resert the initrd image area. */
1401                 reserve_bootmem(initrd_start, size);
1402                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1403
1404                 initrd_start += PAGE_OFFSET;
1405                 initrd_end += PAGE_OFFSET;
1406         }
1407 #endif
1408         /* Reserve the kernel text/data/bss. */
1409 #ifdef CONFIG_DEBUG_BOOTMEM
1410         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1411 #endif
1412         reserve_bootmem(kern_base, kern_size);
1413         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1414
1415         /* Reserve the bootmem map.   We do not account for it
1416          * in pages_avail because we will release that memory
1417          * in free_all_bootmem.
1418          */
1419         size = bootmap_size;
1420 #ifdef CONFIG_DEBUG_BOOTMEM
1421         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1422                     (bootmap_pfn << PAGE_SHIFT), size);
1423 #endif
1424         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1425         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1426
1427         return end_pfn;
1428 }
1429
1430 /* paging_init() sets up the page tables */
1431
1432 extern void cheetah_ecache_flush_init(void);
1433
1434 static unsigned long last_valid_pfn;
1435
1436 void __init paging_init(void)
1437 {
1438         extern pmd_t swapper_pmd_dir[1024];
1439         extern unsigned int sparc64_vpte_patchme1[1];
1440         extern unsigned int sparc64_vpte_patchme2[1];
1441         unsigned long alias_base = kern_base + PAGE_OFFSET;
1442         unsigned long second_alias_page = 0;
1443         unsigned long pt, flags, end_pfn, pages_avail;
1444         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1445         unsigned long real_end;
1446
1447         set_bit(0, mmu_context_bmap);
1448
1449         real_end = (unsigned long)_end;
1450         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1451                 bigkernel = 1;
1452 #ifdef CONFIG_BLK_DEV_INITRD
1453         if (sparc_ramdisk_image)
1454                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1455 #endif
1456
1457         /* We assume physical memory starts at some 4mb multiple,
1458          * if this were not true we wouldn't boot up to this point
1459          * anyways.
1460          */
1461         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1462         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1463         local_irq_save(flags);
1464         if (tlb_type == spitfire) {
1465                 __asm__ __volatile__(
1466         "       stxa    %1, [%0] %3\n"
1467         "       stxa    %2, [%5] %4\n"
1468         "       membar  #Sync\n"
1469         "       flush   %%g6\n"
1470         "       nop\n"
1471         "       nop\n"
1472         "       nop\n"
1473                 : /* No outputs */
1474                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1475                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1476                 : "memory");
1477                 if (real_end >= KERNBASE + 0x340000) {
1478                         second_alias_page = alias_base + 0x400000;
1479                         __asm__ __volatile__(
1480                 "       stxa    %1, [%0] %3\n"
1481                 "       stxa    %2, [%5] %4\n"
1482                 "       membar  #Sync\n"
1483                 "       flush   %%g6\n"
1484                 "       nop\n"
1485                 "       nop\n"
1486                 "       nop\n"
1487                         : /* No outputs */
1488                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1489                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1490                         : "memory");
1491                 }
1492         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1493                 __asm__ __volatile__(
1494         "       stxa    %1, [%0] %3\n"
1495         "       stxa    %2, [%5] %4\n"
1496         "       membar  #Sync\n"
1497         "       flush   %%g6\n"
1498         "       nop\n"
1499         "       nop\n"
1500         "       nop\n"
1501                 : /* No outputs */
1502                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1503                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1504                 : "memory");
1505                 if (real_end >= KERNBASE + 0x340000) {
1506                         second_alias_page = alias_base + 0x400000;
1507                         __asm__ __volatile__(
1508                 "       stxa    %1, [%0] %3\n"
1509                 "       stxa    %2, [%5] %4\n"
1510                 "       membar  #Sync\n"
1511                 "       flush   %%g6\n"
1512                 "       nop\n"
1513                 "       nop\n"
1514                 "       nop\n"
1515                         : /* No outputs */
1516                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1517                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1518                         : "memory");
1519                 }
1520         }
1521         local_irq_restore(flags);
1522
1523         /* Now set kernel pgd to upper alias so physical page computations
1524          * work.
1525          */
1526         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1527
1528         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1529
1530         /* Now can init the kernel/bad page tables. */
1531         pgd_set(&swapper_pg_dir[0], swapper_pmd_dir + (shift / sizeof(pgd_t)));
1532
1533         sparc64_vpte_patchme1[0] |=
1534                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1535         sparc64_vpte_patchme2[0] |=
1536                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1537         flushi((long)&sparc64_vpte_patchme1[0]);
1538
1539         /* Setup bootmem... */
1540         pages_avail = 0;
1541         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1542
1543         /* Inherit non-locked OBP mappings. */
1544         inherit_prom_mappings();
1545
1546         /* Ok, we can use our TLB miss and window trap handlers safely.
1547          * We need to do a quick peek here to see if we are on StarFire
1548          * or not, so setup_tba can setup the IRQ globals correctly (it
1549          * needs to get the hard smp processor id correctly).
1550          */
1551         {
1552                 extern void setup_tba(int);
1553                 setup_tba(this_is_starfire);
1554         }
1555
1556         inherit_locked_prom_mappings(1);
1557
1558         /* We only created DTLB mapping of this stuff. */
1559         spitfire_flush_dtlb_nucleus_page(alias_base);
1560         if (second_alias_page)
1561                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1562
1563         __flush_tlb_all();
1564
1565         {
1566                 unsigned long zones_size[MAX_NR_ZONES];
1567                 unsigned long zholes_size[MAX_NR_ZONES];
1568                 unsigned long npages;
1569                 int znum;
1570
1571                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1572                         zones_size[znum] = zholes_size[znum] = 0;
1573
1574                 npages = end_pfn - pfn_base;
1575                 zones_size[ZONE_DMA] = npages;
1576                 zholes_size[ZONE_DMA] = npages - pages_avail;
1577
1578                 free_area_init_node(0, &contig_page_data, NULL, zones_size,
1579                                     phys_base >> PAGE_SHIFT, zholes_size);
1580                 mem_map = contig_page_data.node_mem_map;
1581         }
1582
1583         device_scan();
1584 }
1585
1586 /* Ok, it seems that the prom can allocate some more memory chunks
1587  * as a side effect of some prom calls we perform during the
1588  * boot sequence.  My most likely theory is that it is from the
1589  * prom_set_traptable() call, and OBP is allocating a scratchpad
1590  * for saving client program register state etc.
1591  */
1592 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1593 {
1594         int swapi = 0;
1595         int i, mitr;
1596         unsigned long tmpaddr, tmpsize;
1597         unsigned long lowest;
1598
1599         for (i = 0; thislist[i].theres_more != 0; i++) {
1600                 lowest = thislist[i].start_adr;
1601                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1602                         if (thislist[mitr].start_adr < lowest) {
1603                                 lowest = thislist[mitr].start_adr;
1604                                 swapi = mitr;
1605                         }
1606                 if (lowest == thislist[i].start_adr)
1607                         continue;
1608                 tmpaddr = thislist[swapi].start_adr;
1609                 tmpsize = thislist[swapi].num_bytes;
1610                 for (mitr = swapi; mitr > i; mitr--) {
1611                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1612                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1613                 }
1614                 thislist[i].start_adr = tmpaddr;
1615                 thislist[i].num_bytes = tmpsize;
1616         }
1617 }
1618
1619 void __init rescan_sp_banks(void)
1620 {
1621         struct linux_prom64_registers memlist[64];
1622         struct linux_mlist_p1275 avail[64], *mlist;
1623         unsigned long bytes, base_paddr;
1624         int num_regs, node = prom_finddevice("/memory");
1625         int i;
1626
1627         num_regs = prom_getproperty(node, "available",
1628                                     (char *) memlist, sizeof(memlist));
1629         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1630         for (i = 0; i < num_regs; i++) {
1631                 avail[i].start_adr = memlist[i].phys_addr;
1632                 avail[i].num_bytes = memlist[i].reg_size;
1633                 avail[i].theres_more = &avail[i + 1];
1634         }
1635         avail[i - 1].theres_more = NULL;
1636         sort_memlist(avail);
1637
1638         mlist = &avail[0];
1639         i = 0;
1640         bytes = mlist->num_bytes;
1641         base_paddr = mlist->start_adr;
1642
1643         sp_banks[0].base_addr = base_paddr;
1644         sp_banks[0].num_bytes = bytes;
1645
1646         while (mlist->theres_more != NULL){
1647                 i++;
1648                 mlist = mlist->theres_more;
1649                 bytes = mlist->num_bytes;
1650                 if (i >= SPARC_PHYS_BANKS-1) {
1651                         printk ("The machine has more banks than "
1652                                 "this kernel can support\n"
1653                                 "Increase the SPARC_PHYS_BANKS "
1654                                 "setting (currently %d)\n",
1655                                 SPARC_PHYS_BANKS);
1656                         i = SPARC_PHYS_BANKS-1;
1657                         break;
1658                 }
1659
1660                 sp_banks[i].base_addr = mlist->start_adr;
1661                 sp_banks[i].num_bytes = mlist->num_bytes;
1662         }
1663
1664         i++;
1665         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1666         sp_banks[i].num_bytes = 0;
1667
1668         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1669                 sp_banks[i].num_bytes &= PAGE_MASK;
1670 }
1671
1672 static void __init taint_real_pages(void)
1673 {
1674         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1675         int i;
1676
1677         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1678                 saved_sp_banks[i].base_addr =
1679                         sp_banks[i].base_addr;
1680                 saved_sp_banks[i].num_bytes =
1681                         sp_banks[i].num_bytes;
1682         }
1683
1684         rescan_sp_banks();
1685
1686         /* Find changes discovered in the sp_bank rescan and
1687          * reserve the lost portions in the bootmem maps.
1688          */
1689         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1690                 unsigned long old_start, old_end;
1691
1692                 old_start = saved_sp_banks[i].base_addr;
1693                 old_end = old_start +
1694                         saved_sp_banks[i].num_bytes;
1695                 while (old_start < old_end) {
1696                         int n;
1697
1698                         for (n = 0; sp_banks[n].num_bytes; n++) {
1699                                 unsigned long new_start, new_end;
1700
1701                                 new_start = sp_banks[n].base_addr;
1702                                 new_end = new_start + sp_banks[n].num_bytes;
1703
1704                                 if (new_start <= old_start &&
1705                                     new_end >= (old_start + PAGE_SIZE)) {
1706                                         set_bit (old_start >> 22,
1707                                                  sparc64_valid_addr_bitmap);
1708                                         goto do_next_page;
1709                                 }
1710                         }
1711                         reserve_bootmem(old_start, PAGE_SIZE);
1712
1713                 do_next_page:
1714                         old_start += PAGE_SIZE;
1715                 }
1716         }
1717 }
1718
1719 void __init mem_init(void)
1720 {
1721         unsigned long codepages, datapages, initpages;
1722         unsigned long addr, last;
1723         int i;
1724
1725         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1726         i += 1;
1727         sparc64_valid_addr_bitmap = (unsigned long *)
1728                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1729         if (sparc64_valid_addr_bitmap == NULL) {
1730                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1731                 prom_halt();
1732         }
1733         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1734
1735         addr = PAGE_OFFSET + kern_base;
1736         last = PAGE_ALIGN(kern_size) + addr;
1737         while (addr < last) {
1738                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1739                 addr += PAGE_SIZE;
1740         }
1741
1742         taint_real_pages();
1743
1744         max_mapnr = last_valid_pfn - pfn_base;
1745         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1746
1747 #ifdef CONFIG_DEBUG_BOOTMEM
1748         prom_printf("mem_init: Calling free_all_bootmem().\n");
1749 #endif
1750         totalram_pages = num_physpages = free_all_bootmem() - 1;
1751
1752         /*
1753          * Set up the zero page, mark it reserved, so that page count
1754          * is not manipulated when freeing the page from user ptes.
1755          */
1756         mem_map_zero = alloc_pages(GFP_KERNEL, 0);
1757         if (mem_map_zero == NULL) {
1758                 prom_printf("paging_init: Cannot alloc zero page.\n");
1759                 prom_halt();
1760         }
1761         SetPageReserved(mem_map_zero);
1762         clear_page(page_address(mem_map_zero));
1763
1764         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1765         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1766         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1767         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1768         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1769         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1770
1771 #ifndef CONFIG_SMP
1772         {
1773                 /* Put empty_pg_dir on pgd_quicklist */
1774                 extern pgd_t empty_pg_dir[1024];
1775                 unsigned long addr = (unsigned long)empty_pg_dir;
1776                 unsigned long alias_base = kern_base + PAGE_OFFSET -
1777                         (long)(KERNBASE);
1778
1779                 memset(empty_pg_dir, 0, sizeof(empty_pg_dir));
1780                 addr += alias_base;
1781                 free_pgd_fast((pgd_t *)addr);
1782                 num_physpages++;
1783                 totalram_pages++;
1784         }
1785 #endif
1786
1787         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1788                nr_free_pages() << (PAGE_SHIFT-10),
1789                codepages << (PAGE_SHIFT-10),
1790                datapages << (PAGE_SHIFT-10),
1791                initpages << (PAGE_SHIFT-10),
1792                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1793
1794         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1795                 cheetah_ecache_flush_init();
1796 }
1797
1798 void free_initmem (void)
1799 {
1800         unsigned long addr, initend;
1801
1802         /*
1803          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1804          */
1805         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1806         initend = (unsigned long)(__init_end) & PAGE_MASK;
1807         for (; addr < initend; addr += PAGE_SIZE) {
1808                 unsigned long page;
1809                 struct page *p;
1810
1811                 page = (addr +
1812                         ((unsigned long) __va(kern_base)) -
1813                         ((unsigned long) KERNBASE));
1814                 p = virt_to_page(page);
1815
1816                 ClearPageReserved(p);
1817                 set_page_count(p, 1);
1818                 __free_page(p);
1819                 num_physpages++;
1820                 totalram_pages++;
1821         }
1822 }
1823
1824 #ifdef CONFIG_BLK_DEV_INITRD
1825 void free_initrd_mem(unsigned long start, unsigned long end)
1826 {
1827         if (start < end)
1828                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1829         for (; start < end; start += PAGE_SIZE) {
1830                 struct page *p = virt_to_page(start);
1831
1832                 ClearPageReserved(p);
1833                 set_page_count(p, 1);
1834                 __free_page(p);
1835                 num_physpages++;
1836                 totalram_pages++;
1837         }
1838 }
1839 #endif